JP7809588B2 - Radiation-resistant semiconductor device, radiation-resistant semiconductor device control method, and sensor system for nuclear power plant - Google Patents

Description

The present invention relates to a radiation-resistant semiconductor device, a control method for a radiation-resistant semiconductor device, and a sensor system for a nuclear power plant.

An example of a facility or equipment that needs to be protected in a radiation environment is a nuclear power plant.
The inside of the reactor containment vessel at a nuclear power plant is exposed to high levels of radiation (gamma rays).Even in such a high-radiation environment, it is necessary to operate sensors, measuring instruments, and various other devices to understand the situation for maintenance and decommissioning work.

Furthermore, even if the above-mentioned sensors and measuring instruments are placed in a high radiation environment area, the control unit that performs analysis and control, and the command unit that performs operation, must be placed in a low radiation environment area where the impact of radiation is minimal.
Therefore, sensor signals and the power lines for driving them are transmitted from inside the containment vessel to the outside of the reactor building via a penetration that spans between the containment vessel and the reactor building.
However, there is a limit to the number of wires that can pass through the penetration. Furthermore, signals that pass through the penetration generally have a poor signal-to-noise ratio because they have to travel through long wires (cables).
These circumstances make it difficult to manage and monitor the reactor containment vessel.

In light of the above background and circumstances, development is underway to develop radiation-resistant devices that use wide bandgap semiconductors, such as silicon carbide (SiC), which have a wider bandgap than silicon, as information processing devices and regulators for measuring instruments and sensors to be installed inside the reactor containment vessel.
In addition, in order to reduce the number of electrical wires that pass through the penetration, a method is used in which a multiplexer (multiplexer: multiplexing device, data selector) is installed inside the reactor containment vessel to reduce the number of signal wires that are taken out to the outside of the reactor containment vessel.

For example, Patent Document 1 relates to such a technology.
The Abstract of Patent Document 1 states, "[Problem] To simplify operation and improve the space factor, while also improving maintainability inside the reactor building and the reliability of equipment inside the reactor building. [Solution] A fixed in-reactor instrumentation device measures heat generation due to radiation absorption using a plurality of fixed sensors (10) fixed inside the reactor together with a detector that detects neutron flux levels, and performs neutron flux distribution measurement and sensitivity calibration using the measurement signals output from the fixed sensors (10). The reactor building (2) is provided with a plurality of multiplexer processing units (13) that selectively take in the measurement signals output from the plurality of fixed sensors (10) and convert them into transmission data in a predetermined format, and a plurality of heater control units (30) that control the temperatures of a plurality of heaters (10) installed inside the reactor to calibrate the fixed sensors (10). A signal processing unit (40) that receives transmission data from the multiplexer processing units (13) and monitors the measurement signals of the fixed sensors (10) is provided outside the reactor building near the central operating room."

Japanese Patent Application Publication No. 09-236687

However, in the configuration disclosed in Patent Document 1, the larger the integration scale of the transistors in the multiplexer, the more likely initial defects are to occur due to crystal defects in SiC when SiC is used, but no clear measures are taken to address this.
Furthermore, there are issues (problems) such as the fact that no clear consideration has been given to measures against fluctuations in V _th (threshold voltage) and leakage current caused by gamma rays in a nuclear reactor.
In the configuration disclosed in Patent Document 1, the multiplexer is assumed to be a general-purpose product, and there is no evidence that the above-mentioned problem has been taken into consideration.

The present invention was devised in light of the above-mentioned problems, and its objective is to provide a radiation-hardened semiconductor device equipped with a multiplexer that is radiation-resistant and has a high manufacturing yield.

In order to solve the above problems, the present invention is configured as follows.
That is, the radiation-hardened semiconductor device of the present invention comprises a large-scale multiplexer in which a plurality of unit multiplexers formed using silicon carbide are connected in a predetermined manner, and the large-scale multiplexer comprises a plurality of input signal lines connected to some of the plurality of unit multiplexers, and an output signal line output from one of the plurality of unit multiplexers, and is controlled by a control signal that is different from the unit multiplexer to which the output signal line is connected and the unit multiplexer to which the input signal line is connected, and the plurality of unit multiplexers are each formed from an independent chip piece , and are guaranteed to be good products in a preliminary inspection by screening for crystal defects in the silicon carbide .

Other means will also be described in the description of the invention.

The present invention provides a radiation-resistant semiconductor device equipped with a multiplexer that is radiation-resistant and has a high manufacturing yield.

1 is a diagram showing an example of a circuit configuration of a multiplexer included in a radiation-hard semiconductor device according to a first embodiment of the present invention; FIG. 1 is a diagram illustrating an example of a conceptual circuit configuration of a multiplexer having a basic configuration with four input signal lines, two control lines, and one output signal line. FIG. 1 is a diagram showing an example of an outline of a nuclear reactor premises. FIG. 1 is a diagram showing an example of the configuration of a multiplexer having ²ⁿ input signal lines, n control lines, and one output signal line. 10A and 10B are diagrams illustrating an example of the relationship between the number of control lines, the chip area, and the reduction effect. FIG. 1 is a diagram showing the relationship between defect density and yield in a SiC-IC chip. 1 is a diagram showing an example of a specific circuit configuration of a "multiplexer with a small chip area" having two control lines included in the radiation-hardened semiconductor device according to the first embodiment of the present invention; FIG. 10 is a diagram showing an example of a configuration in which a NOR circuit is configured as a CMOS circuit using pMOS and nMOS. 10 is a diagram showing an equation indicating the threshold voltage of a pMOS transistor M2 when the source potential of the transistor M2 is different from the substrate potential. FIG. 1 is a diagram illustrating an example of a circuit configuration on an nMOS side in a NAND circuit and a path in a state where leakage current occurs. 11 is a diagram showing an example of a pattern configuration on the nMOS side in the NAND circuit corresponding to FIG. 10 and a state in which leakage current occurs. FIG. 12 is a diagram showing an example of a countermeasure for preventing leakage current on the nMOS side in the NAND circuit corresponding to FIG. 11 ;

Below, modes for implementing the present invention (hereinafter referred to as "embodiments") will be described with reference to the drawings as appropriate.

First Embodiment: Part 1
An outline of the configuration of a radiation-hard semiconductor device according to a first embodiment of the present invention will be described as "first embodiment: part 1" with reference to FIGS. 1 and 2. FIG.
1 is a diagram showing an example of the circuit configuration of a multiplexer 101 (large-scale multiplexer) included in a radiation-hardened semiconductor device according to a first embodiment of the present invention. In FIG. 1, the multiplexer 101 (radiation-hardened semiconductor device) is configured to include 16 input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F , four control lines A ₀₀ , A ₀₁ , A ₀₂ and A ₀₃ , and an output terminal D.
FIG. 2 is a diagram showing an example of a conceptual circuit configuration of a multiplexer 201 (unit multiplexer) having a basic configuration with four input signal lines, two control lines, and one output signal line.

In FIG. 1, five multiplexers 201 (201A to 201D, 201S) each having the basic configuration of four input signal lines, two control lines, and one output signal line shown in FIG. 2 are combined to form a large-scale multiplexer 101 having 16 input signal lines, four control lines, and one output signal line.
Each of the five multiplexers 201 (201A to 201D, 201S) is made up of an independent chip.
Furthermore, the multiplexer 201 (201A to 201D, 201S) of the basic configuration is also referred to as a "unit multiplexer" as appropriate.
Additionally, the multiplexer 101 having a large-scale configuration is also referred to as a "large-scale multiplexer" as appropriate.

As will be described later, the five multiplexers 201 (201A to 201D, 201S) are configured as independent chip pieces in order to ensure a predetermined yield as an IC chip by manufacturing each multiplexer 201 small.
Then, five multiplexers 201 (unit multiplexers) that operate reliably are selected and combined to form the multiplexer 101 (large-scale multiplexer) shown in FIG.
Although the five multiplexers 201 (201A to 201D, 201S) are each configured as an independent chip, they share the same power supply system _Vdd and _Vss .

Details of the multiplexer 201 having four input signal lines, two control lines, and one output signal line shown in FIG. 2 and the multiplexer 101 having 16 input signal lines, four control lines, and one output signal line shown in FIG. 1 will be described later as "First Embodiment: Part 2."
Before that, we will explain the electronic equipment and signal transmission within the reactor premises and explain the situations in which the above-mentioned multiplexer is required.

<Outline of the reactor premises>
FIG. 3 is a diagram showing an example of an outline of a reactor premises 301 .
3, a reactor containment vessel 303 is located inside a reactor building 302, and a reactor pressure vessel 304 is located inside the reactor containment vessel 303. The insides of the reactor containment vessel 303 and the reactor pressure vessel 304 are high-dose radiation (gamma rays) areas. The outside of the reactor building 302 is a low-dose radiation area.

3, the outside of the boundary line (302) depicted as the reactor building 302 is also part of the reactor building, and a signal output unit 323 and a signal processing unit 324, which will be described later, are substantially provided within the "reactor building 302." However, to clearly express that this is a low-dose radiation region, the reactor building 302 may also be described as "the outside of the reactor building 302."
That is, inside the boundary line (302) described as the reactor building 302, there are provided a reactor containment vessel 303 and a reactor pressure vessel 304, which are high-dose radiation (gamma rays) areas. In contrast, outside the boundary line (302) described as "outside the reactor building 302" is a low-dose radiation area of the reactor building 302.

In a predetermined instrument installation area 312 in the reactor pressure vessel 304, a sensor group consisting of a plurality of sensors (312A, 312B) for measuring various information about the reactor is provided.
Furthermore, a signal transmission unit 320 including a multiplexer 321 that processes signals from the above-mentioned multiple measuring instruments and sensors and an amplifier 322 that amplifies the signals is provided inside the containment vessel 303. Then, a signal is output from the signal transmission unit 320 to a signal output unit 323 for a low-dose region.
The output signal from the signal output unit 323 is processed in a signal processing unit 324 provided outside the reactor building 302 .
Further, on the outside of the reactor building 302, there is a pressure suppression chamber 305 that controls the reactor.
Furthermore, the reactor building 302 and the containment vessel 303 are provided with a penetration 311 that passes a signal from the signal transmission unit 320 to the outside of the reactor building 302 .

As described above, sensor signals and power lines for driving them are input and output from inside the containment vessel 303 to the outside of the reactor building 302 via a penetration 311 between the containment vessel 303 and the reactor building 302.
However, due to the nature of a radioactive nuclear reactor facility, there is naturally a limit to the cross-sectional size of the penetration part 311. Therefore, there is a limit to the number of signal lines that can pass through the penetration part 311. For this reason, the number of signal lines can be reduced by passing the signals of the multiple signal lines through a multiplexer that is resistant to radiation.
Furthermore, the multiplexer 321 is susceptible to radiation because it is installed inside the containment vessel 303. For this reason, the multiplexer 321 uses SiC (Silicon Carbide), a wide bandgap semiconductor that is less susceptible to radiation.

First Embodiment: Part 2
1, 2, and 4 to 7, the configuration of the multiplexer according to the first embodiment of the present invention will be described in detail.

<Configuration and characteristics of multiplexers>
2 shows a unit multiplexer 201 with a basic configuration having four input signal lines, two control lines, and one output signal line. Also, FIG. 1 shows a multiplexer 101 with a large-scale configuration having 16 input signal lines, four control lines, and one output signal line. However, the specific configuration (circuit configuration) of a multiplexer varies.
Next, a desirable configuration for the number of input signal lines and control lines in a multiplexer for passing a small number of signal lines through a penetration 311 in a nuclear reactor facility will be examined and explained.
As an example of an element that constitutes a multiplexer, a MOSFET using SiC is assumed.

When manufacturing a multiplexer that takes radiation resistance into consideration, it is desirable to use SiC, which is highly radiation-resistant. However, SiC (silicon carbide) is prone to crystal defects because it is a material made of silicon (Si) crystals mixed with carbon (C). These crystal defects generally tend to reduce the manufacturing yield of SiC chips.
Therefore, taking into consideration the decrease in yield of the multiplexer due to this crystal defect, a desirable multiplexer configuration will be considered next.

4 shows an example of the configuration of a multiplexer having ²ⁿ input signal lines, n control lines, and one output signal line. In practice, two power supply lines (not shown) are also included.
In FIG. 4, there is a parameter n as input signal lines ( ²ⁿ lines) and control lines (n lines).
When configuring an actual multiplexer, the selection of the number of input signal lines and control lines has a significant impact on performance and cost. Therefore, next we will consider optimizing the parameter n for the control lines (n lines).

<Number of control lines, chip area, and reduction effect>
FIG. 5 is a diagram showing an example of the relationship between the number of "control lines", the "chip area", and the "effect of reducing the number of signal lines".
In Figure 5, the horizontal axis represents the number of control lines, and the vertical axis on the left represents the "signal line reduction effect" of the multiplexer, which is the total number of lines (control lines + power supply lines + output signal lines) divided by the number of lines (input signal lines).
Reduction in signal lines = (control lines + power lines + output signal lines) / (input signal lines)
is.
In FIG. 5, this relationship is shown by a curved graph with multiple circles and a solid line.
On the left vertical axis, the lower the value is from "1", the greater the effect of reducing the number of signal lines.

5, the vertical axis on the right side represents the "chip area based on a multiplexer with two control lines" and is simply referred to as "chip area." The unit is an arbitrary unit (a.u.).
5 shows this relationship as a curved graph with multiple squares and dashed lines, which indicates that as the number of control lines increases, the chip area of the multiplexer increases.

<<Defect Density and Yield>>
FIG. 6 is a diagram showing the relationship between defect density and yield in a SiC-IC chip.
6, the horizontal axis represents the defect density per 1 cm ² , that is, (defect density/cm ² ). Note that in FIG. 6, it is expressed as "defect density (cm ⁻² )."
The vertical axis indicates the yield of chips (SiC-IC) per 1 mm ^2. In Fig. 6, this is indicated as "yield (%)".
FIG. 6 shows that as the defect density of chips on the horizontal axis increases, the chip yield per unit area of 1 mm ² decreases.

<<Selecting the number of control lines for a multiplexer>>
5 and 6, an example of selection of the number of control lines of a multiplexer will be considered below.
5, increasing the number of control lines of the multiplexer causes a rapid increase in chip area, which reduces the yield of the chip (SiC-IC).
In other words, if a multiplexer with a large number of control lines is constructed in order to allow a small number of signal lines to pass through the penetration 311 in a nuclear reactor facility, the chip area will become large, which will result in a sharp drop in yield and increased costs.

To address this issue, multiplexers with small chip areas are first manufactured, and the manufactured small multiplexers are then inspected to eliminate any defective products.
As explained with reference to FIGS. 5 and 6, in the case of a multiplexer with a small chip area, the number of defective products is small.

Next, a number of small chip area multiplexers (unit multiplexers) that have been judged to be non-defective through this inspection and selection are combined to form and manufacture a large multiplexer with many control lines and high functionality.
With this method, all of the small unit multiplexers selected are guaranteed to be good products, and therefore the large-scale multiplexers with high functionality and many control lines that are constructed by combining these multiplexers are also guaranteed to be good products.
That is, a multiplexer with a large scale configuration and high functionality can be produced efficiently, reliably, and at low cost.

Specifically, as a "unit multiplexer with a small chip area," a multiplexer with two control lines is selected with reference to Figure 5. Referring to Figures 5 and 6, a "multiplexer with two control lines" has a small chip area, and therefore a high yield can be expected.
This "two control line multiplexer" is multiplexer 201 in FIG. 2 and multiplexer 201S in FIG.
Furthermore, a specific example of the circuit configuration of the selected small unit multiplexers is the circuit of a unit multiplexer 201 shown in FIG. 7, which will be described later.

Moreover, the "multiplexer 101" in FIG. 1 is an example of the above-mentioned "multiplexer having a large-scale configuration with many control lines and high functionality, which is formed by combining a plurality of unit multiplexers with small chip areas."
In FIG. 1, multiplexers 201A to 201D and multiplexer 201S are combined as "unit multiplexers with small chip area" to form "multiplexer 101," which is a "large-scale multiplexer with many control lines and high functionality."

It should be noted that the "multiplexer 101" in FIG. 1 has four control lines _A00 , _A01 , _A02 , and _A03 .
Also, although this roughly corresponds to the case of four control lines in FIG. 5, combining five "multiplexers 201 with small chip area" with two control lines leads to improved yield and lower costs.
In FIG. 5, the area where characteristic line 501, which shows the relationship between the number of control lines and the reduction effect of signal lines, and characteristic line 502, which shows the relationship between the number of control lines and the chip area, intersect corresponds to roughly four to six control lines.
That is, as mentioned above, the configuration of "multiplexer 101" in FIG. 1 has four control lines, which suggests that the configuration of multiplexer 101 in FIG. 1 is one effective solution that achieves both the effect of reducing control lines and signal lines and low costs.

<Specific circuit configuration of a "small chip area unit multiplexer" with two control lines>
FIG. 7 is a diagram showing an example of a specific circuit configuration of a "unit multiplexer with a small chip area" having two control lines provided in the radiation-hardened semiconductor device according to the first embodiment of the present invention.
7, the multiplexer 201 is shown as an example of the signal lines of the multiplexer 201S in FIG.
In FIG. 7, the multiplexer 201 is made up of a control section 221 and a switch section 231 .

<<Control Unit 221>>
The control section 221 is configured to include four NAND circuits 22NA1 to 22NA4, which are two-input NAND circuits, and six NOT circuits 22IN1 to 22IN6, which are inverter circuits (inverting circuits).
The control signal on the control line _A02 is input to a NAND circuit 22NA1, a NAND circuit 22NA3, and a NOT circuit 22IN5.
The control signal on the control line _A03 is input to a NAND circuit 22NA1, a NAND circuit 22NA2, and a NOT circuit 22IN6.
The output signal of the NOT circuit 22IN5 is input to a NAND circuit 22NA2 and a NAND circuit 22NA4.
The output signal of the NOT circuit 22IN6 is input to a NAND circuit 22NA3 and a NAND circuit 22NA4.

The output signal of the NAND circuit 22NA1 is input to a NOT circuit 22IN1.
The output signal of the NAND circuit 22NA2 is input to a NOT circuit 22IN2.
The output signal of the NAND circuit 22NA3 is input to a NOT circuit 22IN3.
The output signal of the NAND circuit 22NA4 is input to a NOT circuit 22IN4.

The control unit 221 outputs a pair of an output signal from the NAND circuit 22NA1 and an output signal from the NOT circuit 22IN1.
The control unit 221 outputs a pair of an output signal from the NAND circuit 22NA2 and an output signal from the NOT circuit 22IN2.
The control unit 221 outputs a pair of an output signal from the NAND circuit 22NA3 and an output signal from the NOT circuit 22IN3.
The control unit 221 outputs a pair of an output signal from the NAND circuit 22NA4 and an output signal from the NOT circuit 22IN4.

<<Switch section 231>>
7, the switch section 231 is configured with four bidirectional switches (analog switches, transmission gates) 23T1 to 23T4 that transmit analog signals to each other. The bidirectional switches are configured with transmission gates, for example, by connecting a pMOS and an nMOS in parallel. To turn the transmission gates on, a negative potential is applied to the gate of the pMOS, and a positive potential is applied to the gate of the nMOS. Conversely, to turn the transmission gates off, a positive potential is applied to the gate of the pMOS, and a negative potential is applied to the gate of the nMOS.

An input signal on an input signal line _S10 is input to the bidirectional switch 23T1, and is output to an output terminal D of the multiplexer 201. The bidirectional switch 23T1 is controlled to be turned on and off by a pair of signals, an output signal of a NAND circuit 22NA4 and an output signal of a NOT circuit 22IN4.
An input signal on the input signal line _S11 is input to the bidirectional switch 23T2, and is output to the output terminal D of the multiplexer 201. The bidirectional switch 23T2 is controlled to be turned on and off by a pair of signals, namely, the output signal of the NAND circuit 22NA3 and the output signal of the NOT circuit 22IN3.

An input signal on the input signal line _S12 is input to the bidirectional switch 23T3, and is output to the output terminal D of the multiplexer 201. The bidirectional switch 23T3 is controlled to be turned on and off by a pair of signals, namely, the output signal of the NAND circuit 22NA2 and the output signal of the NOT circuit 22IN2.
An input signal on the input signal line _S13 is input to the bidirectional switch 23T4, and is output to the output terminal D of the multiplexer 201. The bidirectional switch 23T4 is controlled to be turned on and off by a pair of signals, namely, the output signal of the NAND circuit 22NA1 and the output signal of the NOT circuit 22IN1.

As described above, the input signals on the input signal lines _S10 to _S13 are input to the bidirectional switches 23T1 to 23T4 of the switch unit 231, respectively, and one of the input signals _S10 to _S13 is selected by the control signal on the control lines _A02 to _A03 of the control unit 221, and output to the output terminal D of the multiplexer 201.
The input signals on the input signal lines S ₁₀ to S ₁₃ and the output signal from the output terminal D are generally analog signals, and the control signals on the control lines A ₀₂ to A ₀₃ are digital signals of 1 and 0.

1. The circuit configuration, input signals, and output signals of the multiplexer 201 shown in FIG. 7 are illustrated corresponding to the circuit configuration, input signals, and output signals of the multiplexer 201S in FIG.
Also, for example, in multiplexer 201A, by connecting _S00 to _S10 , _S01 to _S11 , _S02 to _S12 , and _S03 to _S13 on the input signal lines of multiplexer 201S, and by connecting _A00 to _A02 and _A01 to _A03 on the control lines, a small unit multiplexer with the same four inputs and one output can be configured, and the basic circuit configuration of Figure 7 can be shared.
That is, although the control signals and input signals of the multiplexers 201A to 201D in FIG. 1 are different, the circuit configuration corresponds to that in FIG. 7 and is substantially equivalent.

<Configuration and Operation of Multiplexer 101>
The configuration and operation of the multiplexer 101 shown in the circuit diagram of FIG. 1 will now be described in detail.
1 has 16 input signal lines, with input signal lines _S00 to _S09 and _S0A to _S0F connected to the respective input terminals, and four control lines, with control lines _A00 to _A03 connected to the respective input terminals.
The input signals on the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F are analog signals, and the control signals on the control lines A _{01 to} A ₀₃ are digital signals.

The first small unit multiplexer 201A has four input terminals, input signal lines _S00 to _S03 , to which four input signals are input, respectively. Also, two control signals are connected to two terminals, control lines _A00 and _A01 , respectively.
With this configuration, depending on the combination of control signals on control lines A ₀₀ and A ₀₁ , one of the input signals on input signal lines S ₀₀ to S ₀₃ is output from output signal line 211A connected to the output terminal (D) of the first small unit multiplexer 201A.

The second small unit multiplexer 201B has four input terminals, input signal lines _S04 to _S07 , to which four input signals are input, respectively. Also, two control signals are connected to two terminals, control lines _A00 and _A01 , respectively.
With this configuration, depending on the combination of control signals on control lines A ₀₀ and A ₀₁ , one of the input signals on input signal lines S ₀₄ to S ₀₇ is output from output signal line 211B connected to output terminal (D) of second small multiplexer 201B.

The third small unit multiplexer 201C has four input terminals, input signal lines _S08 to _S09 and _S0A to _S0B , each of which receives four input signals. Also, two control signals are connected to two terminals, control lines _A00 and _A01 .
With this configuration, depending on the combination of control signals on control lines A ₀₀ and A ₀₁ , one of the input signals on input signal lines S ₀₈ to S ₀₉ and S _0A to S _0B is output from output signal line 211C connected to output terminal (D) of the third small multiplexer 201C.

The fourth small unit multiplexer 201D has four input terminals, input signal lines _S0C to _S0F , to which four input signals are input, respectively. Also, two control signals are connected to two terminals, control lines _A00 and _A01 , respectively.
With this configuration, depending on the combination of control signals on control lines A ₀₀ and A ₀₁ , one of the input signals on input signal lines S _0C to S _0F is output from output signal line 211D connected to the output terminal (D) of the fourth small multiplexer 201D.
The input signal line S _0F of the fourth small multiplexer 201D is connected to the ground G. The reason for connecting this input signal line S _0F to the ground G will be described later.

As described above, by selecting the control signals on the two control lines A ₀₀ and A ₀₁ , four signals are output as output signal lines 211A to 211D from the output terminals D of the first to fourth small unit multiplexers 201A to 201D, respectively.
The four signals output to the output signal lines 211A to 211D are input to the four input terminals of the fifth small multiplexer 201S as four input signal lines S ₁₀ to S ₁₃ , respectively.
Furthermore, the fifth small unit multiplexer 201S is controlled by input signals on two control lines _A02 and _A03 . Depending on the selection of the control signals on the control lines _A02 and _A03 , one of the input signals on the input signal lines _S10 to _S13 is output to the output terminal D of the multiplexer 201S.

As described above, four signals are selected from the input signals on input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F by selecting the control signals on control lines A ₀₀ and A _01. Then, one signal is output to output terminal D of multiplexer 201S by selecting the control signals on control lines A ₀₂ and A ₀₃ .
The output terminal D of the multiplexer 201S is also the output terminal D of the multiplexer 101.
That is, the multiplexer 101 is composed of 16 input signal lines and 4 control lines, and one of the input signals on the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F is selected according to the combination of control signals on the control lines _{A 00} to A ₀₃ , and output to the output terminal D. The output signal from the output terminal D is passed through the penetration 311 of the reactor building 302.
In this way, by using the multiplexer 101, the number of signal lines passing through the through portion 311 can be reduced.

As described above, the input signals of the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F are analog signals, and the control signals of the control lines A _{01 to} A ₀₃ are digital signals. Also, the output signal of the output terminal D of the multiplexer 101 is an analog signal.
The input signals of the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F remain inside the containment vessel 303 and do not pass through the penetration 311 of the reactor building 302 .
However, the control signals of the control lines _{A01 to A03} and the output signal of the output terminal D of the multiplexer 101 must pass through a penetration 311 in the reactor building 302. The signal lines passing through the penetration 311 are relatively long and are in an environment susceptible to noise.

The control signals on the control lines _{A01 to A03} are digital signals and therefore are less susceptible to noise.
However, since the output signal from the output terminal D of the multiplexer 101 is an analog signal, measures are required to make it less susceptible to the effects of noise.
Next, a description will be given of noise countermeasures for the output signal of the multiplexer 101, which is an analog signal, and grasping of the switching timing.

<Noise countermeasures and timing understanding for analog multiplexer output signals>
1, the input signal line S _0F of the multiplexer 101 is connected to the ground G. Two reasons for connecting this input signal line S _0F to the ground G will be explained below.

1. Noise Countermeasures
The input signals on the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F have signal amplitudes as analog signals with the ground G as the reference.
However, when sending input signals to the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F , there is a possibility that the input signals and the ground G reference may become unstable due to environmental changes such as noise in the reactor containment vessel 303 or the penetration 311.

However, the reliability of the input signals on the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F relative to the ground G is generally maintained.
Therefore, when the output signal from the output terminal D of the multiplexer 101 is transmitted to the outside of the reactor building 302 through the penetration 311 of the reactor building 302, the signal from the ground G is sent first.

Specifically, the multiplexer 101 selects the signal of ground G on the input signal line S _0F using the control signals on the control lines A _{01 to} A ₀₃ , and passes it through the through-hole 311 as an output signal from the output terminal D of the multiplexer 101. Then, immediately after that, one of the input signals on the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0E is selected using the control signals on the control lines A _{01 to} A ₀₃ , and passes it through the through-hole 311 as an output signal from the output terminal D of the multiplexer 101.
Then, it is assumed and estimated that the noise influence received when passing through the through-hole 311 is the influence of approximately the same time and under the same conditions, and the level of the output signal of the output terminal D of the multiplexer ₁₀₁ corresponding to one of the input signals of the input signal lines S ₀₀ to S ₀₉ , S _0A to S _0E transmitted immediately afterwards can be accurately grasped using the signal of the ground G of the input signal line S 0F as a reference.

2. Understanding the timing of switching
When the input signals of the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0E are transmitted over a long distance via the through-holes (penetrations) 311, a time delay occurs in the transmission of the signals.
Therefore, when switching the signal to be transmitted from the multiplexer 101, the ground G signal of the input signal line S _0F is first selected. Then, this ground G signal is passed through the through-hole 311 as the output signal of the output terminal D of the multiplexer 101.
In this way, when switching between input signals on different input signal lines S ₀₀ to S ₀₉ and S _0A to S _0E , a ground G signal is sent once to communicate that the input signal has changed, and the timing for switching between the input signals on different input signal lines S ₀₀ to S ₀₉ and S _0A to S _0E is clearly communicated to the signal processing unit 324 (FIG. 3) at the end of the through-hole 311.

For the reasons of (1. Noise countermeasures) and (2. Understanding switching timing) above, when transmitting any of the input signals of input signal lines S ₀₀ to S ₀₉ and S _0A to S _0E , or when switching the input signal, the signal of ground G of input signal line S _0F is passed through through-hole 311 as the output signal of output terminal D of multiplexer 101 immediately before that.
This method reduces the influence of noise when passing through the penetration 311, and enables the signal processing unit 324 outside the reactor building 302 to clearly grasp the timing at which the input signal is switched.

In the above method, the signal of the ground G of the input signal line S _0F passes through the penetration 311 as an output signal of the output terminal D of the multiplexer 101. Therefore, it is not necessary to pass the potential of the ground G in the reactor pressure vessel 304 through the penetration 311 independently as a signal line.
That is, by adopting the above method, the number of signal lines passing through the through portion 311 is reduced by one.
Furthermore, by passing the signal of the ground G of the input signal line S _0F through the multiplexer 101, the input signals of the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0E are subjected to the same conditions of radiation and influence at the through-hole 311.

<Circuit configuration of the control circuit using NAND circuits and inverter circuits>
In FIG. 7, as described above, the control section 221 is configured to include four NAND circuits 22NA1 to 22NA4, which are two-input NAND circuits, and six NOT circuits 22IN1 to 22IN6, which are inverter circuits.
That is, it is composed only of a NAND circuit and a NOT circuit. The control unit 221 has the role of selecting one of the bidirectional switches 23T1 to 23T4 of the switch unit 231, and therefore can generally be composed of a logic circuit. In general logic circuits, not only NAND circuits but also NOR circuits are often used.
However, the control section 221 in FIG. 7 is configured with a plurality of NAND circuits and a plurality of NOT circuits, and does not use a NOR circuit.
Next, the reason why the use of a NOR circuit is avoided in the control section 221 of FIG. 7 will be explained.

<Reasons for avoiding the use of NOR circuits>
FIG. 8 is a diagram showing an example of a configuration in which a NOR circuit is configured as a CMOS (Complementary MOS) circuit using p-type MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) and n-type MOSFETs.
CMOS NOR circuits are commonly used circuit configurations, but when used inside a nuclear reactor, it may be necessary to consider the effects of radiation and the unique phenomena caused by using SiC.
The behavior of the NOR circuit in such a case will be explained next.

In FIG. 8, the NOR circuit in the CMOS circuit has nMOS (n-type MOS) transistors M3 and M4 connected in parallel on the _Vss side (negative power supply side).
On the _Vdd side (positive power supply side), pMOS (p-type MOS) transistors M1 and M2 are connected in series.
An output terminal X is formed at the connection point between the drain of the pMOS transistor M2 and the drains of the nMOS transistors M3 and M4.
In such a transistor circuit configuration, the connection point (S12) between the PMOS transistors M1 and M2 is at a different potential from the substrate potential (V _dd ), so the source potential of the PMOS transistor M2 floats above the substrate potential (V _dd ) and is at a different potential.
Therefore, in FIG. 8, the threshold voltage of the pMOS transistor M2 enclosed by the dashed line is different from that when the source potential and the substrate potential are the same.

FIG. 9 is a diagram showing an equation indicating the threshold voltage of the pMOS transistor M2 when the source potential of the transistor M2 is different from the substrate potential.
9 is the threshold voltage _Vt . The first term ( _Vfb ) and the second term ( _2φB ) on the right side are terms related to the flat band and Fermi potential in a MOSFET, and roughly correspond to the threshold voltage when the source potential is equal to the substrate potential.
The third term on the right side is a term that indicates how the variation in the substrate bias affects the threshold voltage of transistor M2. The fourth term on the right side is a term that indicates how the variation in the substrate bias affects the threshold voltage of transistor M2 by affecting the charge on the gate when the source potential of transistor M2 differs from the substrate potential.
The fluctuation in the characteristics of the pMOS transistor M2 shown in FIG. 9 may affect the function of the NOR circuit, causing operational problems.

When configured as a NAND circuit with a CMOS configuration, the circuit configuration differs from the NOR circuit configuration shown in FIG. 8 and is configured with nMOS (n-type MOS) transistors M3 and M4 connected in series.
Therefore, it is conceivable that floating of the nMOS transistor M3 from the _Vss side may cause a similar problem, but in the case of nMOS, the fourth term in the equation corresponding to the threshold voltage in FIG. 9, the charge Q _ot , is about one order of magnitude smaller, so the impact is small.
In this way, the substrate bias effect occurs in the pMOS transistor M2 in the NOR circuit shown in Fig. 8. Furthermore, due to the negative shift of the threshold voltage _Vth caused by gamma rays, the NOR circuit may not operate correctly even transiently.

For the above reasons, when used within a nuclear reactor, in order to avoid the effects of radiation and problems specific to SiC, if the logic circuit of the control unit 221 (FIG. 7) is configured with a CMOS circuit, it is desirable to avoid the use of NOR circuits as much as possible and configure the logic circuit with NAND circuits and NOT circuits.
It is known that a logic circuit in an integrated circuit can generally be configured using a plurality of NAND circuits and NOT circuits without using a NOR circuit.

<Leakage current countermeasures for nMOS series circuit configuration>
Next, the phenomenon of leakage current between nMOS transistors in a two-stage series circuit configuration of nMOS transistors and countermeasures will be described with reference to FIGS.

FIG. 10 is a diagram showing an example of a circuit configuration on the nMOS side of a NAND circuit configured with a CMOS circuit, and a path in a state where a leakage current occurs.
The NAND circuit in the CMOS circuit is configured to include two nMOS (M3, M4) connected in series and two pMOS (M1, M2) connected in parallel.
Therefore, there is a two-stage series circuit configuration (M3, M4) configured on the nMOS side.
This section explains the phenomenon and countermeasures for an example of a leakage current path between nMOS in a two-stage series circuit configuration. Note that the NAND circuit shown in Figure 10 is just an example, and the phenomenon of leakage current between nMOS is not necessarily a phenomenon caused by the NAND circuit itself.

In FIG. 8, the problems of pMOS transistors in NOR circuits are pointed out, and it is described that it is desirable to use NAND circuits whenever possible, but it is not only the pMOS in NOR circuits that should be considered.
Taking the configuration of a NAND circuit as an example in FIGS. 10 and 11, the phenomenon, problems, and countermeasures of leakage current between nMOSs in a two-stage series circuit configuration formed on the nMOS side will be explained.
As mentioned above, SiC with a large band gap is used to ensure radiation resistance, but since SiC is made by mixing carbon (C) with silicon (Si) crystals, crystal defects are likely to occur. Therefore, measures to prevent leakage current, especially in nMOS, may be necessary.
10, it is assumed that the signals at input terminal A and input terminal B are both at negative potential. Thus, even though the gate potentials of nMOS transistors M3 and M4 are negative and both are off, leakage current L43 may occur between the drain of transistor M3 and the source of transistor M4.

FIG. 11 is a diagram showing an example of a pattern configuration on the nMOS side of the NAND circuit corresponding to FIG. 10 and a state in which leakage current occurs.
FIG. 11 shows a state in which the gate potentials of the nMOS transistors M3 and M4 are negative and leakage current L43 occurs even though both are off.
The reason why these leakage currents L43 may occur is that, as mentioned above, SiC is made by mixing carbon (C) with silicon (Si) crystals, which makes it easy for crystal defects to occur.

FIG. 12 is a diagram showing an example of a countermeasure for preventing leakage current on the nMOS side in the NAND circuit corresponding to FIG.
In FIG. 12, a diffusion layer P ⁺ separation layer, which is an example of a "high concentration separation layer" compared to the concentration of a P-type substrate (or well), is provided between nMOS transistors M3 and M4.
By providing this isolation layer for the P ⁺ diffusion layer, it is possible to prevent leakage current from the drain side of the nMOS transistor M3 and the source side of the nMOS transistor M4.
There are various possible paths for leakage current caused by crystal defects in SiC. For example, measures to prevent leakage current from the source side of transistor M3 and the drain side of transistor M3 may involve other methods not described above.

<Summary of the First Embodiment>
Sensor signals and power lines for driving them are input and output from the inside of the containment vessel 303 to the outside of the reactor building 302 via a penetration 311 between the containment vessel 303 and the reactor building 302. However, there is a limit to the number of signal lines that can pass through the penetration 311.
Therefore, by passing signals from a plurality of signal lines through a multiplexer that is resistant to radiation, the number of signal lines passing through the through portion 311 can be reduced.

SiC, a wide-gap semiconductor that is resistant to radiation, has a relatively large number of crystal defects because the Si (silicon) crystal contains C (carbon).
Therefore, increasing the integration scale of transistors in a multiplexer made of SiC can significantly reduce the yield of SiC-IC chips.
To avoid this yield drop, for example, relatively small unit multiplexers 201 with a basic configuration having four input signal lines, two control lines, and one output signal line are manufactured, and good products are selected. Five of the small unit multiplexers 201 with the basic configuration that have been selected and guaranteed to be good products are then combined as independent chip pieces to manufacture a large-scale multiplexer 101 with 16 input signal lines, four control lines, and one output signal line.
This manufacturing method allows the multiplexer 101 to be manufactured with a large number of input signal lines and control lines, and to have a large scale configuration, with a high yield.

Furthermore, because multiplexer 101 and multiplexer 201 are placed in locations affected by radiation, the logical configuration of the control unit of multiplexer 201 is configured with NAND circuits and NOT circuits (inverters), and does not use NOR circuits.

<Effects of the First Embodiment>
According to the radiation-hardened semiconductor device of the first embodiment of the present invention, a single multiplexer with many input signal lines is constructed by combining a plurality of small unit multiplexers, each of which is made up of independent chip pieces and has few input signal lines. This makes it possible to provide a radiation-hardened semiconductor device that avoids a decrease in yield due to an increase in the integration scale of transistors and reduces the effects of initial defects caused by crystal defects in SiC.
That is, it is possible to provide a radiation-resistant semiconductor device equipped with a multiplexer of a large scale configuration, which is radiation-resistant and has a high manufacturing yield and low cost.

Furthermore, it is possible to provide a radiation-resistant semiconductor device in which the influence of _Vth fluctuations and leakage currents caused by gamma rays is reduced.
Furthermore, at least one of the multiple input signal lines of the multiplexer is connected to ground, and a method is adopted in which a signal of the ground voltage is sent when switching between the multiple input signal lines. This has the effect of enabling the input signal to be accurately grasped even when the ground voltage fluctuates, and also makes it possible to provide a radiation-hardened semiconductor device and a method of controlling a radiation-hardened semiconductor device that have the effect of clearly transmitting the switching timing of the input signal.

Second Embodiment: Method for Controlling Radiation-Resistant Semiconductor Device
1, noise countermeasures for the output signal of the multiplexer 101, which is an analog signal, have been described. Although some of the above is redundant, key points of the control method for a radiation-hard semiconductor device will be described again from the perspective of noise countermeasures as a "control method for a radiation-hard semiconductor device."

1, the input signal line S _0F is connected to the ground G. The input signals of the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F have signal amplitudes as signals with the ground G as the reference.
Therefore, when the output signal from the output terminal D of the multiplexer 101 is transmitted to the outside of the reactor building 302 through the penetration 311 of the reactor building 302, the signal from the ground G is sent first.

Specifically, as described above, in the multiplexer 101 (radiation-hardened semiconductor device), the signal of ground G of the input signal line S _0F is selected by the control signals of the control lines A _{01 to} A ₀₃ , and is passed through the penetration 311 as an output signal of the output terminal D of the multiplexer 101. Then, immediately thereafter, one of the input signals of the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F is selected by the control signals of the control lines A _{01 to} A ₀₃ , and is passed through the penetration 311 as an output signal of the output terminal D of the multiplexer 101.
Then, it is assumed and estimated that the influence of noise received when passing through the through-hole 311 is an influence occurring at approximately the same time, and the level of the output signal of the output terminal D of the multiplexer ₁₀₁ corresponding to any of the input signals of the input signal lines S ₀₀ to S ₀₉ , S _0A to S _0F transmitted immediately afterwards can be accurately grasped using the signal of the ground G of the input signal line S 0F as a reference.

Furthermore, when the input signals of the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0E are transmitted over a long distance via the penetration 311, a time delay occurs in the transmission of the signals.
In order to prevent malfunctions due to time delays caused by such signal transmission, the ground G signal of the input signal line S _0F is first selected when switching the signal transmitted from the multiplexer 101. Then, this ground G signal is passed through the through-hole 311 as the output signal of the output terminal D of the multiplexer 101.
In this way, when switching between input signals on different input signal lines S ₀₀ to S ₀₉ and S _0A to S _0E , a ground G signal is sent once to communicate that the input signal has changed, and the timing for switching between the input signals on different input signal lines S ₀₀ to S ₀₉ and S _0A to S _0E is clearly communicated to the signal processing unit 324 (FIG. 3) at the end of the through-hole 311.

As described above, the radiation-hardened semiconductor device of the second embodiment uses the radiation-hardened semiconductor device of the first embodiment, and connects at least one of the plurality of input signal lines to ground. When switching input signals of the plurality of input signal lines, the multiplexer 101 first switches to the input signal line connected to ground G or a predetermined voltage, and then switches to the input signal of the desired input signal line.
There is a method for controlling such a radiation-resistant semiconductor device.

<Effects of the Second Embodiment>
When the output signal from output terminal D of multiplexer 101 is transmitted to the outside of reactor building 302 through penetration 311 in reactor building 302, a method is adopted in which the signal from ground G is sent first. This method provides a method for controlling a radiation-hard semiconductor device that is effective in preventing the influence of noise received when passing through penetration 311 and malfunctions due to time delays caused by signal transmission.

Third Embodiment: Sensor System for Nuclear Power Plant
Referring to FIG. 1 and FIG. 3, the sensor system of a nuclear power plant will be described again, although some of the points will be overlapped.
As shown in FIG. 3 , a signal transmission unit 320 composed of the multiplexer 101 (radiation-resistant semiconductor device) described in the first embodiment, i.e., the multiplexer 321 in FIG. 3 and an amplifier 322, is connected to a signal output unit 323 and a signal processing unit 324 via a penetration 311.
In this way, the sensor system of the nuclear power plant is installed across the reactor containment vessel 303 and the reactor building 302 in the reactor premises 301 .

Specifically, the sensor system for a nuclear power plant is configured as follows:
Installed within the containment vessel 303 are a sensor group including a plurality of sensors 312A, 312B that detect data within the containment vessel 303, a multiplexer 321 (101: radiation-resistant semiconductor device) that switches measurement signals output from the sensor group, and an amplifier 322 that amplifies the measurement signal selectively output by the multiplexer 321 (101).

In addition, the output signal of amplifier 322 is output to the outside of reactor building 302 via penetration 311 that spans between reactor containment vessel 303 and reactor building 302.

Installed outside the reactor building 302 are a signal output unit 323 that outputs the measurement signal output from the amplifier 322, and a signal processing unit 324 that monitors and processes the measurement signal output from the signal output unit 323.

In addition, the multiplexer 321 (101: radiation-resistant semiconductor device) and amplifier 322 are made of silicon carbide (SiC).

Furthermore, the sensor group including the plurality of sensors 312A and 312B and the multiplexer 321 (101: radiation-resistant semiconductor device) are exposed to a high radiation environment.
The signal processing unit 324 is provided outside the reactor building 302, which is in a low radiation environment.
Furthermore, the signal line that transmits the measurement signal selectively output by the multiplexer 321 (101: radiation-resistant semiconductor device) passes through the penetration 311 of the reactor building 302 as described above.
As described above, the sensor system for a nuclear power plant is configured using the multiplexer 101 (radiation-resistant semiconductor device) described in the first embodiment, and monitors signals from a group of sensors inside the reactor containment vessel 303, which is in a high radiation environment, from outside the reactor building 302, which is in a low radiation environment.

<Effects of the Third Embodiment>
The sensor system for a nuclear power plant of the third embodiment uses the multiplexer 101 (radiation-resistant semiconductor device) described in the first embodiment to pass signals from a group of sensors inside a reactor containment vessel 303 that is in a high radiation environment through a penetration 311 in the reactor building 302, and monitors them on the outside of the reactor building 302. This reduces the number of signal lines in the penetration 311, and has the effect of preventing malfunctions due to the influence of noise and time delays caused by signal transmission.
Furthermore, since the radiation-resistant semiconductor device is used, which is radiation-resistant and equipped with a low-cost multiplexer with a high manufacturing yield, it is possible to provide a low-cost sensor system for nuclear power plants that is resistant to malfunctions due to the effects of noise and time delays caused by signal transmission.

Other embodiments and supplements
The present invention is not limited to the above-described embodiments, and various modifications are also possible. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with part of the configuration of another embodiment, and it is also possible to add, delete, or replace part or all of the configuration of another embodiment with the configuration of one embodiment.
Other embodiments, modifications, and supplements will be further described below.

<<About semiconductor elements>>
In the first embodiment, a case has been described in which SiC is used in pMOS and nMOS as a semiconductor having a wider band gap than Si and being resistant to radiation.
However, semiconductors with a wider band gap than Si (silicon) and that are resistant to radiation are not limited to SiC (silicon carbide). For example, semiconductors with a wider band gap include compound semiconductors such as GaAs (gallium arsenide), GaN (gallium nitride), AlP (aluminum phosphide), and InP (indium phosphide).

Incidentally, SiC is a combination of group IV and group IV elements, and like Si, is a group IV element. Therefore, when creating pMOS and nMOS, trivalent (group V) B (boron) and pentavalent (group III) P (phosphorus) are implanted as impurities to form the p-type and n-type semiconductors, respectively.
For example, GaAs is a combination of group III and group V. When it contains more Ga (gallium) than As (arsenic), it becomes a p-type semiconductor, and when it contains more As than Ga, it becomes an n-type semiconductor.
As described above, by forming p-type and n-type semiconductors and using semiconductors (including compound semiconductors) that have a wider band gap than Si and are resistant to radiation, pMOS and nMOS that are resistant to radiation can be constructed.

<<About MOSFETs>>
In the first embodiment, the pMOS and nMOS are simply referred to as MOSFETs. The above-described effects can be achieved with MOSFETs having a planar (horizontal) structure, MOSFETs having a trench (vertical) structure, and even superjunction MOSFETs.

Other reasons for using NAND circuits
Using the example of the fluctuation in substrate potential on the pMOS side of the NOR circuit in FIG. 8, it has been explained that it is desirable to avoid using NOR circuits in logic circuits and to configure them using NAND circuits and NOT circuits.
However, there are other advantages to avoiding NOR circuits and using NAND circuits.
In a NOR circuit, nMOSs are configured in parallel, while pMOSs are configured in series. When nMOSs are configured in parallel, the driving capacity of the nMOSs is the same as when there is one nMOS or when there are two nMOSs. On the other hand, the pMOSs are configured in series, so the driving capacity is less than half.

Furthermore, nMOS operates using electrons, which have high mobility, while pMOS operates using holes, which have low mobility. The mobility of electrons is generally more than three times higher than that of holes.
Due to the above background, in a NOR circuit, the operation of the nMOS side configured in parallel is generally six times faster than the operation of the pMOS side configured in series, which means that there is an extreme imbalance between the operating speed of the nMOS side and the operating speed of the pMOS side.
On the other hand, in a NAND circuit, the difference in operating speed due to the number of stages and the difference in operating speed due to the difference in mobility between electrons and holes act to cancel each other out, so the operating speed of the pMOS side configured in parallel and the operating speed of the nMOS configured in series become closer.
That is, even from the viewpoint other than the above-mentioned fluctuation in substrate potential, it is preferable to use NAND circuits as much as possible in the configuration of logic circuits rather than NOR circuits.

<<Number of inputs to a NAND circuit>>
7, a method using a NAND circuit with two input signals has been described, but the NAND circuit used in the control unit 221 is a two-input NAND circuit.
Although we have explained that NAND circuits are preferable, multi-stage NAND circuits with three or more inputs have a series circuit configuration of three or more stages of nMOS, which may further increase the difference between the source potential and substrate potential of the nMOS. Therefore, although the above-mentioned nMOS has little effect on the threshold voltage, it is not preferable.

That is, a suitable NAND circuit is a two-input NAND circuit, and it is generally preferable to avoid NAND circuits with three or more inputs.
All of the four NAND circuits 22NA1 to 22NA4 used in the control unit 221 shown in Fig. 7 are two-input NAND circuits, and no NAND circuits with three or more inputs are used.
From the viewpoint of operational stability, it is desirable to reconfigure a NAND circuit with three or more inputs by combining a two-input NAND circuit and a NOT circuit.

Highly concentrated separation layer
FIG. 12 shows an example in which a P ⁺ isolation layer is provided in a layout in which nMOS are configured in series, but there is also a method in which an N ⁺ isolation layer is provided in a location in which pMOS are configured in series to prevent leakage current on the pMOS side.

<Applications of radiation-resistant semiconductor devices>
Although the above description has been given of a radiation-resistant semiconductor device used in a reactor containment vessel in a nuclear power plant, the present invention is not limited to the environment of a reactor containment vessel or to radiation-resistant semiconductor devices.
The present invention can also be applied to radiation utilization facilities other than nuclear plants.

<Ground G signal transmission>
In the operation of the multiplexer 101 shown in FIG. 1, when transmitting any of the input signals of the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F , the signal of the ground G of the input signal line S _0F is passed through the penetration 311 as an output signal of the output terminal D of the multiplexer 101 immediately before the transmission, as described above, but the present invention is not limited to this configuration or method.

For example, although the input signal line S _0F is connected to the signal of the ground G, it is not limited to the input signal line S _0F that is connected to the ground G. It may be any of the other input signal lines S ₀₀ to S ₀₉ and S _0A to S _0E .
Furthermore, the number of input signal lines connected to the ground G is not limited to one. A plurality of input signal lines may be connected to the ground G.
In the above description, a signal of ground G is transmitted and used as a reference signal for comparison in order to accurately determine the input signal of the input signal line, but this is not necessarily limited to ground G. If there is a predetermined appropriate reference potential signal, that predetermined signal may be used.

Furthermore, when transmitting any of the input signals on the input signal lines S ₀₀ to S ₀₉ , S _0A to S _0F , or when switching the input signal line, the signal is connected to the ground G immediately before that, but the present invention is not limited to this method.
For example, when transmitting the same predetermined input signal continuously for a long period of time on the input signal lines S ₀₀ to S ₀₉ and S _0A to S _0F , the ground G of the input signal line S _0F may be transmitted along the way. This method is effective when the potential of the ground G fluctuates for some reason.

Even larger scale multiplexers
In the first embodiment, five small unit multiplexers 201, each with four input signal lines and two control lines, are combined to form a large-scale multiplexer 101 with 16 input signal lines and four control lines. However, the present invention is not limited to this configuration. Next, examples 1 and 2 will be described as methods for constructing a large-scale multiplexer.

<Example 1>
For example, it is possible to combine 16 multiplexers 101 each having 16 input signal lines and 4 control lines to form an even larger multiplexer having 256 input signal lines and 8 control lines.

<Example 2>
Also, if the multiplexer in <Example 1> is too large and a more medium-sized multiplexer is desired, the following configuration is also available as <Example 2>.
For example, it is possible to configure a medium-sized multiplexer with 64 input signal lines and 6 control lines by combining four multiplexers 101 each with 16 input signal lines and 4 control lines and one multiplexer (unit multiplexer) 201 with 4 input signal lines and 2 control lines.

101 Multiplexer (large-scale multiplexer), radiation-resistant semiconductor device 201, 201A to 201D, 201S Multiplexer (unit multiplexer)
201N Multiplexer (multiplexer with n control lines)
211A to 211D: output signal lines; 221: control unit; 22IN1 to 22IN6: NOT circuits, inverters
22NA1 to 22NA4 NAND circuit 231 Switch section 23T1 to 23T4 Bidirectional switch (transmission gate)
301 Reactor premises 302 Reactor building 303 Reactor containment vessel 304 Reactor pressure vessel 305 Pressure suppression chamber 311 Penetration
312 Measuring instrument installation area 312A, 312B Sensor 320 Signal transmission unit 321 Multiplexer 322 Amplifier
323 Signal output unit 324 Signal processing unit A ₀₀ , A ₀₁ , A ₀₂ , A ₀₃ Control line D Output terminal G Ground M1, M2 pMOS (p-type MOS)
M3, M4 nMOS (n-type MOS)
S ₀₀ to S ₀₉ , S _0A to S _0F , S ₁₀ to S ₁₃ input signal lines

Claims (11)

a multiplexer having a large-scale configuration in which a plurality of unit multiplexers made of silicon carbide are connected in a predetermined manner;
The multiplexer in a large scale configuration includes:
a plurality of input signal lines connected to some of the plurality of unit multiplexers;
an output signal line output from one of the plurality of unit multiplexers;
Equipped with
a unit multiplexer to which the output signal line is connected and a unit multiplexer to which the input signal line is connected are controlled by different control signals;
each of the plurality of unit multiplexers is formed from an independent chip piece , and is guaranteed to be a non-defective product through screening for crystal defects in the silicon carbide in a prior inspection;
A radiation-resistant semiconductor device characterized by: In claim 1,
The unit multiplexer is configured to include a MOSFET.
A radiation-resistant semiconductor device characterized by: In claim 1,
The unit multiplexer is configured to have four input signal lines, two control signal lines, and one output signal line.
A radiation-resistant semiconductor device characterized by: In claim 1,
The multiplexer of large scale configuration has 16 input signal lines, 4 control signal lines and 1 output signal line,
A radiation-hardened semiconductor device comprising a combination of five of the unit multiplexers, each of which is an independent chip piece having a small chip area and configured to have four input signal lines, two control signal lines, and one output signal line. In claim 1,
The unit multiplexer comprises:
A plurality of input terminals, a plurality of control terminals, and one output terminal;
a plurality of bidirectional switches respectively connected between the plurality of input terminals and the output terminal;
a control unit that controls the bidirectional switches by a plurality of control signals input from the plurality of control terminals;
Equipped with
The radiation-hard semiconductor device is characterized in that the control circuit of the control unit is composed of a plurality of NAND circuits and a plurality of NOT circuits. In claim 5,
The NAND circuit is a two-input NAND circuit.
A radiation-resistant semiconductor device characterized by: In claim 1,
the unit multiplexer is composed of a plurality of transistors,
An isolation layer is disposed in the plurality of transistors to prevent leakage current between the transistors.
A radiation-resistant semiconductor device characterized by: In claim 7,
The radiation-resistant semiconductor device is characterized in that the isolation layer is formed by diffusing impurities at a concentration higher than that of the substrate or well. A method for controlling a radiation-hard semiconductor device using the radiation-hard semiconductor device according to claim 1, comprising:
At least one of the plurality of input signal lines is connected to ground,
When switching the input signals of the plurality of input signal lines as a multiplexer, the input signal line is first switched to the input signal line connected to ground or a predetermined voltage, and then switched to the input signal of the desired input signal line intended for transmission.
2. A method for controlling a radiation-resistant semiconductor device comprising: A sensor system for a nuclear power plant using the radiation-resistant semiconductor device according to claim 1,
the sensor system is installed across a reactor containment vessel and a reactor building of a nuclear power plant,
a group of sensors for detecting data inside the containment vessel;
the multiplexer having a large-scale configuration for switching measurement signals output from the group of sensors;
an amplifier for amplifying the measurement signals selectively output by the multiplexer in a large scale configuration ;
a signal processing unit installed in the reactor building that monitors the measurement signal output from the amplifier;
The present invention is configured to include:
the multiplexer and the amplifier in a large scale configuration are constructed of silicon carbide;
A sensor system for a nuclear power plant. In claim 10,
the group of sensors and the large-scale configuration of the multiplexer are exposed to a high radiation environment;
a signal line for transmitting the measurement signal selectively output by the large-scale multiplexer passes through a penetration part of the reactor building;
A sensor system for a nuclear power plant.