JP7810080B2 - Noise Attenuation Circuit - Google Patents

Description

This disclosure relates to a noise attenuation circuit.

Canceller circuits that attenuate common-mode noise generated in inverters and other devices are known. For example, Patent Document 1 describes a common-mode noise cancellation circuit device that includes a primary coil disposed between a high-voltage DC power supply and a three-phase inverter circuit, a secondary coil electromagnetically coupled to the primary coil, and a noise cancellation circuit. In this device, when a common-mode current flows through the primary coil, a common-mode voltage is generated in the secondary coil, and a common-mode cancellation current that is opposite in phase to the common-mode current is generated by the noise cancellation circuit based on the common-mode voltage.

Japanese Patent Application Laid-Open No. 2006-333647

In order to improve the common-mode noise attenuation effect, it is necessary to increase the gain of the canceller circuit. However, if the voltage value obtained by multiplying the common-mode voltage by the gain becomes greater than the voltage value of the canceller circuit's power supply voltage, the canceller circuit may not operate properly. As a result, the gain of the canceller circuit cannot be made sufficiently large, and there is a risk that common-mode noise may not be sufficiently attenuated.

This disclosure describes a noise attenuation circuit that can improve the attenuation effect of common-mode noise.

A noise attenuation circuit according to one aspect of the present disclosure is provided between a power storage device and an inverter that converts DC power supplied from the power storage device into AC power, and generates an attenuation current for attenuating noise current generated in the inverter. The noise attenuation circuit includes an auxiliary coil wound around the core of a common mode choke coil provided between the power storage device and the inverter, a conversion circuit that generates an attenuation current based on a detection voltage detected by the auxiliary coil, and a generation circuit that generates a negative-phase voltage that attenuates the carrier component of the detection voltage. The conversion circuit includes an adder circuit that generates a sum voltage by adding the detection voltage and the negative-phase voltage, and an amplifier circuit provided downstream of the adder circuit that amplifies the sum voltage.

In this noise attenuation circuit, the conversion circuit adds the detection voltage detected by the auxiliary coil and the negative-phase voltage to generate a summed voltage, which is then amplified. Since the carrier component of the detection voltage is not subject to noise regulations, the carrier component of the detection voltage is attenuated by using a voltage that attenuates the carrier component of the detection voltage as the negative-phase voltage. This results in a summed voltage with an amplitude smaller than that of the detection voltage, allowing the gain of the amplifier circuit to be increased. As a result, it is possible to improve the common-mode noise attenuation effect.

In some embodiments, the generation circuit may include a control circuit that sets the frequency and phase of the negative-phase voltage based on the inverter drive signal. The frequency and phase of the carrier component of the detection voltage may be determined according to the inverter drive signal. In the above configuration, by taking the inverter drive signal into consideration, the frequency and phase of the negative-phase voltage can be matched to the frequency and phase of the carrier component of the detection voltage. Therefore, the carrier component of the detection voltage can be attenuated more reliably, and the amplitude of the added voltage can be reduced more reliably. As a result, it is possible to further improve the common-mode noise attenuation effect.

In some embodiments, the generation circuit may further include an oscillator that outputs a sine wave signal having a frequency and phase set by the control circuit as an antiphase voltage. This configuration allows the carrier component of the detection voltage to be attenuated without attenuating frequency components other than the carrier component. Therefore, it is possible to increase the gain of the amplifier circuit without compromising the attenuation effect of frequency components subject to noise regulations.

In some embodiments, the control circuit may set the amplitude of the negative-phase voltage based on the voltage value of the storage voltage, which is the voltage of the power storage device, and the modulation rate of the inverter, and the oscillator may output a sine wave signal as the negative-phase voltage, further having the amplitude set by the control circuit. The amplitude of the carrier component of the detection voltage may be determined according to the voltage value of the storage voltage and the modulation rate of the inverter. In the above configuration, by taking into account the voltage value of the storage voltage and the modulation rate of the inverter, the amplitude of the negative-phase voltage can be made closer to the amplitude of the carrier component of the detection voltage. Therefore, the amplitude of the added voltage can be further reduced, and the gain of the amplifier circuit can be further increased. As a result, it is possible to further improve the attenuation effect of common-mode noise.

In some embodiments, the control circuit may output a first pulse and a second pulse having the same frequency as the carrier component of the detection voltage. The generation circuit may further include a synthesis circuit that synthesizes the first pulse and the second pulse to generate a synthesized signal, and a filter circuit that extracts a frequency component that is the same as the carrier component of the detection voltage from the synthesized signal. The generation circuit may output an anti-phase voltage based on the extracted frequency component. This configuration allows the anti-phase voltage to be generated without using an oscillator, thereby reducing the circuit size of the noise attenuation circuit.

In some embodiments, the control circuit may set the phase difference between the first pulse and the second pulse based on the voltage value of the storage voltage, which is the voltage of the storage device, and the modulation rate of the inverter. The amplitude of the composite signal can be changed by adjusting the phase difference between the first pulse and the second pulse. As described above, the amplitude of the carrier component of the detection voltage can be determined based on the voltage value of the storage voltage and the modulation rate of the inverter. Therefore, by setting the phase difference between the first pulse and the second pulse based on the voltage value of the storage voltage and the modulation rate of the inverter, the amplitude of the negative-phase voltage can be made closer to the amplitude of the carrier component of the detection voltage. This allows the amplitude of the added voltage to be further reduced, further increasing the gain of the amplifier circuit. As a result, the common-mode noise attenuation effect can be further improved.

This disclosure makes it possible to improve the attenuation effect of common-mode noise.

FIG. 1 is a schematic diagram of a power supply device including a noise attenuation circuit according to a first embodiment. 2A is a diagram showing an example of a waveform of a detected voltage, FIG. 2B is a diagram showing an example of a waveform of a negative-phase voltage, and FIG. 2C is a diagram showing an example of a waveform of an added voltage. FIG. 3 is a schematic diagram of a power supply device including a noise attenuation circuit according to the second embodiment. FIG. 4 is a diagram for explaining a composite signal. 5A to 5E are diagrams showing examples of the waveforms of the signals when the phase difference between the two pulses is 135°. FIGS. 6A to 6E are diagrams showing examples of waveforms of the signals when the phase difference between the two pulses is 0°.

The noise attenuation circuit according to the embodiment will be described in detail below with reference to the accompanying drawings. In the description of the drawings, the same or equivalent elements will be designated by the same reference numerals, and duplicate descriptions will be omitted.

(First embodiment)
The configuration of a power supply device including a noise attenuation circuit according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic diagram of a power supply device including a noise attenuation circuit according to the first embodiment. The power supply device 1 shown in Fig. 1 is a device that supplies AC power to a motor M. The power supply device 1 includes a power storage device 2, a main circuit 3, an inverter 4, and a noise attenuation circuit 5. In the power supply device 1, a noise current In generated in the inverter 4 is attenuated by the noise attenuation circuit 5.

The power storage device 2 supplies DC power to the inverter 4. The power storage device 2 can be used as a battery for various vehicles, such as forklifts, hybrid vehicles, and electric vehicles. The power storage device 2 is composed of, for example, a lithium-ion battery, a lead-acid battery, or a nickel-metal hydride battery. The storage voltage, which is the voltage of the power storage device 2, can vary depending on the type of power storage device 2 and the amount of power stored in the power storage device 2. The storage voltage is the open-circuit voltage of the power storage device 2. In other words, the storage voltage is the voltage between the positive and negative terminals of the power storage device 2.

The main circuit 3 includes a coil 31, a coil 32, a connecting wire 33, a connecting wire 34, a capacitor 35, and a capacitor 36. The coils 31 and 32 are wound around a core 30 made of a magnetic material, forming a common mode choke coil.

In a common mode choke coil, when a common mode current (hereinafter referred to as "common mode current") flows through coils 31 and 32, magnetic flux is generated by electromagnetic induction in coils 31 and 32. In this case, the generated magnetic fluxes are oriented in the same direction, and the magnetic fluxes reinforce each other, causing the common mode choke coil to function as an inductor. When a differential mode current flows through coils 31 and 32, the generated magnetic fluxes are oriented in opposite directions, causing the magnetic fluxes to cancel each other out. As a result, the common mode choke coil does not function as an inductor for differential mode currents.

Coil 31 and coil 32 are provided between the storage device 2 and the inverter 4. One end of coil 31 is connected to the positive terminal of the storage device 2. The other end of coil 31 is connected to connection wire 33. One end of coil 32 is connected to the negative terminal of the storage device 2. The other end of coil 32 is connected to connection wire 34.

The connection line 33 connects the coil 31 and the inverter 4. Specifically, one end of the connection line 33 is connected to the other end of the coil 31. The other end of the connection line 33 is connected to the inverter 4.

The connection line 34 connects the coil 32 and the inverter 4. Specifically, one end of the connection line 34 is connected to the other end of the coil 32. The other end of the connection line 34 is connected to the inverter 4.

Capacitor 35 and capacitor 36 are Y capacitors and are arranged between connection line 33 and connection line 34 and ground potential (earth). Specifically, one end of capacitor 35 is connected to the other end of connection line 33. The other end of capacitor 35 is connected to ground potential (earth). One end of capacitor 36 is connected to ground potential (earth). The other end of capacitor 36 is connected to the other end of connection line 34.

The inverter 4 converts DC power, which is input power supplied from the power storage device 2, into AC power and outputs it to the motor M. In this embodiment, the inverter 4 is a three-phase inverter and has multiple switching elements (not shown). A switching element is an element that can be electrically switched between open and closed. Examples of switching elements that can be used include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), and bipolar transistors. The inverter 4 also includes a drive circuit (not shown).

The noise attenuation circuit 5 generates an attenuation current Ic to attenuate the noise current In (common mode current) generated in the inverter 4. The noise current In is generated by the switching operation of the inverter 4. The noise current In is composed of a carrier component and a harmonic component. The frequency of the carrier component of the noise current In matches the frequency of the carrier component of the signal for driving the inverter 4 (hereinafter referred to as the "drive signal for the inverter 4"). The noise attenuation circuit 5 is provided between the storage device 2 and the inverter 4. The noise attenuation circuit 5 includes an auxiliary coil 50, a generation circuit 51, and a conversion circuit 52. The noise attenuation circuit 5 detects the detection voltage Vn in the auxiliary coil 50 and generates an attenuation current Ic that is opposite in phase to the noise current In based on the detection voltage Vn, thereby attenuating the noise current In generated in the inverter 4.

The auxiliary coil 50 is wound around the core 30 of the coils 31 and 32 and detects the detection voltage Vn. One end of the auxiliary coil 50 is connected to the ground potential (earth). The other end of the auxiliary coil 50 is connected to the conversion circuit 52. The auxiliary coil 50 outputs the detected detection voltage Vn to the conversion circuit 52. When a current flows through the auxiliary coil 50, the detection voltage Vn is generated in the auxiliary coil 50. The detection voltage Vn is obtained by converting the current flowing through the auxiliary coil 50 into a voltage and is composed of a carrier wave component and a harmonic component. Before the attenuation current Ic is generated, only the noise current In flows through the auxiliary coil 50. After the attenuation current Ic is generated, a combined current of the noise current In and the attenuation current Ic flows. However, in this embodiment, the initial stage before the attenuation current Ic is generated will be described.

The generation circuit 51 generates a negative-phase voltage Vi that attenuates the carrier component of the detection voltage Vn. The generation circuit 51 outputs the negative-phase voltage Vi to the conversion circuit 52. The generation circuit 51 includes a control circuit 53 and an oscillator 54.

The control circuit 53 is a circuit that sets the parameter values of the negative-phase voltage Vi. In this embodiment, the control circuit 53 sets the frequency, phase, and amplitude of the negative-phase voltage Vi. The control circuit 53 sets the frequency and phase of the negative-phase voltage Vi based on the drive signal of the inverter 4. Specifically, the control circuit 53 sets the frequency of the carrier component of the drive signal of the inverter 4 as the frequency of the negative-phase voltage Vi. The frequency of the carrier component of the drive signal of the inverter 4 is, for example, 20 kHz.

The control circuit 53 sets the phase of the negative-phase voltage Vi to be the opposite phase to the phase of the carrier component of the drive signal for the inverter 4. Because the phase of the carrier component of the detection voltage Vn is the same as the phase of the carrier component of the drive signal for controlling the inverter 4, the phase of the negative-phase voltage Vi is also the opposite phase to the phase of the carrier component of the detection voltage Vn.

The control circuit 53 sets the amplitude of the negative-phase voltage Vi based on the voltage value of the storage voltage of the storage device 2 and the modulation factor of the inverter 4. In this embodiment, the control circuit 53 has a table that defines the relationship between the voltage value of the storage voltage, the modulation factor of the inverter 4, and the amplitude of the negative-phase voltage Vi. In other words, the table sets the amplitude of the negative-phase voltage Vi for various combinations of the voltage value of the storage voltage and the modulation factor of the inverter 4.

The method for setting the table will now be described in detail. The amplitude of the detection voltage Vn can vary depending on the voltage value of the storage voltage and the modulation rate of the inverter 4. To bring the carrier component of the detection voltage Vn closer to zero, a negative-phase voltage Vi having the same amplitude as the amplitude of the carrier component of the detection voltage Vn must be subtracted from the detection voltage Vn. For this reason, the power supply device 1 is operated for each combination (voltage value of the storage voltage and modulation rate of the inverter 4) and the detection voltage Vn generated in the auxiliary coil 50 is measured. The amplitude of the negative-phase voltage Vi corresponding to that combination is determined to be the same as the amplitude of the carrier component of the measured detection voltage Vn. This is how the table is set.

The control circuit 53 obtains the voltage value of the storage voltage and the modulation rate of the inverter 4, and obtains from the table the amplitude of the negative-phase voltage Vi corresponding to the combination of the obtained voltage value of the storage voltage and the modulation rate of the inverter 4.

The control circuit 53 outputs command values for the frequency, phase, and amplitude of the negative-phase voltage Vi to the oscillator 54.

In this embodiment, the control circuit 53 also functions as a control unit for the inverter 4. Therefore, since the control circuit 53 supplies a drive signal to the inverter 4, it is aware of the frequency, switching timing, and modulation rate of the carrier component of the drive signal of the inverter 4. The control circuit 53 obtains the voltage value of the storage voltage from, for example, a voltage sensor provided between the positive and negative terminals of the storage device 2.

The oscillator 54 outputs a sine wave signal having parameter values set by the control circuit 53 as the negative-phase voltage Vi. In this embodiment, the oscillator 54 generates a sine wave signal having a frequency, phase, and amplitude set by the control circuit 53. The oscillator 54 outputs the generated sine wave signal to the conversion circuit 52 as the negative-phase voltage Vi.

The conversion circuit 52 generates an attenuation current Ic based on the detected voltage Vn. The conversion circuit 52 generates a current that is opposite in phase to the noise current In and outputs it as the attenuation current Ic, thereby attenuating the noise current In generated in the inverter 4. The conversion circuit 52 includes an adder circuit 55, an amplifier circuit 56, and an output capacitor 57.

The adder circuit 55 generates a sum voltage Va by adding the detection voltage Vn and the negative-phase voltage Vi. The adder circuit 55 outputs the sum voltage Va to the amplifier circuit 56. The adder circuit 55 has a known circuit configuration.

The amplifier circuit 56 amplifies the sum voltage Va. The amplifier circuit 56 is provided after the sum circuit 55. A known circuit configuration is used for the amplifier circuit 56.

The output capacitor 57 converts the sum voltage Va amplified by the amplifier circuit 56 into an attenuation current Ic. The output capacitor 57 is provided between the amplifier circuit 56 and the output terminal (connection line 34) of the conversion circuit 52. Specifically, one end of the output capacitor 57 is connected to the output terminal of the amplifier circuit 56, and the other end of the output capacitor 57 is connected to the connection line 34.

Next, the operation of the power supply device 1 will be described with further reference to (a) to (c) of Figure 2. (a) of Figure 2 is a diagram showing an example of a detected voltage waveform. (b) of Figure 2 is a diagram showing an example of a negative-phase voltage waveform. (c) of Figure 2 is a diagram showing an example of an added voltage waveform. The vertical axis of (a) of Figure 2 represents the detected voltage Vn (unit: V). The vertical axis of (b) of Figure 2 represents the negative-phase voltage Vi (unit: V). The vertical axis of (c) of Figure 2 represents the added voltage Va (unit: V). The horizontal axis of each of (a) to (c) of Figure 2 represents time (unit: μs).

In the power supply device 1, when DC power is supplied from the power storage device 2 to the inverter 4, a noise current In is generated due to the switching operation of the inverter 4. At this time, the noise current In flows through coils 31 and 32, and a detection voltage Vn is generated in the auxiliary coil 50 due to the noise current In flowing through coils 31 and 32. In the example shown in Figure 2(a), the detection voltage Vn contains a 20 kHz carrier wave component as its main component and also contains harmonic components.

The generation circuit 51 then generates a negative-phase voltage Vi that attenuates the carrier component of the detection voltage Vn. Specifically, as shown in Figure 2(b), the negative-phase voltage Vi is a sine wave signal having the same frequency as the carrier component of the detection voltage Vn, a phase opposite to that of the carrier component of the detection voltage Vn, and an amplitude identical to that of the carrier component of the detection voltage Vn. The summation circuit 55 of the conversion circuit 52 then adds the detection voltage Vn and the negative-phase voltage Vi to generate a summed voltage Va. As shown in Figure 2(c), the summed voltage Va has a waveform obtained by subtracting the carrier component of the detection voltage Vn from the detection voltage Vn, and the amplitude of the summed voltage Va is smaller than that of the detection voltage Vn.

The sum voltage Va is then amplified by the amplifier circuit 56, and the amplified sum voltage Va is converted by the output capacitor 57 into an attenuation current Ic that is in opposite phase to the noise current In. The attenuation current Ic is then supplied to the inverter 4 (connection line 34), thereby attenuating the harmonic components of the noise current In.

In the noise attenuation circuit 5 described above, the conversion circuit 52 adds the detection voltage Vn detected by the auxiliary coil 50 and the negative-phase voltage Vi to generate a summed voltage Va, which is then amplified. Here, standards such as CISPR restrict noise to frequency components above 150 kHz, so the carrier component of the detection voltage Vn (e.g., 20 kHz) is not. Therefore, by using a voltage that attenuates the carrier component of the detection voltage Vn as the negative-phase voltage Vi, the carrier component of the detection voltage Vn is attenuated. This results in a summed voltage Va with an amplitude smaller than that of the detection voltage Vn, allowing the gain of the amplifier circuit 56 to be increased. As a result, the common-mode noise attenuation effect can be improved.

In the example shown in Figure 2(a), the detection voltage Vn fluctuates within a range of approximately ±2.5V, and the amplitude of the detection voltage Vn is approximately 5V. Assuming that the voltage range of the amplifier circuit 56 is ±15V, if the detection voltage Vn is supplied directly to the amplifier circuit 56, the maximum gain of the amplifier circuit 56 is 6. On the other hand, as shown in Figure 2(c), the sum voltage Va fluctuates within a range of approximately ±1.8V, and the amplitude of the sum voltage Va is approximately 3.6V. If the sum voltage Va is supplied to the amplifier circuit 56, the maximum gain of the amplifier circuit 56 is approximately 8.3. Therefore, the gain of the amplifier circuit 56 can be increased by approximately 1.4 times.

The frequency and phase of the carrier component of the detection voltage Vn can be determined according to the drive signal of the inverter 4. In the power supply device 1, the control circuit 53 sets the frequency and phase of the negative-phase voltage Vi based on the drive signal of the inverter 4. With this configuration, the drive signal of the inverter 4 is taken into consideration, so the frequency and phase of the negative-phase voltage Vi can be matched to the frequency and phase of the carrier component of the detection voltage Vn, respectively. Therefore, the carrier component of the detection voltage Vn can be more reliably attenuated, which more reliably reduces the amplitude of the added voltage Va and further increases the gain of the amplifier circuit 56. As a result, it is possible to further improve the attenuation effect of common-mode noise.

The amplitude of the carrier component of the detection voltage Vn can be determined according to the voltage value of the storage voltage of the storage device 2 and the modulation rate of the inverter 4. In the power supply device 1, the control circuit 53 sets the amplitude of the negative-phase voltage Vi based on the voltage value of the storage voltage of the storage device 2 and the modulation rate of the inverter 4. Therefore, by taking into account the voltage value of the storage voltage and the modulation rate of the inverter 4, the amplitude of the negative-phase voltage Vi can be made closer to the amplitude of the carrier component of the detection voltage Vn. This allows the amplitude of the added voltage Va to be further reduced, and the gain of the amplifier circuit 56 to be further increased. As a result, it is possible to further improve the attenuation effect of common-mode noise.

The oscillator 54 outputs a sine wave signal having a frequency, phase, and amplitude set by the control circuit 53 as the negative-phase voltage Vi. This configuration allows the carrier component of the detection voltage Vn to be attenuated without attenuating frequency components other than the carrier component. Therefore, it is possible to increase the gain of the amplifier circuit 56 without compromising the attenuation effect of frequency components subject to noise regulations.

Second Embodiment
Next, the configuration of a power supply device including a noise attenuation circuit according to a second embodiment will be described with reference to FIGS. 3 and 4. FIG. 3 is a schematic diagram of a power supply device including a noise attenuation circuit according to the second embodiment. FIG. 4 is a diagram for explaining a composite signal. The power supply device 1A shown in FIG. 3 differs from the power supply device 1 mainly in that it includes a noise attenuation circuit 5A instead of the noise attenuation circuit 5. The noise attenuation circuit 5A differs from the noise attenuation circuit 5 mainly in that it includes a generation circuit 51A instead of the generation circuit 51. The generation circuit 51A differs from the generation circuit 51 mainly in that it includes a control circuit 61, a synthesis circuit 62, a filter circuit 63, and an amplifier circuit 64 instead of the control circuit 53 and oscillator 54.

The control circuit 61 outputs a pulse P1 (first pulse) and a pulse P2 (second pulse) to generate a negative-phase voltage Vi. Each of the pulses P1 and P2 has a frequency component (hereinafter referred to as a "specific frequency component") that is the same as the frequency of the carrier component of the drive signal of the inverter 4. The pulses P1 and P2 are square waves with the same amplitude. In this embodiment, the phase of the pulse P1 is the same as or leads the phase of the pulse P2.

The control circuit 61 sets the phase of pulses P1 and P2 so that the phase of the negative-phase voltage Vi is the opposite phase to the phase of the carrier component of the drive signal for inverter 4. Because the phase of the carrier component of detection voltage Vn is the same as the phase of the carrier component of the drive signal for controlling inverter 4, the phase of the negative-phase voltage Vi is also the opposite phase to the phase of the carrier component of detection voltage Vn.

The control circuit 61 sets the phase difference θ between pulse P1 and pulse P2 based on the voltage value of the storage voltage of the storage device 2 and the modulation rate of the inverter 4. In this embodiment, the control circuit 61 has a table that defines the relationship between the voltage value of the storage voltage, the modulation rate of the inverter 4, and the phase difference θ. In other words, the table sets the phase difference θ for various combinations of the voltage value of the storage voltage and the modulation rate of the inverter 4. The method for setting the table will be described later.

The control circuit 61 acquires the voltage value of the storage voltage and the modulation factor of the inverter 4, and acquires the phase difference θ corresponding to the combination of the acquired voltage value of the storage voltage and the modulation factor of the inverter 4 from the table. The control circuit 61 then outputs pulses P1 and P2 with the phase difference θ to the combining circuit 62.

In this embodiment, the control circuit 61 also functions as a control unit for the inverter 4. Therefore, since the control circuit 61 supplies a drive signal to the inverter 4, it is aware of the frequency, switching timing, and modulation rate of the carrier component of the drive signal of the inverter 4. The control circuit 61 obtains the voltage value of the storage voltage from, for example, a voltage sensor provided between the positive and negative terminals of the storage device 2.

The combining circuit 62 combines pulses P1 and P2 to generate a combined signal Vs. The combining circuit 62 outputs the combined signal Vs to the filter circuit 63. In this embodiment, the combining circuit 62 includes resistors 62a, 62b, and a capacitor 62c. One end of the resistor 62a is connected to the output terminal of the control circuit 61 that outputs pulse P1. One end of the resistor 62b is connected to the output terminal of the control circuit 61 that outputs pulse P2. The other ends of the resistors 62a and 62b are connected to each other at a connection point CP and are also connected to the input terminal of the filter circuit 63. One end of the capacitor 62c is connected to the connection point CP, and the other end of the capacitor 62c is connected to ground potential. For example, the resistance value of the resistor 62a is substantially equal to the resistance value of the resistor 62b.

When pulses P1 and P2 are input to the combining circuit 62, the average voltage of the voltages of pulses P1 and P2 is generated at the connection point CP due to the resistance voltage division by resistors 62a and 62b. This average voltage is received by capacitor 62c, generating a combined signal Vs. Here, as shown in Figure 4, the amplitude of combined signal Vs is determined by the phase difference θ. If the amplitude of the specific frequency component of pulse P1 and the amplitude of the specific frequency component of pulse P2 are A, then the amplitude of the specific frequency component of combined signal Vs is A cos(θ/2).

The filter circuit 63 is a circuit that extracts specific frequency components from the composite signal Vs. In this embodiment, the filter circuit 63 includes a high-pass filter 65 and a low-pass filter 66.

The high-pass filter 65 is a circuit for attenuating the low-frequency components of the composite signal Vs output from the synthesis circuit 62. The high-pass filter 65 is located downstream of the synthesis circuit 62. The high-pass filter 65 attenuates low-frequency components below its cutoff frequency and passes frequency components higher than the cutoff frequency. The cutoff frequency of the high-pass filter 65 is set to a frequency lower than a specific frequency component. This removes low-frequency components, including DC components, from the composite signal Vs, generating the signal Vac. The high-pass filter 65 outputs the signal Vac to the low-pass filter 66.

In this embodiment, the high-pass filter 65 includes a capacitor 65a and a resistor 65b. One end of the capacitor 65a is connected to the output terminal (connection point CP) of the combining circuit 62, and the other end of the capacitor 65a is connected to ground potential via the resistor 65b and is also connected to the low-pass filter 66.

The low-pass filter 66 is a circuit for attenuating the high-frequency components of the signal Vac output from the high-pass filter 65. The low-pass filter 66 is located after the high-pass filter 65. The low-pass filter 66 attenuates high-frequency components above its cutoff frequency and passes frequency components below the cutoff frequency. The cutoff frequency of the low-pass filter 66 is set lower than the lower limit of the frequency range subject to noise regulations (e.g., 150 kHz) and higher than the specific frequency component. This removes the high-frequency components from the signal Vac and extracts the specific frequency component. The low-pass filter 66 outputs the specific frequency component of the composite signal Vs to the amplifier circuit 64 as the frequency component Vf.

In this embodiment, the low-pass filter 66 includes a resistor 66a and a capacitor 66b. One end of the resistor 66a is connected to the output terminal of the high-pass filter 65, and the other end of the resistor 66a is connected to ground potential via the capacitor 66b and is also connected to the amplifier circuit 64.

The amplifier circuit 64 generates the negative-phase voltage Vi by amplifying the frequency component Vf, which is a specific frequency component of the composite signal Vs output from the filter circuit 63. The amplifier circuit 64 outputs the negative-phase voltage Vi to the conversion circuit 52 (adder circuit 55). A known circuit configuration is used for the amplifier circuit 64. In this way, the generation circuit 51A outputs the negative-phase voltage Vi.

Here, the method for setting the table in the control circuit 61 will be described in detail. As described above, the amplitude of the carrier component of the detection voltage Vn can vary depending on the voltage value of the storage voltage of the storage device 2 and the modulation rate of the inverter 4. To bring the carrier component of the detection voltage Vn closer to zero, a negative-phase voltage Vi having the same amplitude as the carrier component of the detection voltage Vn must be subtracted from the detection voltage Vn. As described above, the amplitude of the negative-phase voltage Vi can be determined by the phase difference θ and the gain of the amplifier circuit 64. Therefore, by operating the power supply device 1A with each combination (voltage value of the storage voltage and modulation rate of the inverter 4) and measuring the detection voltage Vn generated in the auxiliary coil 50, the phase difference θ that results in a negative-phase voltage Vi having the same amplitude as the amplitude of the carrier component of the measured detection voltage Vn is determined as the phase difference θ corresponding to that combination. The table is set in this manner.

Next, the operation of the power supply device 1A will be described with further reference to (a) to (e) of Figure 5 and (a) to (e) of Figure 6. (a) to (e) of Figure 5 show example waveforms of each signal when the phase difference between two pulses is 135°. (a) to (e) of Figure 6 show example waveforms of each signal when the phase difference between two pulses is 0°. In (a) to (e) of Figure 5 and (a) to (e) of Figure 6, the vertical axis represents voltage (unit: V), and the horizontal axis represents time (unit: μs). In each figure, the carrier component contained in each waveform is indicated by a dashed line.

Similar to the power supply device 1, in the power supply device 1A, when DC power is supplied from the storage device 2 to the inverter 4, a noise current In is generated due to the switching operation of the inverter 4. At this time, the noise current In flows through coil 31, coil 32, and auxiliary coil 50, and a detection voltage Vn is generated in the auxiliary coil 50. Note that before the attenuation current Ic is generated, only the noise current In flows through the auxiliary coil 50; after the attenuation current Ic is generated, a combined current of the noise current In and the attenuation current Ic flows; however, in this embodiment, the initial stage before the attenuation current Ic is generated will be described.

Then, the generation circuit 51A generates a negative-phase voltage Vi that attenuates the carrier component of the detection voltage Vn. Specifically, the control circuit 61 acquires the voltage value of the storage voltage of the storage device 2 and the modulation factor of the inverter 4, and, by referring to the table, determines the phase difference θ corresponding to the combination of these values. The control circuit 61 then outputs pulses P1 and P2 to the combining circuit 62 with the phase difference θ. For example, when the phase difference θ is 135°, pulses P1 and P2 are output with a phase difference of 135°, as shown in (a) and (b) of Figure 5. When the phase difference θ is 0°, pulses P1 and P2 are output with a phase difference of 0°, as shown in (a) and (b) of Figure 6.

As shown in Figures 5(c) and 6(c), pulses P1 and P2 are combined in the combining circuit 62 to generate a combined signal Vs having an amplitude corresponding to the phase difference θ. As shown in Figures 5(d) and 6(d), low-frequency components, including DC components, are removed from the combined signal Vs by the high-pass filter 65 to generate a signal Vac. As shown in Figures 5(e) and 6(e), high-frequency components are removed from the signal Vac by the low-pass filter 66 to extract a specific frequency component of the combined signal Vs, which is output to the amplifier circuit 64 as frequency component Vf. For example, when the phase difference θ is 135°, the amplitude of the carrier component of frequency component Vf is 1.2 V, as shown in Figure 5(e). When the phase difference θ is 0°, the amplitude of the carrier component of frequency component Vf is 3.2 V, as shown in Figure 6(e). The frequency component Vf is then amplified by the amplifier circuit 64 to generate the negative-phase voltage Vi.

Then, in the adder circuit 55 of the conversion circuit 52, the detection voltage Vn and the negative-phase voltage Vi are added together to generate the sum voltage Va. The sum voltage Va has a waveform in which the carrier component of the detection voltage Vn is subtracted from the detection voltage Vn, and the amplitude of the sum voltage Va is smaller than the amplitude of the detection voltage Vn.

The sum voltage Va is then amplified by the amplifier circuit 56, and the amplified sum voltage Va is converted by the output capacitor 57 into an attenuation current Ic that is in opposite phase to the noise current In. The attenuation current Ic is then supplied to the inverter 4 (connection line 34), thereby attenuating the harmonic components of the noise current In.

The noise attenuation circuit 5A described above also has the same configuration as the noise attenuation circuit 5, and therefore achieves the same effects as the noise attenuation circuit 5. Furthermore, the noise attenuation circuit 5A can generate the negative-phase voltage Vi without using an oscillator. Therefore, the circuit scale of the noise attenuation circuit 5A can be reduced compared to the noise attenuation circuit 5.

The amplitude of the carrier component of the detection voltage Vn can be determined based on the voltage value of the storage voltage of the storage device 2 and the modulation rate of the inverter 4. The amplitude of the composite signal Vs can be changed by adjusting the phase difference θ between pulse P1 and pulse P2. The amplitude of the negative-phase voltage Vi is determined based on the amplitude of the composite signal Vs. Therefore, by setting the phase difference θ based on the voltage value of the storage voltage and the modulation rate of the inverter 4, the amplitude of the negative-phase voltage Vi can be brought closer to the amplitude of the carrier component of the detection voltage Vn. This allows the amplitude of the added voltage Va to be further reduced, further increasing the gain of the amplifier circuit 56. As a result, the common-mode noise attenuation effect can be further improved.

Although the embodiments of the present disclosure have been described in detail above, the noise attenuation circuit according to the present disclosure is not limited to the above embodiments.

The control circuit 53 and the control circuit 61 do not have to function as a control unit for the inverter 4. In other words, the power supply device 1 may include a control unit for the inverter 4 separate from the control circuit 53. Similarly, the power supply device 1A may include a control unit for the inverter 4 separate from the control circuit 61.

The control circuit 53 may set the amplitude of the negative-phase voltage Vi based on either the voltage value of the storage voltage of the storage device 2 or the modulation rate of the inverter 4. Similarly, the control circuit 61 may set the phase difference θ based on either the voltage value of the storage voltage of the storage device 2 or the modulation rate of the inverter 4.

Instead of a table, the control circuit 53 may set the amplitude of the negative-phase voltage Vi using a function that defines the relationship between the voltage value of the storage voltage of the storage device 2, the modulation rate of the inverter 4, and the amplitude of the negative-phase voltage Vi. Similarly, the control circuit 61 may set the phase difference θ using a function that defines the relationship between the voltage value of the storage voltage of the storage device 2, the modulation rate of the inverter 4, and the phase difference θ, instead of a table.

The control circuit 53 does not need to set the amplitude of the negative-phase voltage Vi. Similarly, the control circuit 61 does not need to set the phase difference θ.

In the filter circuit 63, the order of the high-pass filter 65 and the low-pass filter 66 may be reversed. That is, the low-pass filter 66 may be provided after the synthesis circuit 62, and the high-pass filter 65 may be provided after the low-pass filter 66. Instead of the high-pass filter 65 and the low-pass filter 66, the filter circuit 63 may include a band-pass filter capable of extracting specific frequency components from the synthesis signal Vs.

The generation circuit 51A does not have to include the amplifier circuit 64.

1, 1A...power supply device, 2...power storage device, 4...inverter, 5, 5A...noise attenuation circuit, 30...core, 31, 32...coil, 50...auxiliary coil, 51, 51A...generation circuit, 52...conversion circuit, 53, 61...control circuit, 54...oscillator, 55...addition circuit, 56...amplification circuit, 62...synthesizing circuit, 63...filter circuit, M...motor.

Claims (6)

A noise attenuation circuit that is provided between a power storage device and an inverter that converts DC power supplied from the power storage device into AC power, and that generates an attenuation current for attenuating a noise current generated in the inverter,
an auxiliary coil wound around a core of a common mode choke coil provided between the power storage device and the inverter;
a conversion circuit that generates the attenuation current based on a voltage detected by the auxiliary coil;
a generating circuit for generating a negative-phase voltage that attenuates the carrier component of the noise current ;
Equipped with
The conversion circuit
an adder circuit that generates a sum voltage by adding the detected voltage and the negative-phase voltage;
an amplifier circuit provided at a subsequent stage of the adder circuit and amplifying the added voltage ;
the carrier wave component of the noise current is generated by a carrier wave component of a drive signal for driving the inverter,
the negative-phase voltage has a frequency equal to the frequency of the carrier wave component of the drive signal, a phase equal to the phase of the carrier wave component of the drive signal, and an amplitude set based on a voltage value of a storage voltage that is a voltage of the storage device and a modulation factor of the inverter;
Noise attenuation circuit. The noise attenuation circuit of claim 1 , wherein the generating circuit comprises a control circuit that sets the frequency and the phase of the negative-phase voltage based on the drive signal. The noise attenuation circuit of claim 2, wherein the generation circuit further includes an oscillator that outputs a sine wave signal having the frequency and phase set by the control circuit as the antiphase voltage. the control circuit sets the amplitude of the negative -phase voltage based on the voltage value of the storage voltage and the modulation factor of the inverter;
4. The noise attenuation circuit of claim 3, wherein the oscillator outputs the sinusoidal signal as the opposite-phase voltage, the sinusoidal signal further having the amplitude set by the control circuit. the control circuit outputs a first pulse and a second pulse having the same frequency as the carrier wave component of the noise current ;
The generating circuit
a combining circuit that combines the first pulse and the second pulse to generate a combined signal;
a filter circuit that extracts a frequency component having the same frequency as the carrier wave component of the noise current from the composite signal,
The noise attenuation circuit according to claim 2 , wherein the generation circuit outputs the negative-phase voltage based on the extracted frequency component. The noise attenuation circuit according to claim 5 , wherein the control circuit sets a phase difference between the first pulse and the second pulse based on the voltage value of the storage voltage and the modulation factor of the inverter.