JP7810892B2 - Semiconductor Devices - Google Patents

Description

The present invention relates to a semiconductor device, and in particular to a bidirectional analog switch with two reverse-connected MOSFETs.

A bidirectional analog switch is a semiconductor device that switches a circuit on and off depending on the state of an input signal. A specific configuration example is two MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) connected in reverse with a common drain. An example of a bidirectional analog switch with this configuration is Patent Document 1. Patent Document 1 discloses a bidirectional switch that includes a first MOS switch M1, a second MOS switch M2, and an N-well region 2 that serves as the drain of M1 and M2. In other words, M1 and M2 are connected in reverse with a common drain. The N-well region 2 is formed in the region between a first gate electrode 71a formed in a first trench 3 via a gate insulating film 6, and a second gate electrode 72a formed in a second trench 3 at a distance from the first trench 3 via a gate insulating film 6.

Another specific configuration example of a bidirectional analog switch is one in which two MOSFETs are reverse-connected with a common source. An example of a bidirectional analog switch with this configuration is disclosed in Patent Document 2. Figure 1 of Patent Document 2 discloses a bidirectional switch in which a first MOS switch 16 and a second MOS switch 17 are reverse-connected with a common source.

JP 2010-016221 A Patent No. 5485108

When forming a semiconductor device (bidirectional analog switch) on an SOI (silicon on insulator) substrate, the configuration described in Patent Document 1 does not require an isolation region between M1 and M2. However, the source and gate of each device must be positioned independently, and a circuit for driving the gate must be provided for each device, which increases the size of the semiconductor device.

On the other hand, with the configuration of Patent Document 2, it is possible to connect the sources and gates of elements 16 and 17 and share a circuit for driving the gates, but this requires the provision of an isolation region for each of elements 16 and 17, which poses the problem of increasing the size of the semiconductor device.

In view of the above circumstances, the object of the present invention is to provide a structure that allows for a smaller size than conventional semiconductor devices (bidirectional analog switches) in which two MOSFETs are reverse-connected.

One aspect of the present invention to solve the above problem is a semiconductor device comprising a first switching element formed on an SOI substrate and a second switching element formed on the SOI substrate and reverse-connected to the first switching element with a common source, characterized in that a trench gate electrode common to the first switching element and the second switching element is provided in an element isolation region formed between the first switching element and the second switching element.

According to the present invention, in a semiconductor device (bidirectional analog switch) in which two MOSFETs are reverse-connected, a trench gate structure is provided that shares the gates of the two MOSFETs, and this serves as an isolation region. This eliminates the need for an additional isolation region, and allows for a structure that is smaller in size than conventional structures.

Other issues, configurations, and advantages will become clear from the description of the following embodiments.

A circuit diagram showing an example of a semiconductor device. FIG. 1 is a plan view showing an example of the structure of a conventional semiconductor device; 2. Cross-sectional view taken along the line E-E' in FIG. FIG. 1 is a plan view showing a structure of a semiconductor device according to a first embodiment; 4A-4B are cross-sectional views taken along the line A-A' in FIG. FIG. 10 is a plan view showing the structure of a semiconductor device according to a second embodiment; 6A-6B line cross section FIG. 10 is a plan view showing the structure of a semiconductor device according to a third embodiment; 7A is a cross-sectional view taken along the line CC' in FIG. FIG. 10 is a plan view showing the structure of a semiconductor device according to a fourth embodiment; 8. A cross-sectional view taken along the line DD' in FIG. FIG. 10 is a plan view showing the structure of a semiconductor device according to a fifth embodiment;

Embodiments of the present invention will be described below using the drawings. Note that the same components in each drawing will be assigned the same reference numerals, and detailed explanations of overlapping components will be omitted.

Figure 1 is a circuit diagram showing an example of a semiconductor device (bidirectional analog switch). In this specification, the term "semiconductor device" refers to a bidirectional analog switch in which two or more MOSFETs are reverse-connected. As shown in Figure 1, the semiconductor device has a first switching element 100a and a second switching element 100b, which are reverse-connected in series with a common gate and source.

The following describes the configuration of a conventional semiconductor device formed on an SOI substrate. Figure 2 is a plan view showing an example of the structure of a conventional semiconductor device, and Figure 3 is a cross-sectional view taken along line E-E' in Figure 2. The general configuration of a switching element that constitutes a conventional bidirectional analog switch, as shown in Figures 2 and 3, is a stack of a support substrate 1, a buried oxide film 2, and a semiconductor substrate 3, with a layer that serves as the source and drain regions of the switching element provided on top of the semiconductor substrate 3. The semiconductor device shown in Figures 2 and 3 has a first switching element 100a and a second switching element 100b as switching elements, and each of the first switching element 100a and the second switching element 100b has an element isolation region 4. The element isolation region 4 is composed of an insulating film 10 and polysilicon 11 sandwiched between the insulating films 10.

The first switching element 100a and the second switching element 100b each have a drain n+ layer (drain layer) 9 and drain wiring 13a, 13b connected to it near their centers, a source p layer (source layer) 7 located a predetermined distance L1 away from the drain n+ layer 9, and a gate oxide film 5 and gate electrode 6 disposed on top of the source p layer 7. The source n+ layers 8 and source p+ layers 7a formed within the source p layer 7 are connected by a common source wiring 12, and the gate electrodes 6 are connected by a common gate wiring 14.

The configuration of the conventional bidirectional analog switch described above had the problem of increasing the element size because it was necessary to provide a gap between the element isolation regions 4 of the first switching element 100a and the second switching element 100b, and because the gate electrode 6 had to be formed laterally across the drain electrode and source electrode.

Furthermore, in order to connect each element outside the element, it is necessary to route source wiring and gate wiring, which increases the wiring area and necessitates a multi-layer wiring structure, resulting in higher process costs.

Next, we will explain the configuration of the semiconductor device of the present invention, which solves the above-mentioned conventional problems. Figure 4 is a plan view showing the structure of the semiconductor device of Example 1, and Figure 5 is a cross-sectional view taken along line A-A' in Figure 4. The semiconductor device of Example 1 surrounds switching elements 100a and 100b, which are connected in reverse in series, with a common element isolation region 4, and further comprises the oxide film of element isolation region 4 as gate oxide film 5, and buried polysilicon sandwiched between oxide films 5 of element isolation region 4 as gate electrode 6. In other words, in this example, the gate electrode of first switching element 100a and the gate electrode of second switching element 100b have a common trench gate structure.

This eliminates the area between the isolation regions of each switching element, which was required in conventional bidirectional analog switch structures. Furthermore, the gate electrodes formed on each element in conventional structures can be shared, and the channel region can be formed in the depth direction of the element, thereby reducing element size. For example, let L1 be the distance between the source p layer 7 and the drain n+ layer 9 in Figure 3, and L2 be the distance from the isolation region 4 to the edge of the source p layer 7. In conventional structures, an area is required to form the gate electrode (or channel region) between the drain electrode and the source electrode. In contrast, in the structure of Example 1 shown in Figure 5, assuming the same breakdown voltage as the structure in Figure 3, the distance between the source p layer 7 and the drain n+ layer 9 is L1. However, because the gate electrode is formed in the isolation region 4 and the channel region is formed along the isolation region 4, the distance L3 from the isolation region 4 to the edge of the source p layer 7 can be shorter than L2. This allows for a reduction in element size.

In addition, the configuration of Example 1 shown in Figure 4 does not require the gate wiring 14 to be routed outside the device, as in the conventional configuration shown in Figure 2, so it is possible to reduce the wiring area outside the device compared to conventional structures and also eliminate the need for a multi-layer wiring structure.

Figure 6 is a plan view showing the structure of the semiconductor device of Example 2, and Figure 7 is a cross-sectional view taken along line B-B' in Figure 6. The source p layer 7 of Example 1 described above is formed in regions at both ends of the first switching element 100a and the second switching element 100b, facing the drain n+ region 8 of each of the first switching element 100a and the second switching element 100b in the longitudinal direction, sandwiching the drain n+ region 8. The semiconductor device of this example is characterized in that the source p layer 7 is provided only in one region facing the drain n+ layer 9 in the longitudinal direction. With this structure, although the on-resistance is higher than in Example 1, the distance from the drain n+ layer 9 to the other element isolation region 4 where the source p layer 7 is not formed (L4 shown in Figure 7) can be reduced by more than the distance from the drain n+ layer 9 to the element isolation region 4 (L1 + L3) in the semiconductor device of Example 1, thereby enabling further reduction in element size.

Furthermore, as shown in Figure 6, since there is no need to route the source wiring 12 outside the element, it is possible to reduce the wiring area compared to the structure of Example 1.

Figure 8 is a plan view showing the structure of the semiconductor device of Example 3, and Figure 9 is a cross-sectional view taken along line CC' in Figure 8. As shown in Figures 8 and 9, the structure of the semiconductor device of Example 3 is characterized in that the source p layer 7 of the first switching element 100a and the second switching element 100b is formed in a region surrounding the respective drain n+ layer 9 on three sides. This structure makes it possible to reduce the on-resistance compared to the structure of Example 1, and also makes it possible to reduce the wiring area because there is no need to route the source wiring 12 outside the element.

Figure 10 is a plan view showing the structure of a semiconductor device of Example 4, and Figure 11 is a cross-sectional view taken along line D-D' in Figure 10. The configuration of the semiconductor device of this example connects four switching elements. From the left in the figure, the first and third switching elements share a drain electrode, and the second and fourth switching elements share a drain electrode. The source p layers 7 of the first and fourth switching elements 100 are formed in one region spaced apart from the drain n+ layer 9, and the source p layers 7 of the second and third switching elements are formed in both regions spaced apart from the drain n+ layer 9. This structure makes it possible to realize a bidirectional analog switch with low on-resistance using a small element size.

Note that the structures shown in Figures 10 and 11 show an example of a bidirectional analog switch formed by switching element 100a, which has two switching elements connected together, and switching element 100b, which has two switching elements connected in parallel, but it is clear that the number of elements connected in parallel does not need to be limited to two.

Figure 12 is a plan view showing the structure of a semiconductor device according to Example 5. The configuration of the semiconductor device shown in Figure 12 is a bidirectional analog switch formed by connecting multiple switching elements according to Example 3 shown in Figure 8 in parallel. The effects of the present invention can also be obtained in this configuration.

As explained above, the present invention has demonstrated that it is possible to provide a structure that allows for a smaller size than conventional semiconductor devices (bidirectional analog switches) with two reverse-connected MOSFETs.

The present invention is not limited to the above-described embodiments, and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

1...Support (SOI) substrate, 2...Buried oxide film, 3...Semiconductor substrate, 4...Element isolation region, 5...Gate oxide film, 6...Gate electrode, 7...Source p layer, 9...Drain n+ layer, 10...Insulating film, 11...Polysilicon, 12...Source wiring, 13a...First drain wiring, 13b...Second drain wiring, 14...Gate wiring, 100a...First switching element, 100b...Second switching element.

Claims (6)

A semiconductor device including a first switching element and a second switching element reversely connected to the first switching element,
the first switching element and the second switching element are formed on a common SOI substrate;
a trench gate electrode common to the first switching element and the second switching element, the trench gate electrode being located in an element isolation region formed between the first switching element and the second switching element; The semiconductor device according to claim 1, wherein the source layers of the first switching element and the second switching element are provided only in one of the regions that face each other in the longitudinal direction of the drain layer. The semiconductor device according to claim 1, wherein the source layers of the first switching element and the second switching element are formed in regions surrounding the respective drain layers on three sides. The semiconductor device according to any one of claims 1 to 3, wherein the first switching element and the second switching element are each configured by connecting two or more switching elements in parallel. The semiconductor device according to claim 4, wherein one of the first switching elements connected in parallel and one of the second switching elements connected in parallel are alternately arranged. The semiconductor device according to claim 5, wherein the first switching element and the second switching element arranged at both ends are provided only in one region where the source layer faces the drain layer in the longitudinal direction.