JP7814735B2 - Audio Output Circuit - Google Patents

Description

The present invention relates to an audio output circuit.

There are audio output devices installed in devices that output audio such as guide voices and sound effects. One such audio output device known is one that converts audio data into a PWM signal (Pulse Width Modulation) and drives a speaker based on the PWM signal to output audio at a predetermined volume. For example, Patent Document 1 below discloses an audio playback device (audio output device) that includes an inexpensive microcomputer (hereinafter, "microcomputer" is abbreviated as "micon") and an H-bridge circuit (drive circuit) (see Figure 1(B) of Patent Document 1).

In the above audio playback device, the microcomputer's memory stores a driver, which is middleware for driving the audio output devices (H-bridge circuit, speaker). The microcomputer (CPU) converts compressed audio data into a PCM format digital audio signal, and then, based on the driver stored in memory, converts the PCM format audio signal into a PWM signal whose pulse width is proportional to the signal level.

In addition, in the above audio playback device, the H-bridge circuit is composed of four field effect transistors (FETs). This H-bridge circuit amplifies power by switching the four FETs based on a PWM signal from the microcontroller, driving the speaker. This allows audio to be played at a set volume.

The above audio playback device uses a fully digital system, with all processes from inputting the digital audio signal to generating the PWM signal that drives the speaker being carried out digitally. Compared to devices that first convert the signal to analog, this type of fully digital audio playback device generates less heat and consumes less power, avoids signal degradation due to noise contamination, and also significantly reduces component costs.

Japanese Patent No. 6308705 (paragraphs 0021, 0022, Figure 1(B))

The above-mentioned audio playback device plays audio at a predetermined volume based on the input audio signal, so it is not expected that the volume will be adjusted after installation in the device. In this regard, if the above-mentioned audio playback device were configured to allow free control of the audio volume even after installation in an audio output device, each user would be able to adjust the volume to their desired level, thereby expanding its applications. Therefore, in such fully digital audio playback devices, a configuration using a digital volume control is conceivable. For example, when lowering the audio volume, the amplitude of the digital data output by the PWM signal is reduced using signed division processing, thereby lowering the modulation degree of the PWM signal and thereby reducing the amplitude of the output audio signal.

However, with this configuration, if the bit depth that can be reproduced by the audio playback device is relatively small (for example, 16 bits), lowering the volume using the volume control method described above reduces the number of effective bits of the signal components in the digital data (for example, to 16 bits - 3 bits = 13 bits), which results in quantization noise, raising the noise floor, and reducing the quality of the audio (i.e., the sound quality becomes poor).

To avoid sound quality degradation when the volume is turned down using a digital volume control, it is sufficient to ensure an effective bit depth of about 16 bits in the output digital data. However, in this case, if the number of bits controlled by the volume is 4 to 8 bits, the reproducible bit depth (N _D ) of the audio playback device must be about 24 bits. If the sampling rate (f _S ) is then 48 kilohertz (kHz), the frequency of the timer clock signal that generates the PWM signal (2 to the power of N _D × f _S ) will be 800 gigahertz (GHz) or more, which is extremely difficult to achieve with current technology.

The present invention was made in consideration of the above-mentioned circumstances, and aims to provide an audio output circuit that can adjust the volume and output good-quality (i.e., high-quality) audio even at low volumes while employing a fully digital system.

In order to achieve the above object, the present invention provides an audio output circuit comprising: a microcomputer that generates a differential PWM signal based on audio data; and a drive circuit that switches an H-bridge circuit in accordance with the differential PWM signal to output a drive voltage to a speaker, the audio output circuit further comprising a variable voltage power supply that applies a variable voltage to the drive circuit and causes the drive circuit to output a drive voltage corresponding to the variable voltage, the drive circuit comprising a logic level voltage conversion circuit that converts the voltage of an input PWM signal to a voltage level different from this voltage according to the voltages of the microcomputer power supply and the variable voltage power supply, and inputs the converted voltage to the gate terminals of PMOSFETs in the H-bridge circuit, the PMOSFETs having a source terminal connected to the variable voltage power supply and a gate terminal connected to the variable voltage power supply via a resistor, the logic level voltage conversion circuit having a Schottky barrier diode connected between the gate terminal of the PMOSFET and the variable voltage power supply, and a capacitor connected between the anode terminal of the Schottky barrier diode and the PWM signal input terminal, the output voltage of the H-bridge circuit being controlled by changing the voltage of the variable voltage power supply, thereby making it possible to vary the output volume of the speakers.

In the above configuration , the FETs constituting the H -bridge circuit may be two PMOSFETs and two NMOSFETs, the drain terminals of the two NMOSFETs may be connected to the drain terminals of different PMOSFETs, the gate terminals of the NMOSFETs may be connected to the PWM signal input terminal and to ground via a resistor, and the source terminals of the NMOSFETs may be connected to ground. Furthermore, in the above configuration, the logic level voltage conversion circuit may apply a voltage of a level equal to the signal voltage of the PWM signal to the gate terminals of the NMOSFETs, and in certain cases, apply a voltage of a level obtained by subtracting the voltage value of the variable voltage power supply from the voltage value of the power supply voltage of the microcomputer to the gate terminal of the PMOSFET.

This invention allows the volume to be adjusted by changing the voltage of the variable voltage power supply, and employs a fully digital system to output high-quality audio even at low volumes.

FIG. 2 is a block diagram showing an example of a schematic configuration of an audio output circuit. FIG. 2 is a schematic diagram illustrating an example of a main part of an audio output circuit. FIG. 2 is a schematic diagram illustrating an example of a main part of an audio output circuit.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to these. In addition, in order to explain the embodiments, the drawings may be drawn to a different scale, such as by enlarging or emphasizing certain parts.

Figure 1 is a block diagram showing an example of the schematic configuration of an audio output circuit 100. Figure 1 shows the audio output circuit 100 configured together with a speaker SP to form an audio output device 1. The audio output device 1 in Figure 1 is configured to include the audio output circuit 100 and the speaker SP, and outputs audio from the speaker SP by driving the speaker SP based on a PWM signal generated from audio data. As shown in Figure 1, the audio output circuit 100 includes a microcontroller 10, a voltage variable power supply 20, a logic level voltage conversion circuit 30, and an H-bridge circuit 40. The audio output circuit 100 employs a fully digital system, and as described below, all processes from the input of the audio signal (digital data) to the generation of the PWM signal that drives the speaker are performed digitally.

The microcomputer 10 has a CPU 11, memory 12, and timers 13 and 14. The microcomputer 10 is a circuit in which the CPU 11, memory 12, and timers 13 and 14 are integrated into a single LSI chip (Large Scale Integration Circuit).

The CPU 11 decodes the compressed audio data in the memory 12 and converts it into a PCM format audio signal based on the audio playback middleware 15 described below. Note that a PCM format audio signal is discrete digital data with a predetermined sampling frequency.

The CPU 11 also controls the timers 13 and 14 built into the microcomputer 10 based on the audio playback middleware 15 stored in memory 12 to generate a PWM signal based on the signal level of the PCM audio signal. The PWM signal has a constant output pulse period. However, the PWM signal has different pulse "H" (high level) and "L" (low level) times (widths) depending on the audio signal level. Here, the percentage of the PWM signal that has an "H" signal level within one period is called the duty ratio.

Memory 12 stores audio playback middleware 15. Audio playback middleware 15 is a driver for driving speaker SP. Memory 12 also stores compressed audio data and middleware for decoding and playing compressed audio data.

The timer 13 and other components, under the control of the audio playback middleware 15, convert the PCM audio signal into a PWM signal with a pulse width that corresponds to the signal level. The PWM signal generated here is a drive signal (a signal input to the signal input terminal of the H-bridge circuit 40) that drives the H-bridge circuit 40, and is a pair of differential signals consisting of a PWM signal (PWM0) and a PWM signal (PWM1). This differential PWM signal is generated, for example, as follows based on the PCM audio signal.

That is, the positive output PWM signal (e.g., PWM0) and the negative output PWM signal (e.g., PWM1) are in phase. Then, a differential signal is generated by reversing the direction of pulse width changes for the positive output PWM signal and the negative output PWM signal. The output range of the differential signal is +100% to 0% to -100%. For example, if the duty ratio of the positive output PWM signal is 40% and the duty ratio of the negative output PWM signal is 60%, the differential component (differential output) will be +20%. Conversely, if the duty ratio of the positive output PWM signal is 60% and the duty ratio of the negative output PWM signal is 40%, the differential component will be -20%. Furthermore, if the duty ratio of the positive output PWM signal is 30% and the duty ratio of the negative output PWM signal is 70%, the differential component will be +40%. When the differential output is 0%, the duty ratio of the positive output and negative output PWM signals is 50%.

The microcontroller 10 outputs two PWM signals (PWM0, PWM1) generated by the timer 13 etc. from two output pins to the H-bridge circuit 40 via the logic level voltage conversion circuit 30.

The variable voltage power supply 20 outputs a power supply voltage Vdd to the logic level voltage conversion circuit 30 and the H-bridge circuit 40, and is configured to be able to change the voltage value of the output voltage Vdd. The variable voltage power supply 20 includes a voltage source and a voltage variable device that changes the magnitude of the power supply voltage Vdd output by the voltage source. The voltage variable device changes the voltage value of the power supply voltage Vdd in response to external operations, signal reception, etc. As an example of the specific configuration of such a voltage variable device, Figure 1 shows a variable resistor VR connected to the power supply. The variable resistor VR has an operating unit (not shown) (e.g., a volume control knob), and changes the voltage value of the power supply voltage Vdd by changing its resistance value in response to the amount of operation of the operating unit (e.g., the amount of rotation of the knob).

In other words, when the user operates the operation unit, the resistance value of the variable resistor VR changes according to the operation level, and the change in the resistance value of the variable resistor VR changes the voltage value of the power supply voltage Vdd output by the voltage variable power supply 20. When the voltage value of the power supply voltage Vdd changes, the volume of the output sound from the audio output device 1 changes accordingly. Therefore, the audio output circuit 100 is configured so that the user can adjust the volume of the sound output device 1 by controlling the magnitude of the voltage value of the power supply voltage Vdd output by the voltage variable power supply 20 when operating the operation unit.

The logic level voltage conversion circuit 30 receives two PWM signals (PWM0, PWM1) output from the microcomputer 10 and also receives the power supply voltage Vdd from the variable voltage power supply 20. The logic level voltage conversion circuit 30 then converts the voltage levels (logic level voltages) of the two input PWM signals (PWM0, PWM1) and outputs the converted PWM signals (PWM0, PWM1) to the H-bridge circuit 40. The configuration and function of this logic level voltage conversion circuit 30 will be described in detail below.

The H-bridge circuit 40 receives two PWM signals (PWM0, PWM1) output from the microcomputer 10. The H-bridge circuit 40 outputs a signal (drive signal) to the speaker SP by switching (opening and closing) four field-effect transistors (FET1 to FET4) (see Figure 2) based on the PWM signals (PWM0, PWM1) from the microcomputer 10, thereby driving the speaker SP. At this time, the H-bridge circuit 40 passes current through the speaker SP (which serves as a load) for the duration of the difference in pulse width between the two PWM signals (PWM0, PWM1), thereby driving the speaker SP.

The speaker SP is a dynamic speaker, and includes a moving coil and a diaphragm (both not shown) arranged in a magnetic field. When a current flows through the moving coil, the moving coil vibrates, and this vibration is transmitted to the diaphragm, thereby outputting sound. The speaker SP is connected to an H-bridge circuit 40, and outputs sound according to the voltage applied via the H-bridge circuit 40. Note that the speaker SP is not limited to a dynamic speaker, and may be, for example, a piezoelectric speaker (sometimes called a piezo speaker or piezoelectric sounder) that has a piezoelectric element. In this case, the speaker SP is driven by applying a voltage to the piezoelectric element, and outputs sound.

Figure 2 is a schematic diagram showing an example of the main components of the audio output circuit 100. Note that in the following description of Figure 2, up, down, left, and right refer to the directions when viewing Figure 2 in the direction of the symbols. As shown in Figure 2, the audio output circuit 100 includes two half-bridge circuits 40A and 40B that form an H-bridge circuit 40, and two logic-level voltage conversion circuits 30A and 30B. Next, the specific configurations and operations of the logic-level voltage conversion circuit 30 and the H-bridge circuit 40 will be described.

Logic level voltage conversion circuit 30A is connected between the signal input terminal that inputs the PWM signal (PWM0) and half-bridge circuit 40A. Logic level voltage conversion circuit 30B is connected between the signal input terminal that inputs the PWM signal (PWM1) and half-bridge circuit 40B. These half-bridge circuits 40A, 40B and logic level voltage conversion circuits 30A, 30B constitute a drive circuit 60 that outputs a drive signal to speaker SP. That is, drive circuit 60 that drives speaker SP is composed of a first drive circuit 50A (the left part of drive circuit 60) consisting of half-bridge circuit 40A and logic level voltage conversion circuit 30A, and a second drive circuit 50B (the right part of drive circuit 60) consisting of half-bridge circuit 40B and logic level voltage conversion circuit 30B.

The drive circuit 60 includes four field-effect transistors FET1 to FET4. In the following description, the field-effect transistors FET1 to FET4 will be referred to simply as transistors FET1 to FET4.

The drive circuit 60 is configured to switch transistors FET1 to FET4 in response to the input PWM signals (PWM0, PWM1). That is, when the PWM signal (PWM0) is "H," the upper left transistor FET1 is off (open) and the lower left transistor FET2 is on (open). When the PWM signal (PWM0) is "L," the first drive circuit 50A turns transistor FET1 on (closed) and transistor FET2 off (open). In this way, transistors FET1 and FET2 are configured to alternately turn on and off (open and close) based on the signal level ("H," "L") of the PWM signal (PWM0). In addition, when the PWM signal (PWM1) of the second drive circuit 50B is "H," the upper right transistor FET3 is off (open) and the lower right transistor FET4 is on (closed); when the PWM signal (PWM1) is "L," the transistor FET3 is on (closed) and the transistor FET4 is off (open). In this way, the transistors FET3 and FET4 are configured to alternately turn on and off (open and closed) based on the signal level ("H," "L") of the PWM signal (PWM1).

Of the four transistors FET1 and others shown in Figure 2, the two upper transistors FET1 and FET3 are P-type MOS (Metal-Oxide-Semiconductor) FETs. In the following explanation, P-type MOSFETs will be referred to as PMOSFETs. The two lower transistors FET2 and FET4 are N-type MOSFETs. In the following explanation, N-type MOSFETs will be referred to as NMOSFETs. All four of these transistors FET1 to FET4 are enhancement type. PMOSFETs (FET1 and FET3) turn on when a voltage of a predetermined magnitude and negative with respect to the source voltage is applied to their gates. NMOSFETs (FET2 and FET4) turn on when a voltage of a predetermined magnitude and positive with respect to the source voltage is applied to their gates. In this way, transistors such as FET1 turn on when a specific voltage is applied, and the voltage between the gate and source (hereinafter simply referred to as the "gate-source voltage") required to switch transistors such as FET1 is called the threshold voltage, also known as threshold voltage.

In the first drive circuit 50A, the source terminal and gate terminal of transistor FET1 are each connected to the voltage variable power supply 20. The drain terminal of transistor FET1 is connected to the drain terminal of transistor FET2. A resistor R11 (e.g., resistance value 10 kilohms (kΩ)) is connected between the gate terminal of transistor FET1 and the voltage variable power supply 20. A resistor R12 (e.g., resistance value 100 ohms (Ω)) and a Schottky barrier diode SBD1 are connected in series between the gate terminal of transistor FET1 and the voltage variable power supply 20. The gate terminal of transistor FET2 is connected to a signal input terminal that inputs a PWM signal (PWM0). The source terminal of transistor FET2 is connected to ground (GND). A resistor R21 (e.g., resistance value 10 kilohms (kΩ)) is connected between the gate terminal of transistor FET2 and ground. Resistor R22 (e.g., resistance value 100 ohms (Ω)) is connected between the gate terminal of transistor FET2 and the signal input terminal for inputting the PWM signal (PWM0). Capacitor C1 (e.g., capacitance 0.1 microfarads (μF)) is connected between the gate terminal side of transistor FET1 (connection point H1 between the anode terminal of Schottky barrier diode SBD1 and resistor R12) and the gate terminal side of transistor FET2 (connection point L1 between the signal input terminal and resistor R22).

The second drive circuit 50B, which includes transistors FET3 and FET4, resistors R31, R32, R41, and R42, a Schottky barrier diode SBD2, and a capacitor C2, is configured similarly to the first drive circuit 50A, which includes transistors FET1 and FET2, resistors R11, R12, R21, and R22, a Schottky barrier diode SBD1, and a capacitor C1. Specifically, the source and gate terminals of transistor FET3 are each connected to the variable voltage power supply 20. The drain terminal of transistor FET3 is connected to the drain terminal of transistor FET4. Resistor R31 (e.g., resistance value 10 kilohms (kΩ)) is connected between the gate terminal of transistor FET3 and the variable voltage power supply 20. Resistor R32 (e.g., resistance value 100 ohms (Ω)) and Schottky barrier diode SBD2 are connected in series between the gate terminal of transistor FET3 and the variable voltage power supply 20. The gate terminal of transistor FET4 is connected to a signal input terminal that inputs a PWM signal (PWM1). The source terminal of transistor FET4 is connected to ground. A resistor R41 (e.g., resistance value 10 kilohms (kΩ)) is connected between the gate terminal of transistor FET4 and ground. A resistor R42 (e.g., resistance value 100 ohms (Ω)) is connected between the gate terminal of transistor FET4 and the signal input terminal that inputs the PWM signal (PWM1). A capacitor C2 (e.g., capacitance 0.1 microfarads (μF)) is connected between the gate terminal of transistor FET3 (connection point H2 between the anode terminal of Schottky barrier diode SBD2 and resistor R32) and the gate terminal of transistor FET4 (connection point L2 between the signal input terminal and resistor R22).

A speaker SP is connected between a connection point O1 between the drain terminals of transistors FET1 and FET2, and a connection point O2 between the drain terminals of transistors FET3 and FET4. Note that connection point O1 is also the output terminal of the first drive circuit 50A, and connection point O2 is also the output terminal of the second drive circuit 50B.

In the drive circuit 60, when all four transistors FET1 to FET4 are off, no voltage is applied to the speaker SP. When transistors FET1 and FET4 are on and transistors FET2 and FET3 are off, current flows through the path (1) in Figure 2 (variable voltage power supply 20, transistor FET1, speaker SP, transistor FET4, ground). At this time, current flows in a predetermined direction through the speaker SP, and the power supply voltage Vdd of the voltage variable power supply 20 is applied to the speaker SP. Conversely, when transistors FET2 and FET3 are on and transistors FET1 and FET4 are off, current flows through the path (2) in Figure 2 (variable voltage power supply 20, transistor FET3, speaker SP, transistor FET2, ground). At this time, current flows in the opposite direction to the predetermined direction through the speaker SP, and the power supply voltage Vdd of the voltage variable power supply 20 is applied to the speaker SP.

The drive circuit 60 applies the power supply voltage Vdd from the variable voltage power supply 20 to the speaker SP to drive the speaker SP, causing the speaker SP to output sound at a volume that corresponds to the magnitude of the power supply voltage Vdd.

As described above, the user can change the voltage value of the power supply voltage Vdd and adjust the volume of the sound output by the speaker SP by operating the operation unit provided on the variable voltage power supply 20. For example, if the user operates the operation unit to lower the power supply voltage Vdd, the volume of the sound output from the speaker SP will decrease accordingly. Conversely, if the user increases the power supply voltage Vdd, the volume of the sound output from the speaker SP will increase accordingly.

In this way, the drive circuit 60 connects the variable voltage power supply 20 to the H-bridge circuits 40A, 40B, which convert audio data into speaker drive signals, and is configured to change the magnitude of the power supply voltage Vdd applied to the source terminals of transistors FET1, FET3.By simply changing the magnitude of the power supply voltage Vdd, the volume of the audio output from the speaker SP can be adjusted without degrading the sound quality (for example, without compromising the dynamic range of the audio signal).

In the above-described configuration of the audio output circuit 100, logic level voltage conversion circuits 30A and 30B are connected between the signal input terminals that input the PWM signals (PWM0 and PWM1) and the half-bridge circuits 40A and 40B. If the audio output circuit is configured without these logic level voltage conversion circuits 30A and 30B, the following problems will arise.

As described above, the power supply voltage Vdd of the variable voltage power supply 20 is applied to the source terminal of transistor FET1. For example, if a user adjusts the power supply voltage Vdd of the variable voltage power supply 20 downward to lower the volume, the power supply voltage Vdd may become lower than the power supply voltage of the microcontroller 10 (i.e., the logic level voltage of the microcontroller that generates the PWM signal). In other words, the voltage applied to the source terminal of transistor FET1 may become lower than the power supply voltage of the microcontroller 10. In this case, if the signal input terminal of the PWM signal (PWM0) is directly connected to the gate terminal of transistor FET1 without going through the logic level voltage conversion circuit 30A (i.e., the logic level voltage of the microcontroller 10 is not converted), the gate-source voltage of transistor FET1 may become higher than the threshold voltage, causing transistor FET1 to remain in the off state and not turn on, resulting in no switching operation. Similarly, in this case, the gate-source voltage of transistor FET3 may also become higher than the threshold voltage, preventing it from turning on and no longer performing switching operation.

As such, if the audio output circuit does not include logic level voltage conversion circuits 30A and 30B, transistors FET1 and FET3 may not switch properly. If transistors FET1 and FET3 do not switch properly, the audio circuit will not be able to output a current to speaker SP in accordance with the PWM signals (PWM0 and PWM1), and will not be able to output audio in accordance with the audio data.

In contrast, the audio output circuit 100 configuration described above includes logic level voltage conversion circuits 30A and 30B, which allows transistors FET1 and FET3 to perform appropriate switching operation even when the power supply voltage Vdd is set to a low voltage or stepped down, so the above-mentioned problem does not occur.

Next, the operation of the drive circuit 60 will be described in detail. The voltage values applied to the drive circuit 60 are as follows: The power supply voltage of the microcontroller 10 is +5 volts, with ground as the reference potential. Because the power supply voltage of the microcontroller 10 is +5 volts, a voltage of 0 volts (ground) is applied to the signal input terminal of the drive circuit 60 for the PWM signals (PWM0, PWM1) when the PWM signals (PWM0, PWM1) are "L," and a voltage of +5 volts is applied when the PWM signals (PWM0, PWM1) are "H." Furthermore, the power supply voltage Vdd of the voltage-variable power supply 20 is +1 volt. Therefore, the power supply voltage Vdd (voltage value +1 volt) of the voltage-variable power supply 20 is lower than the power supply voltage (voltage value +5 volts) of the microcontroller 10.

Note that the above values for the power supply voltage of the microcontroller 10 and the power supply voltage Vdd of the voltage variable power supply 20 are merely examples, and can be set arbitrarily as long as the drive circuit 60 operates.

In general, the gate-source voltage (threshold voltage) required for an FET to turn on varies depending on its electrical characteristics and changes depending on the voltage applied to the terminals and temperature, but we will assume that the gate-source voltage (threshold voltage) Vgs required for transistors FET1 and FET3 to turn on is -2.5 volts, and the gate-source voltage (threshold voltage) Vgs required for transistors FET2 and FET4 to turn on is +2.5 volts.

First, we will explain the state of the first drive circuit 50A before the PWM signal (PWM0) is input (hereinafter referred to as the "initial state"). In the initial state, no PWM signal (PWM0) is input to the signal input terminal for the PWM signal (PWM0), so 0 volts is applied to the signal input terminal for the PWM signal (PWM0). In addition, the potential at connection point L1 on the signal input terminal side of capacitor C1 is 0 volts.

In the initial state, before the power supply voltage Vdd of the variable voltage power supply 20 is applied, the charge on capacitor C1 is 0 (C1:Q = 0). Figure 3 is a schematic diagram showing an example of a first drive circuit 50A. As shown in Figure 3, when the power supply voltage Vdd (voltage value +1 volt) is applied, the potential at connection point H1 on the power supply voltage Vdd side becomes +1 volt. This causes charge to accumulate in capacitor C1, and the voltage of capacitor C1 is charged up to -1 volt. Because the Schottky barrier diode SBD1 functions to cut off voltages that exceed the power supply voltage Vdd, the potential at connection point H1 on the power supply voltage Vdd side of capacitor C1 remains at +1 volt.

Also, in the initial state, when the power supply voltage Vdd (voltage value +1 volt) is turned on, a voltage of +1 volt is applied to the gate terminal of transistor FET1, and a voltage of +1 volt is also applied to the source terminal. At this time, the gate-source voltage of transistor FET1 is 0 volts, which is higher than the threshold voltage (-2.5 volts), so transistor FET1 is turned off.

In the initial state, a voltage of 0 volts is applied to the gate terminal of transistor FET2, and a voltage of 0 volts is applied to the source terminal, which is connected to ground. At this time, the gate-source voltage of transistor FET2 is 0 volts, which is lower than the threshold voltage (+2.5 volts), so transistor FET2 is off.

As such, in the initial state, neither transistor FET1 nor transistor FET2 is driven, so the potential at the output terminal (connection point O1) of the first drive circuit 50A is undefined.

When the input of the PWM signal (PWM0) to the first drive circuit 50A begins (after the PWM signal is input), the initial state continues while the PWM signal (PWM0) is "L" (voltage value 0 volts), but when the PWM signal (PWM0) becomes "H" (i.e., when a voltage of +5 volts is applied to the PWM signal (PWM0) input terminal), the first drive circuit 50A operates as follows:

First, the potential at connection point L1 on the PWM signal input terminal side of capacitor C1 changes from 0 volts to +5 volts. This causes the voltage of capacitor C1 to change from its initial state of -1 volt to +6 volts, but the Schottky barrier diode SBD1 turns on, causing it to eventually charge up from -1 volt to +4 volts. Once capacitor C1 is charged up to +4 volts, it maintains the post-charge potential difference (voltage value +4 volts) as long as the PWM signal (PWM0) is input. When the voltage of capacitor C1 is charged up, a forward voltage bias is generated in Schottky barrier diode SBD1, which turns on temporarily and functions to cut off voltages that exceed the power supply voltage Vdd (voltage value +1 volt). As a result, the potential at connection point H1 on the power supply voltage Vdd side of capacitor C1 becomes +1 volt.

Since the potential at connection point H1 is +1 volts, a voltage of +1 volt is applied to the gate terminal of transistor FET1. At this time, the potential of the gate terminal of transistor FET1 becomes the same as the power supply voltage Vdd. In addition, the power supply voltage Vdd (voltage value +1 volt) continues to be applied to the source terminal of transistor FET1. At this time, the gate-source voltage of transistor FET1 is 0 volts, which is higher than the threshold voltage (-2.5 volts), so transistor FET1 is turned off.

Furthermore, since the potential at node L1, which is connected to the signal input terminal for the PWM signal (PWM0), is +5 volts, a voltage of +5 volts is applied to the gate terminal of transistor FET2. Also, 0 volts (ground) continues to be applied to the source terminal of transistor FET2. At this time, the gate-source voltage of transistor FET2 changes from 0 volts to +5 volts, and a voltage higher than the threshold voltage (+2.5 volts) is applied to the gate of transistor FET2, so transistor FET2 turns on.

In this way, when the PWM signal (PWM0) input to the first drive circuit 50A is "H," transistor FET1 is off and transistor FET2 is on. At this time, a voltage of 0 volts (ground) is applied to the output terminal (connection point O1) of the first drive circuit 50A.

Next, when the PWM signal (PWM0) input to the first drive circuit 50A changes from "H" to "L" (i.e., when a voltage of 0 volts is applied to the PWM signal (PWM0) input terminal), the first drive circuit 50A operates as follows:

Since the voltage across capacitor C1 is +4 volts, the potential at connection point H1 changes from +1 volt to -4 volts. This causes a voltage of -4 volts to be applied to the gate terminal of transistor FET1.

The +1 volt power supply voltage Vdd continues to be applied to the source terminal of transistor FET1. At this time, the gate-source voltage of transistor FET1 becomes -5 volts, which is lower than the threshold voltage (-2.5 volts), so transistor FET1 turns on.

Furthermore, since the potential of node L1, which is connected to the signal input terminal of the PWM signal (PWM0), is 0 volts, a voltage of 0 volts is applied to the gate terminal of transistor FET2. Also, 0 volts (ground) continues to be applied to the source terminal of transistor FET2. At this time, the gate-source voltage of transistor FET2 is 0 volts, which is lower than the threshold voltage (+2.5 volts), so transistor FET2 is turned off.

In this way, when the PWM signal (PWM0) input to the first drive circuit 50A goes "L," transistor FET1 turns on and transistor FET2 turns off. At this time, a voltage of +1 volt is applied to the output terminal (connection point O1) of the first drive circuit 50A.

Furthermore, when the PWM signal (PWM0) input to the first drive circuit 50A changes from "L" to "H" again, the state returns to the above, and transistor FET1 turns off and transistor FET2 turns on again.

As a result of this operation of the first drive circuit 50A, a PWM signal (PWM0) is input from the PWM signal input terminal, causing FET1 and FET2 to alternately turn on and off.

The operation of the second drive circuit 50B is similar to that of the first drive circuit 50A described above. That is, returning to FIG. 2, in the initial state (before the PWM signal is input), before the power supply voltage Vdd of the variable voltage power supply 20 is applied to the second drive circuit 50B, the charge on capacitor C2 is 0 (C2:Q = 0). Then, when the power supply voltage Vdd (voltage value +1 volt) is applied, the potential at connection point H2 on the power supply voltage Vdd side becomes +1 volt. As a result, charge accumulates in capacitor C2, and the voltage on capacitor C2 is charged up to -1 volt. Because the Schottky barrier diode SBD2 functions to cut off voltages exceeding the power supply voltage Vdd, the potential at connection point H2 on the power supply voltage Vdd side of capacitor C2 remains at +1 volt.

Also, in the initial state, when the power supply voltage Vdd (voltage value +1 volt) is turned on, a voltage of +1 volt is applied to the gate terminal of transistor FET3, and a voltage of +1 volt is also applied to the source terminal. At this time, the gate-source voltage of transistor FET3 is 0 volts, which is higher than the threshold voltage (-2.5 volts), so transistor FET3 is turned off.

In the initial state, a voltage of 0 volts is applied to the gate terminal of transistor FET4, and a voltage of 0 volts is applied to the source terminal, which is connected to ground. At this time, the gate-source voltage of transistor FET4 is 0 volts, which is lower than the threshold voltage (+2.5 volts), so transistor FET4 is turned off.

As such, in the initial state, neither transistor FET3 nor transistor FET4 is driven, so the potential at the output terminal (connection point O2) of the second drive circuit 50B is undefined.

When the input of the PWM signal (PWM1) to the second drive circuit 50B begins (after the PWM signal is input), the initial state continues while the PWM signal (PWM1) is "L" (voltage value 0 volts), but when the PWM signal (PWM1) becomes "H" (i.e., when a voltage of +5 volts is applied to the PWM signal (PWM1) input terminal), the second drive circuit 50B operates as follows:

First, the potential at connection point L2 on the PWM signal input terminal side of capacitor C2 changes from 0 volts to +5 volts. This causes the voltage of capacitor C2 to change from its initial state of -1 volt to +6 volts, but the Schottky barrier diode SBD2 turns on and it eventually charges up from -1 volt to +4 volts. Once capacitor C2 is charged up to +4 volts, it maintains the post-charge potential difference (voltage value +4 volts) as long as the PWM signal (PWM1) is input. As the voltage of capacitor C2 charges up, a forward voltage bias is generated in Schottky barrier diode SBD2, which temporarily turns on and functions to cut off voltages that exceed the power supply voltage Vdd (voltage value +1 volt). As a result, the potential at connection point H2 on the power supply voltage Vdd side of capacitor C2 becomes +1 volt.

Since the potential at connection point H2 is +1 volt, a voltage of +1 volt is applied to the gate terminal of transistor FET3. At this time, the potential of the gate terminal of transistor FET3 becomes the same as the power supply voltage Vdd. In addition, the power supply voltage Vdd (voltage value +1 volt) continues to be applied to the source terminal of transistor FET3. At this time, the gate-source voltage of transistor FET3 is 0 volts, which is higher than the threshold voltage (-2.5 volts), so transistor FET3 is turned off.

Furthermore, since the potential at node L3, which is connected to the signal input terminal for the PWM signal (PWM1), is +5 volts, a voltage of +5 volts is applied to the gate terminal of transistor FET4. Also, 0 volts (ground) continues to be applied to the source terminal of transistor FET4. At this time, the gate-source voltage of transistor FET4 changes from 0 volts to +5 volts, and a voltage higher than the threshold voltage (+2.5 volts) is applied to the gate of transistor FET4, so transistor FET4 turns on.

In this way, when the PWM signal (PWM1) input to the second drive circuit 50B is "H," transistor FET3 is off and transistor FET4 is on. At this time, a voltage of 0 volts (ground) is applied to the output terminal (connection point O2) of the second drive circuit 50B.

Next, when the PWM signal (PWM1) input to the second drive circuit 50B changes from "H" to "L" (i.e., when a voltage of 0 volts is applied to the PWM signal (PWM1) input terminal), the second drive circuit 50B operates as follows:

Since the voltage across capacitor C2 is +4 volts, the potential at connection point H2 changes from +1 volt to -4 volts. This causes a voltage of -4 volts to be applied to the gate terminal of transistor FET3.

The +1 volt power supply voltage Vdd continues to be applied to the source terminal of transistor FET3. At this time, the gate-source voltage of transistor FET3 is -5 volts, which is lower than the threshold voltage (-2.5 volts), so transistor FET3 turns on.

Furthermore, since the potential of node L2, which is connected to the signal input terminal of the PWM signal (PWM1), is 0 volts, a voltage of 0 volts is applied to the gate terminal of transistor FET4. Also, 0 volts (ground) continues to be applied to the source terminal of transistor FET4. At this time, the gate-source voltage of transistor FET4 is 0 volts, which is lower than the threshold voltage (+2.5 volts), so transistor FET4 is turned off.

In this way, when the PWM signal (PWM1) input to the second drive circuit 50B goes "L," transistor FET3 turns on and transistor FET4 turns off. At this time, a voltage of +1 volt is applied to the output terminal (connection point O2) of the second drive circuit 50B.

Furthermore, when the PWM signal (PWM1) input to the second drive circuit 50B changes from "L" to "H" again, the state returns to the above, and transistor FET3 turns off and transistor FET4 turns on again.

By operating the second drive circuit 50B in this way, a PWM signal (PWM1) is input from the PWM signal input terminal, causing FET3 and FET4 to alternately turn on and off.

A voltage swing between the power supply voltage Vdd (+1 volt) and ground (0 volts) occurs at the terminals of speaker SP in synchronization with the PWM signals (PWM0, PWM1). When transistors FET1 and FET4 are both on and transistors FET2 and FET3 are both off (i.e., PWM0 is "L" and PWM1 is "H"), or when transistors FET1 and FET4 are both off and transistors FET2 and FET3 are both on (PWM0 is "H" and PWM1 is "L"), the drive circuit 60 drives speaker SP with a voltage of +1 volt (power supply voltage Vdd).

In the drive circuit 60 configuration described above, the logic level voltage conversion circuits 30A and 30B apply a voltage of the same level as the signal voltage of the PWM signals (PWM0 and PWM1) input to the PWM signal input terminal to the gate terminals of the NMOSFETs (transistors FET2 and FET4). When the PWM signals (PWM0 and PWM1) are "L," a voltage value of the voltage level obtained by subtracting the power supply voltage of the microcontroller 10 from the voltage value of the voltage Vdd of the voltage variable power supply 20 (in other words, if the power supply voltage of the microcontroller 10 is Vm, then Vdd - Vm) is applied to the gate terminals of the PMOSFETs (transistors FET1 and FET3). When the PWM signals (PWM0 and PWM1) are "H," a voltage of the same level as the voltage Vdd of the voltage variable power supply 20 is applied to the gate terminals of the PMOSFETs (transistors FET1 and FET3).

For example, as described above, when the PWM signals (PWM0, PWM1) input to the PWM signal input terminals are "L" (0 volts), the logic-level voltage conversion circuits 30A, 30B apply 0 volts to the gate terminals of transistors FET2, FET4. Furthermore, when the signal voltage of the input PWM signals (PWM0, PWM1) is "L" (0 volts), if the power supply voltage Vm of the microcontroller 10 is 5 volts and the voltage Vdd is +1 volt, the logic-level voltage conversion circuits 30A, 30B apply -4 volts (Vdd - Vm = (+1) - (+5)) to the gate terminals of transistors FET1, FET3. This allows the threshold voltage to be applied to the gate terminals, turning on transistors FET1, FET3 and enabling appropriate switching operation, even when voltage Vdd is lower than voltage Vm.

As mentioned above, the voltage Vdd of the variable voltage power supply 20 can be set arbitrarily, and may be set to the same voltage as the voltage Vm of the microcontroller 10. In this case (i.e., when the voltage Vdd = voltage Vm in the above example), when an "L" PWM signal (PWM0, PWM1) (voltage value 0 volts) is input, the logic level voltage conversion circuits 30A, 30B apply a voltage (voltage value 0 volts) equal to the signal voltage of the input PWM signal (PWM0, PWM1) to the gate terminals of the PMOSFETs (FET1, FET3), resulting in no conversion of the input voltage. In this case, as long as the voltage Vdd is of a predetermined magnitude, the PMOSFETs will not be hindered from turning on.

The operation of the drive circuit 60 described above applies when the power supply voltage Vdd of the voltage variable power supply 20 is lower than the power supply voltage of the microcontroller 10. However, the operation of the drive circuit 60 is similar when the power supply voltage Vdd of the voltage variable power supply 20 is the same as or higher than the power supply voltage of the microcontroller 10. For example, if the power supply voltage Vdd is set to +8 volts, when an "H" PWM signal (PWM0) is input to the first drive circuit 50A, +8 volts is applied to the gate of transistor FET1. At this time, the gate-source voltage of transistor FET1 becomes 0 volts, which is higher than the threshold voltage (-2.5 volts), so transistor FET1 turns off. Thereafter, capacitor C1 maintains a potential difference of -3 volts. When the PWM signal (PWM0) goes low, +3 volts (Vdd - Vm: (+8V) - (+5V)) is applied to the gate of transistor FET1, and the gate-source voltage of transistor FET1 becomes -5 volts, which is lower than the threshold voltage (-2.5 volts), so transistor FET1 turns on.

As described above, the first drive circuit 50A converts the voltage of the input PWM signal (PWM0) (i.e., the logic level voltage of the microcomputer 10) using the functions of capacitor C1 and Schottky barrier diode SBD1, which constitute the logic level voltage conversion circuit 30A, and inputs it to the gate of transistor FET1. Similarly, the second drive circuit 50B converts the voltage of the input PWM signal (PWM1) (i.e., the logic level voltage of the microcomputer 10) by level-shifting it using the functions of capacitor C2 and Schottky barrier diode SBD2, which constitute the logic level voltage conversion circuit 30B, and inputs it to the gate of transistor FET3. By including these logic level voltage conversion circuits 30A and 30B, the drive circuit 60 can appropriately switch (on and off) transistors FET1 and FET3 based on the audio signal, even when the power supply voltage Vdd is lower or higher than the power supply voltage of the microcomputer 10, and outputs a drive voltage of the same voltage value as the power supply voltage Vdd to the speaker SP.

That is, the audio output circuit 100 includes a microcomputer that generates a differential PWM signal based on audio data, a drive circuit 60 that switches the H-bridge circuit 40 in accordance with the differential PWM signal to output a drive voltage to the speaker SP, and a variable voltage power supply 20 that applies a variable voltage to the drive circuit 60, causing the drive circuit 60 to output a drive voltage corresponding to the variable voltage. The drive circuit 60 also includes a logic level voltage conversion circuit 30 that converts the voltage of the input PWM signal (PWM0, PWM1) to a different voltage level depending on the power supply of the microcomputer 10 and the voltage of the variable voltage power supply 20, and inputs the converted voltage to the gate terminals of the PMOSFETs (FET1, FET3) of the H-bridge circuit 40. The audio output circuit 100 controls the output voltage of the H-bridge circuit 40 by varying the voltage of the variable voltage power supply 20. With this configuration of the audio output circuit 100, the output volume of the speaker SP can be adjusted by changing the voltage of the variable voltage power supply 20, and high-quality audio can be output while adopting a fully digital system.

Furthermore, due to the configuration of the drive circuit 60 of the audio output circuit 100, even when the voltage Vdd of the voltage variable power supply 20 is low relative to the signal voltage of the PWM signals (PWM0, PWM1) (i.e., the power supply voltage Vm of the microcontroller 10), the transistors FET1 and FET3 turn on and off, making it possible to output audio at a low volume corresponding to the voltage Vdd.

Although an embodiment of the present invention has been described above, the technical scope of the present invention is not limited to the scope described in the above embodiment. Various modifications and improvements can be made to the above embodiment without departing from the spirit of the present invention. Furthermore, one or more of the requirements described in the above embodiment may be omitted. Such modifications, improvements, and omitted forms are also included within the technical scope of the present invention.

10 Microcomputer 20 Variable voltage power supply 30 Logic level voltage conversion circuit 40 H-bridge circuit 60 Driver circuit 100 Audio output circuit FET1, FET3 PMOSFET
FET2, FET4 NMOSFET
R11, R21, R31, R41 Resistors SBD1, SBD2 Schottky barrier diode SP Speaker

Claims (3)

a microcomputer that generates a differential PWM signal based on audio data;
a drive circuit that performs a switching operation of an H-bridge circuit in accordance with the differential PWM signal to output a drive voltage to a speaker,
a variable voltage power supply that applies a variable voltage to the drive circuit and causes the drive circuit to output the drive voltage corresponding to the variable voltage;
The drive circuit
a logic level voltage conversion circuit that converts the voltage of an input PWM signal to a voltage level different from the voltage of a power supply of the microcomputer and the voltage variable power supply, and inputs the converted voltage to a gate terminal of a PMOSFET of the H-bridge circuit;
The PMOSFET is
a source terminal connected to the variable voltage power supply and a gate terminal connected to the variable voltage power supply via a resistor;
The logic level voltage conversion circuit includes:
a Schottky barrier diode connected between a gate terminal of the PMOSFET and the voltage variable power supply;
a capacitor connected between the anode terminal of the Schottky barrier diode and a PWM signal input terminal,
An audio output circuit, characterized in that the output voltage of the H-bridge circuit is controlled by changing the voltage of the variable voltage power supply, thereby making it possible to vary the output volume of the speaker. The FETs constituting the H-bridge circuit are two of the PMOSFETs and two NMOSFETs,
the drain terminals of the two NMOSFETs are connected to the drain terminals of different PMOSFETs,
a gate terminal of the NMOSFET is connected to the PWM signal input terminal and is also connected to ground via a resistor;
2. The audio output circuit according to claim 1 , wherein a source terminal of the NMOSFET is connected to the ground. 3. The audio output circuit according to claim 2, wherein the logic level voltage conversion circuit applies a voltage of a voltage level equal to the signal voltage of the PWM signal to the gate terminal of the NMOSFET, and in a predetermined case applies a voltage of a voltage level obtained by subtracting the voltage value of the voltage variable power supply from the voltage value of the power supply voltage of the microcomputer to the gate terminal of the PMOSFET.