JP7815751B2 - display device - Google Patents

Description

This disclosure relates to a display device.

For example, the in-vehicle device described in Patent Document 1 includes a primary power supply unit that generates primary power, multiple secondary power supply units that generate secondary power from the primary power supply, and a control unit that can be activated based on a reset signal, and is configured to disable the generation of secondary power in the event of a momentary interruption in the DC power supply.

Japanese Patent Application Laid-Open No. 2017-196993

In the configuration of Patent Document 1, a logic circuit monitors the secondary power supplied from each secondary power supply unit to the control unit, thereby disabling the generation of secondary power in the event of a momentary power interruption. Therefore, if a temporary voltage drop occurs in the primary power supply, there is a risk that the primary power supply unit and multiple secondary power supply units may not be able to restart in the correct sequence.

This disclosure was made in consideration of the above-mentioned circumstances, and aims to provide a display device that can more reliably restart the main power supply and sub power supplies in the correct order when a temporary voltage drop occurs in the main power supply.

In order to achieve the above object, a display device according to the present disclosure includes a display unit that displays an image, a control unit that controls the display unit, a main power supply that outputs a first voltage and outputs a first power-good signal "on" while outputting the first voltage, a first sub-power supply that starts up when receiving the first power-good signal "on", receives the first voltage from the main power supply, outputs a second voltage to the control unit, and outputs a second power-good signal "on" while outputting the second voltage, a second sub-power supply that starts up when receiving the second power-good signal "on", receives the first voltage from the main power supply, and outputs a third voltage to the control unit, and a control unit that controls the main power supply to output a third voltage to the control unit. and an on-delay circuit that delays the startup of the first sub-power supply until the output of the third voltage from the second sub-power supply stops when the output of the second voltage from the first sub-power supply stops due to a temporary drop in the first voltage, wherein the on-delay circuit includes a storage unit that delays the startup of the first sub-power supply for an on-delay time after the first power-good signal output from the main power supply switches from off to on, and a charge discharge unit that forms a current path from the storage unit to ground when the first power-good signal switches from on to off, thereby discharging the charge accumulated in the storage unit to the ground .

According to the present disclosure, in a display device, if a temporary voltage drop occurs in the main power supply, the main power supply and secondary power supplies can be restarted more reliably in the correct order.

1 is a block diagram of a display device according to a first embodiment of the present disclosure. 4 is a timing chart showing the operation of each component of the display device according to the first embodiment of the present disclosure. 1 is a circuit diagram of a main power off delay circuit, a fixed period off circuit, and a sub power off delay circuit according to a first embodiment of the present disclosure. FIG. FIG. 10 is a block diagram of a display device according to a second embodiment of the present disclosure. FIG. 10 is a circuit diagram of an on-delay circuit according to a second embodiment of the present disclosure. 10 is a timing chart showing the states of a main power supply and each sub power supply when the power supply is turned on according to a second embodiment of the present disclosure. 10 is a timing chart showing the states of the main power supply and each sub power supply when the voltage from the main power supply according to the second embodiment of the present disclosure is momentarily interrupted. 10 is a timing chart showing the states of the main power supply and each sub power supply when the voltage from the main power supply is momentarily interrupted in a comparative example.

(First embodiment)
A first embodiment of a display device according to the present disclosure will be described with reference to the drawings. In this example, the display device is an instrument mounted on a vehicle.
As shown in FIG. 1, the display device 1 includes a power supply control circuit 10, a control unit 4, and a display unit 70.

The display unit 70 is an LCD (Liquid Crystal Display) that displays images under the control of the control unit 4. These images include various vehicle information, such as vehicle speed. The display unit 70 operates by receiving a voltage from the power supply control circuit 10 (more precisely, a fifth voltage V5 from the sub-power supply 34, described below).

The power supply control circuit 10 includes a main power supply 2, a plurality of sub-power supplies 31 to 34, a main power supply off delay circuit 5, a fixed-period off circuit 6, a plurality of sub-power supply off delay circuits 71 to 74, diodes D1 to D6 for preventing backflow, and resistors R1 to R4.
In this example, the power-off processing unit is configured by the main power-off delay circuit 5, the fixed-period off circuit 6, the plurality of sub power-off delay circuits 71 to 74, and the diodes D3 to D6.

(Main power supply 2)
The main power supply 2 receives power from an on-board battery (not shown), generates primary power, and supplies the generated primary power to each of the sub-power supplies 31 to 34. The main power supply 2 is a DC (direct current)/DC (direct current) converter. The main power supply 2 has a voltage input terminal VIN, a voltage output terminal VOUT, an enable terminal EN, and a power good terminal PG.

The voltage input terminal VIN is electrically connected to the vehicle battery (not shown). The voltage output terminal VOUT is electrically connected to each voltage input terminal VIN of the sub-power supplies 31 to 34. The enable terminal EN is electrically connected to an ignition switch (not shown) and the main power supply off delay circuit 5. A diode D1 is provided between the enable terminal EN and the ignition switch (not shown) with its cathode facing the enable terminal EN. A diode D2 is provided between the enable terminal EN and the main power supply off delay circuit 5 with its cathode facing the enable terminal EN. The power good terminal PG is electrically connected to the enable terminal EN of the sub-power supply 31 via the sub-power supply off delay circuit 71. A resistor R1, to which a constant voltage (first voltage V1) is applied, is electrically connected to the power good terminal PG.

When the ignition signal IGN input via the enable terminal EN of the main power supply 2 is on, the main power supply 2 steps down the battery voltage BAT (e.g., 12 V) applied to the voltage input terminal VIN and outputs a first voltage V1 (e.g., 5 V) from the voltage output terminal VOUT. The first voltage V1 is applied to each of the sub power supplies 31 to 34. On the other hand, when the ignition signal IGN is off, the main power supply 2 stops outputting the first voltage V1.

Furthermore, the power-good terminal PG of the main power supply 2 turns on the power-good signal Sp1 when the first voltage V1 at the voltage output terminal VOUT is within a normal range (for example, within a range of 5V ± 5V × 10%), and turns off the power-good signal Sp1 when the first voltage V1 at the voltage output terminal VOUT is outside the normal range. More specifically, the power-good terminal PG of the main power supply 2 is an open-drain terminal. The power-good terminal PG is open when the first voltage V1 is within the normal range, and is at ground potential when it is outside this range. When the power-good terminal PG is open, a voltage determined by resistor R1 is applied between the power-good terminal PG of the main power supply 2 and the enable terminal EN of the sub-power supply 31, turning on the power-good signal Sp1. When the power-good terminal PG is at ground potential, no voltage is applied to the enable terminal EN of the sub-power supply 31, and the power-good signal Sp1 is turned off.

(Sub power supplies 31 to 34)
As shown in FIG. 1, each of the sub-power supplies 31 to 34 receives a primary power supply (first voltage V1) from the main power supply 2, generates a secondary power supply (second to fifth voltages V2 to V5), and supplies the generated secondary power supplies (second to fifth voltages V2 to V5) to the control unit 4.
The secondary power supply 31 is a DC/DC converter that generates a second voltage V2 (for example, 3.1 V).
The secondary power supply 32 is a DC/DC converter that generates a third voltage V3 (for example, 1.42 V).
The secondary power supply 33 is a DC/DC converter that generates a fourth voltage V4 (for example, 1.5 V).
The secondary power supply 34 is a DC/DC converter that generates a fifth voltage V5 (for example, 3.3 V).

The second voltage V2 (e.g., 3.1 V) is an operating voltage that governs the operation of the control unit 4 itself, such as issuing operating commands to the core of the control unit 4. The third voltage V3 (e.g., 1.42 V) and the fourth voltage V4 (e.g., 1.5 V) are used to operate the core that performs internal calculations in the control unit 4. The fifth voltage V5 is used to operate the display unit 70.

Each sub-power supply 31-34 has a voltage input terminal VIN, a voltage output terminal VOUT, an enable terminal EN, and a power good terminal PG.

The enable terminal EN of the sub power supply 31 is electrically connected to the power good terminal PG of the main power supply 2 via a sub power supply off delay circuit 71. The enable terminal EN of the sub power supply 32 is electrically connected to the power good terminal PG of the sub power supply 31 via a sub power supply off delay circuit 72. The enable terminal EN of the sub power supply 33 is electrically connected to the power good terminal PG of the sub power supply 32 via a sub power supply off delay circuit 73. The enable terminal EN of the sub power supply 34 is electrically connected to the power good terminal PG of the sub power supply 33 via a sub power supply off delay circuit 74.

The voltage input terminals VIN of the sub power supplies 31 to 34 are electrically connected to the voltage output terminal VOUT of the main power supply 2. The voltage output terminals VOUT of the sub power supplies 31 to 34 are electrically connected to the voltage input terminals VI1 to VI4 of the control unit 4, respectively.
Resistors R2 to R4, to which constant voltages (second to fourth voltages V2 to V4) are applied, are connected to the power-good terminals PG of the sub-power supplies 31 to 33. Like the power-good terminal PG of the main power supply 2, the power-good terminal PG of each of the sub-power supplies 31 to 34 is an open-drain terminal, and turns on the power-good signals Sp2 to Sp4 when the voltage at the voltage output terminal VOUT is within the normal range, and turns off the power-good signals Sp2 to Sp4 when the voltage at the voltage output terminal VOUT is outside the normal range. When the power-good terminal PG is in the open state, a voltage determined by the resistors R2 to R4 provided corresponding to the power-good terminal PG is applied between the power-good terminal PG of each of the sub-power supplies 31 to 33 and the enable terminal EN of each of the sub-power supplies 32 to 34, turning on the power-good signals Sp2 to Sp4. If the power-good terminal PG is at ground potential, no voltage is applied to the enable terminals EN of the sub-power supplies 32 to 34, and the power-good signals Sp2 to Sp4 are turned off.

When the power-good signals Sp1 to Sp4 input to the enable terminal EN of each sub-power supply 31 to 34 are turned on, the sub-power supplies 31 to 34 output the second to fourth voltages V2 to V4 from their voltage output terminal VOUT, and when the power-good signals Sp1 to Sp4 input to the enable terminal EN of each sub-power supply 31 to 34 are turned off, the sub-power supplies 31 to 34 stop outputting the second to fourth voltages V2 to V4 from their voltage output terminal VOUT.

Of the sub power supplies 31-34, sub power supply 31 is closest to the main power supply 2, sub power supply 32 is farther from the main power supply 2 than sub power supply 31, sub power supply 33 is farther from the main power supply 2 than sub power supply 32, and sub power supply 34 is located farthest from the main power supply 2. The distance of sub power supplies 31-34 from the main power supply 2 does not refer to the Euclidean distance from the main power supply 2 to sub power supplies 31-34, but rather refers to the distance in terms of the connection relationship between sub power supplies 31-34, whose signal lines are connected in series to the main power supply 2. The higher the priority of sub power supplies 31-34, the closer they are to the main power supply 2. The sub power supplies 31-34 are configured to turn on in order of highest priority (in this example, sub power supply 31 → sub power supply 32 → sub power supply 33 → sub power supply 34) and turn off in order of lowest priority (in this example, sub power supply 34 → sub power supply 33 → sub power supply 32 → sub power supply 31).

(Control unit 4)
1, the control unit 4 is a microcomputer equipped with a graphics processing unit (GPU), a central processing unit (CPU), etc., and has multiple processor cores that each perform different internal calculation processes. The control unit 4 displays an image on a display unit 70. The control unit 4 includes an IGN detection input unit 41, a self-holding output unit 42, and voltage input terminals VI1 to VI4.

The IGN detection input unit 41 receives the ignition signal IGN and detects whether the input ignition signal IGN is in an on or off state. The IGN detection input unit 41 has a chattering absorption function that absorbs momentary voltage fluctuations caused by chattering of the ignition signal IGN by a physical switch.
The voltage input terminal VI1 is electrically connected to the voltage output terminal VOUT of the sub-power supply 31 and receives the second voltage V2 from the sub-power supply 31.
The voltage input terminal VI2 is electrically connected to the voltage output terminal VOUT of the sub power supply 32 and receives the third voltage V3 from the sub power supply 32.
The voltage input terminal VI3 is electrically connected to the voltage output terminal VOUT of the sub-power supply 33 and receives the fourth voltage V4 from the sub-power supply 33.
The voltage input terminal VI4 is electrically connected to the voltage output terminal VOUT of the sub-power supply 34 and receives the fifth voltage V5 from the sub-power supply 34.

The self-holding output unit 42 outputs an ON self-holding signal S1 when the control unit 4 is in the ON state, and outputs an OFF self-holding signal S1 when the control unit 4 is in the OFF state. When the ignition signal IGN switches from ON to OFF (time t8 in Figure 2), the self-holding output unit 42 waits for the control unit 4's function-off process to be completed, and then switches the self-holding signal S1 from ON to OFF (time t9 in Figure 2).

The power-on sequence of the control unit 4 is set to the following order: first voltage V1 → second voltage V2 → third voltage V3 → fourth voltage V4 → fifth voltage V5. The power-off sequence of the control unit 4 is set to the following order: fifth voltage V5 → fourth voltage V4 → third voltage V3 → second voltage V2 → first voltage V1. Adhering to these sequences increases the reliability of the operation of the control unit 4.

(Child power off delay circuits 71 to 74)
As shown in FIG. 1, child power supply off delay circuits 71 to 74 are provided corresponding to the child power supplies 31 to 34, respectively. Each child power supply off delay circuit 71 to 74 maintains the corresponding child power supply 31 to 34 in an on state capable of outputting voltage for delay times 71T to 74T (see FIG. 2) after the power-good signals Sp1 to Sp4 are turned off, and switches the corresponding child power supply 31 to 34 to an off state in which voltage output is stopped after the delay times 71T to 74T have elapsed. Each child power supply off delay circuit 71 to 74 is composed of discrete components, such as resistors, capacitors, and diodes. The delay times 71T to 74T of each child power supply off delay circuit 71 to 74 are set by setting the delay constant of each child power supply off delay circuit 71 to 74 to a predetermined constant using the discrete components. The magnitude relationship between delay times 71T to 74T is set as follows: delay time 71T of child power supply off delay circuit 71 > delay time 72T of child power supply off delay circuit 72 > delay time 73T of child power supply off delay circuit 73 > delay time 74T of child power supply off delay circuit 74. This allows the order in which the child power supplies 31 to 34 are turned off to be set in accordance with the power-off sequence described above.

An example in which the child power supply off delay circuit 71 is configured using discrete components will be described below.
As shown in FIG. 3, the child power supply off delay circuit 71 includes a diode Da, a resistor Ra, and a capacitor Ca.
The diode Da and resistor Ra are connected in parallel. The capacitor Ca is connected between ground and the enable terminal EN of the sub power supply 31. The resistance value of the resistor Ra and the capacitance value of the capacitor Ca set the delay constant of the sub power supply off delay circuit 71, and therefore the delay time 71T. The diode Da is provided so that the current (turning on the power good signal Sp1) from the power good terminal PG of the main power supply 2 to the enable terminal EN of the sub power supply 31 is not blocked by the resistor Ra.
The child power supply off delay circuits 72 to 74 may also be configured in the same manner as the child power supply off delay circuit 71. By adjusting the resistance value of the resistor Ra and the capacitance value of the capacitor Ca of each child power supply off delay circuit 71 to 74, the delay constant, and therefore the delay times 72T to 74T, are set to different values.

(Fixed-period off circuit 6)
As shown in FIG. 1, the fixed-period off circuit 6 disables the on of the power-good signals Sp1 to Sp4 from reaching the sub-power supplies 31 to 34 for a fixed period Tof1 (see FIG. 2) from when the self-holding signal S1 is turned off.
More specifically, as shown in FIGS. 1 and 3, the period-off circuit 6 includes terminals 6a and 6b.
Terminal 6a of fixed-period off circuit 6 is electrically connected to each enable terminal EN of sub power supplies 31 to 34. Terminal 6b is electrically connected to self-holding output unit 42 of control unit 4. Diodes D3 to D6 are provided between fixed-period off circuit 6 and each power-good terminal PG so that their cathodes face toward fixed-period off circuit 6.

When the self-holding signal S1 from the self-holding output unit 42 switches from OFF to ON, the fixed-period OFF circuit 6 transitions the output of terminal 6a from ground potential to a high-impedance state without delay. When the fixed-period OFF circuit 6 is in the high-impedance state, the power-good signals Sp1 to Sp4 are enabled and output to the enable terminals EN of each of the sub-power supplies 31 to 34. This keeps each of the sub-power supplies 31 to 34 ON.

When the self-holding signal S1 from the self-holding output unit 42 switches from on to off, the fixed-period off circuit 6 transitions the output of terminal 6a from a high-impedance state to ground potential. As a result, the on power-good signals Sp1 to Sp4 flow into the fixed-period off circuit 6 and do not reach the enable terminals EN of the sub-power supplies 31 to 34. Therefore, the sub-power supply off delay circuits 71 to 74 act to turn off the sub-power supplies 31 to 34 in sequence.

The off circuit 6 maintains the ground potential for a certain time Tof1 (see FIG. 2) and then transitions to a high impedance state. The certain time Tof1 is set to be longer than the time it takes for voltage output from all of the sub power supplies 31 to 34 and the main power supply 2 to stop.
The constant-period off circuit 6 may be composed of discrete components such as resistors, capacitors, diodes, and MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), or may be composed of a logic semiconductor, a semiconductor with a timer, or an oscillator to improve the accuracy of the delay time (constant time Tof1).

An example in which the fixed-period off circuit 6 is configured with discrete components will be described below.
As shown in FIG. 3, the fixed-period off circuit 6 includes a plurality of switching elements TR44, TR45, TR46, and F40, a delay circuit 61, and resistors R5 and R6.

Switching elements TR44, TR45, and TR46 are, for example, transistors. Switching element F40 is, for example, an FET. The emitter terminal or source terminal of each of switching elements TR44, TR45, TR46, and F40 is connected to ground. Resistors R5 and R6, to which a constant voltage is applied, are connected to the collector terminals of switching elements TR45 and TR46, respectively.

The collector terminal of switching element TR44 is electrically connected to terminal 6a. The base terminal of switching element TR44 is electrically connected to the collector terminal of switching element TR45 and the drain terminal of switching element F40. The base terminals of switching elements TR45 and TR46 are electrically connected to the self-holding output unit 42 of the control unit 4. The gate terminal of switching element F40 is electrically connected to the collector terminal of switching element TR46 via delay circuit 61.

The delay circuit 61 has a resistor and a capacitor (not shown), and the charge/discharge time constant is set based on the resistance value of the resistor and the capacitance value of the capacitor so that the circuit automatically returns to a high impedance state after a certain time Tof1 has elapsed.

Next, the operation of the fixed-period off circuit 6 will be described.
When the self-holding signal S1 is on, the switching elements TR45 and TR46 are turned on, and current from each constant voltage passes through the resistors R5 and R6 and flows to ground via the switching elements TR45 and TR46. This turns off the switching elements TR44 and F40. As a result, the terminal 6a of the off circuit 6 is in a high impedance state for a certain period of time. When the self-holding signal S1 switches from on to off, the switching elements TR45 and TR46 are turned off, and a voltage from the constant voltage is applied to the base terminal of the switching element TR44, turning it on. As a result, each of the power-good signals Sp1 to Sp4 flows to ground via the switching element TR44.
When a certain time Tof1 has elapsed since the self-holding signal S1 switched from on to off, the potential of the delay circuit 61 exceeds a specified value, and the switching element F40 turns on. When the switching element F40 turns on, a current flows from the constant voltage via the resistor R5 to ground via the switching element F40, and the switching element TR44 turns off. As a result, the off circuit 6 returns to a high impedance state for a certain period of time.

(Main power off delay circuit 5)
As shown in FIG. 1, even when the control unit 4 switches from on to off, the main power supply off delay circuit 5 keeps the main power supply 2 on until all of the sub power supplies 31 to 34 are turned off (voltage output stops), and then turns off the main power supply 2 after all of the sub power supplies 31 to 34 are turned off.
The main power supply off delay circuit 5 is connected between the self-holding output unit 42 and the enable terminal EN of the main power supply 2. When the self-holding signal S1 from the self-holding output unit 42 switches from off to on, the main power supply off delay circuit 5 applies a voltage to the enable terminal EN of the main power supply 2, thereby starting up the main power supply 2.

Furthermore, when the self-holding signal S1 from the self-holding output unit 42 switches from on to off, the main power supply off delay circuit 5 stops applying voltage to the enable terminal EN of the main power supply 2 after the off delay time Tof2 has elapsed from the timing at which the self-holding signal S1 is switched off (time t9 in FIG. 2 ), and turns off the main power supply 2.
The off delay time Tof2 is set to the time required for voltage output from all of the sub power supplies 31 to 34 to be stopped. The off delay time Tof2 is set to a time shorter than the fixed time Tof1. The period after the off delay time Tof2 has elapsed and within the fixed time Tof1 is used to turn off the main power supply 2. The main power supply off delay circuit 5, like the fixed-period off circuit 6, may be configured with discrete components, or may be configured using a semiconductor or an oscillator.

An example in which the main power supply off delay circuit 5 is configured using discrete components will be described below.
As shown in FIG. 3, the main power supply off delay circuit 5 includes a plurality of switching elements TR41 and TR41, a delay circuit 51, and resistors R7 and R8.

Switching element TR41 is, for example, a transistor. Switching element F41 is, for example, an FET. The emitter terminal or source terminal of each of switching elements TR41 and F41 is connected to ground. Resistors R7 and R8, to which a constant voltage is applied, are connected to the collector terminal or drain terminal of switching elements TR41 and F41.

The base terminal of switching element TR41 is electrically connected to the self-holding output unit 42 of the control unit 4. The gate terminal of switching element F41 is electrically connected to the collector terminal of switching element TR41 via the delay circuit 51. The drain terminal of switching element F41 is connected to the enable terminal EN of the main power supply 2.

Next, the operation of the main power supply off delay circuit 5 will be described.
When the self-holding signal S1 is on, the switching element TR41 is on, and a current flows from the constant voltage through the resistor R8 to the ground, turning off the switching element F41. When the switching element F41 is off, a voltage from the constant voltage through the resistor R7 is applied to the enable terminal EN of the main power supply 2, keeping the main power supply 2 on.

When the self-holding signal S1 switches from on to off, switching element TR41 turns off. After the off delay time Tof2 has elapsed, the voltage from the constant voltage via resistor R8 causes the potential of delay circuit 51 to exceed a specified value, turning switching element F41 on. When switching element F41 turns on, current from the constant voltage via resistor R7 flows to ground, stopping the voltage applied to the enable terminal EN of main power supply 2. This turns off main power supply 2.

(Power-on sequence)
Next, the power-on sequence will be described with reference to the timing chart in Figure 2. First, at time t0, the ignition signal IGN, control unit 4, self-holding output unit 42, sub power supplies 31 to 34, main power-off delay circuit 5, and main power supply 2 are all off, and the off circuit 6 is in a high impedance state for a certain period of time.

At time t1, when the ignition signal IGN turns on, voltage is applied to the enable terminal EN of the main power supply 2, starting the main power supply 2. At this time, voltage is also applied to the IGN detection input terminal 41 of the control unit 4, but the control unit 4 is in the off state and does not start up.

After the main power supply 2 starts up, at time t2, the power-good signal Sp1 is output as an ON signal from the power-good terminal PG of the main power supply 2 to the enable terminal EN of the sub-power supply 31. This starts up the sub-power supply 31. At this time, the sub-power supply off delay circuit 71 does not delay the startup of the sub-power supply 31 because current (power-good signal Sp1) flows from the power-good terminal PG of the main power supply 2 to the enable terminal EN of the sub-power supply 31 via diode Da (see Figure 3).

After the sub power supply 31 starts up, at time t3, the power-good signal Sp2 is output from the power-good terminal PG of the sub power supply 31 to the enable terminal EN of the sub power supply 32, causing the sub power supply 32 to start up. At this time, the sub power supply off delay circuit 72, like the sub power supply off delay circuit 71, does not delay the start of the sub power supply 32.

After the sub power supply 32 starts up, at time t4, the power-good signal Sp3 is output from the power-good terminal PG of the sub power supply 32 to the enable terminal EN of the sub power supply 33. This starts up the sub power supply 33. At this time, the sub power supply off delay circuit 73, like the sub power supply off delay circuit 71, does not delay the startup of the sub power supply 33.

After the sub power supply 33 starts up, at time t5, the power-good signal Sp4 is output from the power-good terminal PG of the sub power supply 33 to the enable terminal EN of the sub power supply 34. This starts up the sub power supply 34. At this time, the sub power supply off delay circuit 74, like the sub power supply off delay circuit 71, does not delay the startup of the sub power supply 34.

When all of the sub-power supplies 31-34 are activated, the control unit 4 is activated, and at approximately the same time, time t6, the control unit 4 outputs the self-holding signal S1 as ON from the self-holding output unit 42. The control unit 4 constantly detects whether the ignition signal IGN is ON or OFF via the IGN detection input unit 41.

At the same time that the self-holding signal S1 is output as ON from the self-holding output unit 42, the main power supply OFF delay circuit 5 turns ON and applies a voltage to the enable terminal EN of the main power supply 2. At this time, a voltage has already been applied to the enable terminal EN of the main power supply 2 due to the ignition signal IGN being ON, so the main power supply 2 maintains the ON state. Furthermore, the voltage from the ignition signal IGN and the voltage from the main power supply OFF delay circuit 5 are applied to the enable terminal EN of the main power supply 2, but the diodes D1 and D2 (see FIG. 1) cause the higher of the voltage from the ignition signal IGN and the voltage from the main power supply OFF delay circuit 5 to be applied to the enable terminal EN of the main power supply 2.
The fixed-period off circuit 6 maintains a high impedance state during the power-on sequence.
This completes the explanation of the power-on sequence.

(Power off sequence)
Next, the power-off sequence will be described with reference to the timing chart in Figure 2. At time t7 before the start of the power-off sequence, the ignition signal IGN, control unit 4, self-holding output unit 42, sub power supplies 31 to 34, main power-off delay circuit 5, and main power supply 2 are on, and the off circuit 6 is in a high impedance state for a certain period of time.

When the ignition signal IGN switches from ON to OFF at time t8, the control unit 4 detects a drop in the voltage of the ignition signal IGN from the IGN detection input unit 41, and determines that the ignition signal IGN is OFF through chattering absorption processing provided by software. Then, the control unit 4 performs processing to turn off the function of the control unit 4, and then turns off, and switches the self-holding signal S1 from the self-holding output unit 42 from ON to OFF.
When the self-holding signal S1 switches from on to off at time t9, the fixed-period-off circuit 6 transitions from the high impedance state to the ground potential.

The main power supply off delay circuit 5 keeps the main power supply 2 on for an off delay time Tof2 from when the ignition signal IGN is switched off.
During the off delay time Tof2, the off circuit 6 is at ground potential for a certain period of time, and the voltage at the enable terminal EN of each sub-power supply 31 to 34 is dropped in sequence in a stopping order predetermined by the charging and discharging time constants of the sub-power supply off delay circuits 71 to 74, the output of each sub-power supply 31 to 34 is stopped in sequence, and each sub-power supply 31 to 34 is turned off in sequence.
At time t10 after the off delay time Tof2 has elapsed (after voltage output from all of the sub power supplies 31 to 34 has stopped), main power supply off delay circuit 5 drops the voltage to enable terminal EN of main power supply 2 to a predetermined voltage or lower, thereby stopping the voltage output from main power supply 2 and turning off main power supply 2.
The fixed-period off circuit 6 returns from the ground potential to a high impedance state after the fixed period Tof1 has elapsed (after the voltage output of the main power supply 2 has stopped).

(effect)
According to the first embodiment described above, the following effects are achieved.
(1) The display device 1 includes a display unit 70 that displays an image, a control unit 4 that controls the display unit 70, a main power supply 2 that outputs a first voltage V1, a sub-power supply 31 that is an example of a first sub-power supply that is activated when the first voltage V1 becomes equal to or greater than a first specified value, receives the first voltage V1 from the main power supply 2, and outputs a second voltage V2 to the control unit 4, a sub-power supply 32 that is an example of a second sub-power supply that is activated when the second voltage V2 becomes equal to or greater than a second specified value, receives the first voltage V1 from the main power supply 2, and outputs a third voltage V3 to the control unit 4, and a main power supply off delay circuit 5, a fixed period off circuit 6, and a plurality of sub-power supply off delay circuits 71 to 74 that are examples of a power off processing unit that, when an ignition signal IGN, which is an example of an off command signal, is output to the control unit 4, turns off the sub-power supply 32 while keeping the main power supply 2 on, and then turns off the sub-power supply 31, and then turns off the main power supply 2 after turning off the sub-power supply 31.
According to this configuration, it is possible to more reliably turn off the main power supply 2 and the sub power supplies 31 and 32 in the correct order.

(2) The power-off processing unit includes a main power-off delay circuit 5 that turns off the main power supply 2 after a predetermined off delay time Tof2 has elapsed since the completion of the function-off processing by the control unit 4; a fixed-period off circuit 6 that, within the off delay time Tof2, disables the on state of a power-good signal Sp1, which is an example of a first operation command signal output from the main power supply 2 to the sub power supply 31, before it reaches the sub power supply 31 and disables the on state of a power-good signal Sp2, which is an example of a second operation command signal output from the sub power supply 31 to the sub power supply 32, before it reaches the sub power supply 32; a sub power-off delay circuit 71 that is an example of a first off delay circuit that turns off the sub power supply 31 after a delay time 71T, which is an example of a predetermined first delay time, has elapsed since the power-good signal Sp1 was disabled; and a sub power-off delay circuit 72 that is an example of a second off delay circuit that turns off the sub power supply 32 after a delay time 72T, which is an example of a predetermined second delay time shorter than the delay time 71T, has elapsed since the power-good signal Sp2 was disabled.
According to this configuration, it is possible to more reliably turn off the main power supply 2 and the sub power supplies 31 and 32 in the correct order.

(3) The power-off processing unit turns off the multiple sub power supplies 31 to 34, including sub power supply 31 and sub power supply 32, in order of furthest from main power supply 2.
According to this configuration, among the sub power supplies 31 to 34, the power supplies with the lowest importance are turned off first, and the important operating power supplies that are the core of the control unit 4 can be left until the end.

(4) The display device 1 includes a sub-power supply 33, an example of a third sub-power supply, that activates when the third voltage V3 is equal to or greater than a third specified value, receives the first voltage V1 from the main power supply 2, and outputs a fourth voltage V4 to the control unit 4; and a sub-power supply 34, an example of a fourth sub-power supply, that activates when the fourth voltage V4 is equal to or greater than a fourth specified value, receives the first voltage V1 from the main power supply 2, and outputs a fifth voltage to the control unit 4. The sub-power supply 31 is an operating power supply that governs the operation of the control unit 4. The sub-power supplies 32 and 33 are core power supplies for internal calculations of the control unit 4. The sub-power supply 34 is an operating power supply for the display unit 70. When an ignition signal IGN OFF is output to the control unit 4, the power-off processing unit turns off the sub-power supplies 34, 33, 32, and 31 in that order while keeping the main power supply 2 ON.

(5) Each of the sub power supplies 31 to 34 is a DC/DC converter, and the enable terminal EN and power good terminal PG of each of the sub power supplies 31 to 34 are connected in a daisy chain configuration, to which a main power off delay circuit 5, a fixed period off circuit 6, and multiple sub power off delay circuits 71 to 74 are added. This makes it possible to realize a power supply control circuit 10 that can freely set the power off sequence.
Furthermore, the main power-off delay circuit 5, the fixed-period off circuit 6, and the multiple sub power-off delay circuits 71 to 74 can be configured with inexpensive discrete components, which allows for a simpler and less expensive configuration than when the power-off processing unit is configured with a microcomputer, a power management integrated circuit (IC), a programmable logic device (PLD), or the like.

(6) The power supply control circuit 10 includes a plurality of sub-power supplies 31 to 34 connected in a daisy chain according to a preset start-up sequence using the main power supply 2 as a voltage source; a control unit 4 using the plurality of sub-power supplies 31 to 34 as voltage sources and having a self-holding output unit 42; a main power supply off delay circuit 5 connected between the self-holding output unit 42 and the main power supply 2 and delaying the turning-off of the self-holding output unit 42; a fixed-period off circuit 6 connected between the self-holding output unit 42 and the plurality of sub-power supplies 31 to 34 and maintaining the self-holding output unit 42 in an off state for a fixed period and then becoming high impedance; and sub-power supply off delay circuits 71 to 74 connected between the main power supply 2 and the plurality of sub-power supplies 31 to 34 and turning off the sub-power supplies 31 to 34 according to a preset stop sequence.
According to this configuration, power supply control circuit 10 can more reliably turn off main power supply 2 and sub power supplies 31 to 34 in the correct order.

Second Embodiment
A second embodiment of a display device according to the present disclosure will be described with reference to the drawings, focusing on differences from the first embodiment.
4, the power supply control circuit 10 includes a main power supply 2 and a plurality of sub power supplies 31 to 34 similar to those of the first embodiment, as well as an on-delay circuit 80. In this embodiment, the main power supply off-delay circuit 5, the fixed-period off circuit 6, and the plurality of sub power supply off-delay circuits 71 to 74 of the first embodiment are omitted.

In the event of a momentary interruption in the first voltage V1 from the main power supply 2, the on-delay circuit 80 delays the start-up of the sub-power supply 31 until all voltage outputs from the sub-power supplies 31 to 34 have stopped, in order to turn on (restart) the sub-power supplies 31 to 34 in the correct order.
The on-delay circuit 80 is provided between the power-good terminal PG of the main power supply 2 and the enable terminal EN of the secondary power supply 31, and receives the first voltage V1 from the main power supply 2. The on-delay circuit 80 may be configured using discrete components, or may be configured using a semiconductor or an oscillator.

An example in which the on-delay circuit 80 is configured using discrete components will be described below.
As shown in FIG. 5, the on-delay circuit 80 includes a plurality of switching elements F70 and F71, resistors R70 to R77, and capacitors C70, C71, and C72.

Resistors R70 and R73 are pull-up resistors to which a constant voltage (first voltage V1) is applied. Resistor R74 is a pull-up resistor to which a constant voltage source (e.g., 3.3 V from a battery) is applied as a constant power source.

Switching elements F70 and F71 are FETs. The source terminals of switching elements F70 and F71 are connected to ground. The drain terminal of switching element F71 is connected to one end of resistor R70 and the enable terminal EN of the sub-power supply 31. The drain terminal of switching element F70 is connected to one end of resistor R74 and the gate terminal of switching element F71. The gate terminal of switching element F70 is connected to one end of resistor R73 and the power good terminal PG of the main power supply 2.

One end of each of the resistor R71 and the capacitor C70 is connected to ground, and the other end is connected between the enable terminal EN of the sub-power supply 31 and the drain terminal of the switching element F71.
Resistors R70 and R71 and capacitor C70 form a delay circuit. The resistance value of resistor R70 and the capacitance value of capacitor C71 determine the charge/discharge time constant, and this determines the on-delay time Tc (see FIG. 6 ), which is the time from when main power supply 2 is turned on until sub power supply 31 is turned on.
The resistance value of resistor R70 determines the rate at which charge accumulates in capacitor C70.
The resistance value of resistor R71 is set so that when the constant voltage (5V) is divided by the two resistors R70 and R71, the constant voltage (5V) is stepped down to a voltage range that can be recognized as high at the enable terminal EN of the sub-power supply 31.

Resistors R76 and R77 are connected in series to the enable terminal EN of the sub power supply 31 and the drain terminal of the switching element F71. Resistor R76 is located on the drain terminal side of the switching element F71, and resistor R77 is located on the enable terminal EN side of the sub power supply 31. Resistors R76 and R77 are provided to reduce noise.
As an example, the resistance value of the resistor R70 is 51 kΩ, the resistance value of the resistor R71 is 33 kΩ, and the resistance values of the resistors R76 and R77 are smaller than the resistance values of the resistors R70 and R71, and are set to, for example, 10 Ω.

Next, the operation of the ON delay circuit 80 will be described.
As shown in FIG. 5 , when the power-good signal Sp1 switches from off to on (the power-good terminal PG enters an open state), a voltage is applied to the gate terminal of the switching element F70, turning the switching element F70 on. This causes current from the continuous supply voltage source through resistor R74 to flow to ground via the switching element F70, turning the switching element F71 off. This causes the voltage from the constant voltage through resistor R70 to charge capacitor C70, and after the on-delay time Tc has elapsed, the voltage at the enable terminal EN of the sub-power supply 31 becomes equal to or exceeds a specified value, turning the sub-power supply 31 on. After the sub-power supply 31 turns on, the sub-power supplies 32 to 34 turn on in sequence, as in the first embodiment.

On the other hand, when the power-good signal Sp1 switches from ON to OFF (the power-good terminal PG reaches ground potential), the voltage at the gate terminal of switching element F70 drops, turning switching element F70 OFF. This applies the voltage from the constant-voltage source to resistor R74 to the gate terminal of switching element F71, turning switching element F71 ON. This causes the charge stored in capacitor C70 to flow to ground via resistor R76 and switching element F71. The voltage at the enable terminal EN of the sub-power supply 31 then falls below the specified value, turning off the sub-power supply 31. In this way, the charge stored in capacitor C70 is released as current to ground via switching element F71, preventing this current from passing through resistor R71, which has a resistance greater than that of resistor R76. This prevents the charge remaining in capacitor C70 from interfering with the normal operation of the ON delay circuit 80.

(Power-on sequence)
Next, the power-on sequence will be described with reference to the timing chart of FIG.
At time ta, when ignition signal IGN turns on, main power supply 2 starts up and power-good signal Sp1 from main power supply 2 switches from off to on. On-delay circuit 80 delays the timing (time tb) at which subsidiary power supply 31 starts up by an on-delay time Tc from time ta. Thereafter, subsidiary power supplies 32 to 34 are turned on in sequence, as in the first embodiment.

(Operation during power outage)
8, the operation of the main power supply 2 and the sub power supplies 31 to 34 when the first voltage V1 momentarily breaks will be described in a comparative example. This comparative example has a configuration in which the on-delay circuit 80 is omitted from the power supply control circuit 10 of the present embodiment.
As shown in range H1 in Figure 8, if the first voltage V1 is momentarily interrupted for the interruption time T1 while the main power supply 2 and the sub power supplies 31 to 34 are in the ON state, the power-good signal Sp1 from the main power supply 2 is turned OFF only during the interruption time T1. As a result, the enable terminal EN and voltage output terminal VOUT of the sub power supply 31 and the enable terminal EN and voltage output terminal VOUT of the sub power supply 32 are momentarily interrupted (temporarily turned OFF) in that order, but the sub power supplies 33 and 34 remain ON. Therefore, the power-on sequence is not observed, which can cause the control unit 4 to malfunction.

In this regard, in this embodiment, as shown in FIG. 7, when the first voltage V1 is momentarily interrupted for the interruption time T1, the on delay circuit 80 keeps the enable terminal EN and voltage output terminal VOUT of the sub power supply 31 off for the on delay time Tc. During this on delay time Tc, the sub power supplies 31 to 34 are sequentially turned off (see range H2 in FIG. 7). Then, after the on delay time Tc has elapsed, the sub power supplies 31 to 34 are sequentially turned on (see range H3 in FIG. 7). As a result, the power on sequence is maintained even during a momentary interruption of the first voltage V1, and malfunction of the control unit 4 can be suppressed.

(effect)
According to the second embodiment described above, the following effects are achieved.
(1) The display device 1 includes a display unit 70 that displays an image, a control unit 4 that controls the display unit 70, a main power supply 2 that outputs a first voltage V1 and, when the first voltage V1 is being output, outputs an on-state power-good signal Sp1 (first power-good signal), a sub power supply 31 that is an example of a first sub power supply that is started up when it receives the on-state power-good signal Sp1, receives the first voltage V1 from the main power supply 2, outputs a second voltage V2 to the control unit 4, and outputs an on-state power-good signal Sp2 (second power-good signal), when it is outputting the second voltage V2, a sub power supply 32 that is an example of a second sub power supply that is started up when it receives the on-state power-good signal Sp2, receives the first voltage V1 from the main power supply 2, and outputs a third voltage V3 to the control unit 4, and an on-delay circuit 80 that, when the output of the second voltage V2 from the sub power supply 31 is stopped due to a temporary drop in the first voltage V1 from the main power supply 2, delays the start of the sub power supply 31 until the output of the third voltage V3 from the sub power supply 32 is stopped.
With this configuration, even if a temporary voltage drop occurs in first voltage V1 from main power supply 2, on delay circuit 80 delays the start of sub power supply 31 for on delay time Tc until the output of other sub power supplies 32 has stopped. This makes it possible to more reliably restart main power supply 2 and sub power supplies 31, 32 in the correct order.

(2) The on-delay circuit 80 includes a capacitor C70, which is an example of a power storage unit that delays the startup of the sub-power supply 31 for an on-delay time Tc after the power-good signal Sp1 output from the main power supply 2 switches from off to on, and a switching element F71, which is an example of a charge discharge unit that discharges the charge accumulated in the capacitor C70 to ground by forming a current path from the capacitor C70 to ground when the power-good signal Sp1 switches from on to off.
According to this configuration, when the power-good signal Sp1 switches from on to off, the charge accumulated in the capacitor C70 is quickly released to the ground by the switching element F71.
For example, in a configuration without a charge discharge section, when the power supply to the display device 1 is momentarily turned off, the power is turned back on before the charge accumulated in the capacitor C70 has been completely discharged, which causes a malfunction of the on-delay circuit 80. In this regard, in the above configuration, when the power supply to the display device 1 is momentarily turned off, the charge accumulated in the capacitor C70 can be quickly discharged, allowing the on-delay circuit 80 to function normally when the power supply is turned back on.

(3) Sub power supply 32 outputs an ON power-good signal Sp3 (third power-good signal) when outputting third voltage V3. Display device 1 includes sub power supply 33, an example of a third sub power supply, that starts up when it receives the ON power-good signal Sp3, receives first voltage V1 from main power supply 2 to output fourth voltage V4 to control unit 4, and outputs an ON power-good signal Sp4 (fourth power-good signal) when outputting fourth voltage V4, and sub power supply 34, an example of a fourth sub power supply, that starts up when it receives the ON power-good signal Sp4, receives first voltage V1 from main power supply 2, and outputs fifth voltage V5 to control unit 4. When output of second voltage V2 from sub power supply 31 is stopped due to a temporary drop in first voltage V1 from main power supply 2, ON delay circuit 80 delays startup of sub power supply 31 until all voltage outputs from sub power supplies 32, 33, and the fourth sub power supply have stopped.
According to this configuration, even if a temporary voltage drop occurs in the first voltage V1 from the main power supply 2, the main power supply 2 and the sub power supplies 31 to 34 can be restarted more reliably in the correct order.

Note that this disclosure is not limited to the above-described embodiments and drawings. Modifications (including the deletion of components) may be made as appropriate within the scope of the gist of this disclosure. An example of a modification is described below.

(Modification)
In each of the above embodiments, the number, uses, and voltage values of the sub power supplies 31 to 34 can be changed as appropriate. For example, any one or two of the sub power supplies 31 to 34 may be omitted.
Furthermore, the order in which the sub power supplies 31 to 34 are turned on or off can also be changed as appropriate. For example, in each of the above embodiments, the sub power supplies 31 to 34 are turned off in order of furthest from the main power supply 2, but the order is not limited to this.

The first and second embodiments may be combined. For example, as shown in FIG. 1, in the configuration of the first embodiment, the on-delay circuit 80 of the second embodiment may be provided in series with the off-circuit 6 for a fixed period.

The switching element F71 in the second embodiment can be omitted.

In the above embodiments, the display device 1 was an instrument, but it may also be a head-up display device.

1 Display device 10 Power supply control circuit 2 Main power supply 4 Control unit 5 Main power off delay circuit 6 Fixed period off circuit 6a, 6b Terminals 31 to 34 Sub power supply 41 IGN detection input unit 42 Self-holding output unit 51, 61 Delay circuit 70 Display unit 71 to 74 Sub power off delay circuit 71T to 74T Delay time 80 On delay circuit D1 to D6, Da Diode F40, F41, F70, F71, TR41, TR44 to TR46 Switching element C70, C71, C72, Ca Capacitor R1 to R8, R70 to R77, Ra Resistor S1 Self-holding signal Sp1 to Sp4 Power good signal T1 Instantaneous interruption time V1 First voltage V2 Second voltage V3 Third voltage V4 Fourth voltage V5 Fifth voltage EN Enable terminal BAT Battery voltage VI1 to VI4 Voltage input terminal VOUT Voltage output terminal t0 to t10, ta, tb Time IGN Ignition signal Tc On delay time Tof1 Fixed time Tof2 Off delay time PG Power good terminal

Claims (2)

a display unit for displaying an image;
a control unit that controls the display unit;
a main power supply that outputs a first voltage and outputs a first power-good signal in an ON state while outputting the first voltage;
a first sub-power supply that is activated when receiving the first power-good signal, receives the first voltage from the main power supply, outputs a second voltage to the control unit, and outputs a second power-good signal when outputting the second voltage;
a second sub-power supply that is activated when the second power-good signal is turned on, receives the first voltage from the main power supply, and outputs a third voltage to the control unit;
an on-delay circuit that delays activation of the first sub-power supply until output of the third voltage from the second sub-power supply is stopped when output of the second voltage from the first sub-power supply is stopped due to a temporary drop in the first voltage from the main power supply ,
The on-delay circuit includes:
a power storage unit that delays activation of the first sub power supply for an on delay time after the first power-good signal output from the main power supply switches from off to on;
a charge discharging unit that forms a current path from the power storage unit to ground when the first power-good signal is switched from on to off, thereby discharging the charge stored in the power storage unit to the ground.
Display device. the second sub-power supply outputs a third power-good signal in an ON state when outputting the third voltage;
The display device includes:
a third sub-power supply that is activated when receiving the third power-good signal, receives the first voltage from the main power supply, outputs a fourth voltage to the control unit, and outputs a fourth power-good signal when outputting the fourth voltage;
a fourth sub-power supply that is activated when the fourth power-good signal is turned on, receives the first voltage from the main power supply, and outputs a fifth voltage to the control unit,
when the output of the second voltage from the first sub-power supply is stopped due to a temporary drop in the first voltage from the main power supply, the on-delay circuit delays the start-up of the first sub-power supply until all voltage outputs from the second sub-power supply, the third sub-power supply, and the fourth sub-power supply are stopped;
The display device according to claim 1 .