JP7815876B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

One known semiconductor device using nitride semiconductors is the high electron mobility transistor (HEMT), which has a gate electrode located in a recess formed in the barrier layer to reduce parasitic resistance and current collapse. Furthermore, a method is known in which the recess is formed by photoelectrochemical (PEC) etching rather than dry etching to reduce etching damage.

JP 2010-135640 A Japanese Patent Application Laid-Open No. 2020-136476

K. Miwa, Appl. Phys. Express 13 (2020)

When forming a recess by PEC etching, the two-dimensional electron gas (2DEG) in the channel layer below the recess decreases as the PEC etching progresses. When the 2DEG is depleted, the PEC etching stops. As a result, it is not possible to adjust the thickness of the barrier layer remaining below the recess, and the transistor's threshold voltage cannot be adjusted. For example, with conventional methods, the transistor inevitably operates in a normally-off mode.

The present disclosure aims to provide a semiconductor device and a method for manufacturing a semiconductor device that makes it easy to adjust the threshold voltage of a transistor.

a gate electrode in contact with the semiconductor layer through the opening; a first channel layer; a first barrier layer provided on the first channel layer and having a first band gap; a second channel layer provided on the first barrier layer; and a second barrier layer provided on the second channel layer and having a second band gap smaller than the first band gap; a first recess formed in the second barrier layer; and a gate electrode in contact with the semiconductor layer through the opening . When no voltage is applied to the gate electrode, a two-dimensional electron gas exists in the first channel layer on the substrate side of the bottom surface of the first recess, while a binary electron gas does not exist in the second channel layer .

This disclosure makes it easier to adjust the threshold voltage of a transistor.

FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view (part 1) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view (part 3) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view (part 4) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view (part 5) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view (part 6) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a diagram (part 1) showing the band structures of the channel layer and the barrier layer. FIG. 9 is a diagram (part 2) showing the band structures of the channel layer and the barrier layer. FIG. 10 is a cross-sectional view showing a semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view (part 2) showing the method for manufacturing a semiconductor device according to the second embodiment. FIG. 13 is a cross-sectional view showing a semiconductor device according to the third embodiment. FIG. 14 is a cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 15 is a cross-sectional view (part 2) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 16 is a cross-sectional view (part 3) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 17 is a cross-sectional view (part 4) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 18 is a cross-sectional view showing a semiconductor device according to the fourth embodiment.

Description of the embodiments of the present disclosure
First, embodiments of the present disclosure will be listed and described.

[1] A semiconductor device according to one aspect of the present disclosure includes a substrate, a semiconductor layer provided on the substrate, a source electrode and a drain electrode in ohmic contact with the semiconductor layer, an insulating film covering a portion of the semiconductor layer between the source electrode and the drain electrode and having an opening formed therein, and a gate electrode in contact with the semiconductor layer through the opening, wherein the semiconductor layer includes a first channel layer, a first barrier layer provided on the first channel layer and having a first band gap, a second channel layer provided on the first barrier layer, and a second barrier layer provided on the second channel layer and having a second band gap smaller than the first band gap, a first recess formed in the second barrier layer, and the gate electrode contacts the bottom surface of the first recess through the opening.

The second band gap of the second barrier layer is smaller than the first band gap of the first barrier layer. Therefore, when forming the first recess by photoelectrochemical etching, the first recess can be formed without changing the thickness of the first barrier layer by irradiating the second barrier layer with light having energy smaller than the first band gap but greater than the second band gap. Because the thickness of the first barrier layer does not change due to photoelectrochemical etching, adjusting the thickness of the first barrier layer makes it easier to adjust the threshold voltage of the transistor.

[2] In [1], the first barrier layer may be a first nitride semiconductor layer containing Al at a first concentration, and the second barrier layer may be a second nitride semiconductor layer containing Al at a second concentration lower than the first concentration. In this case, the second band gap of the second barrier layer is easily made smaller than the first band gap of the first barrier layer.

[3] In [1] or [2], when no voltage is applied to the gate electrode, two-dimensional electron gas may be present in the first channel layer on the substrate side of the bottom surface of the first recess, and binary electron gas may not be present in the second channel layer. In this case, normally-on operation can be achieved.

[4] In [1] to [3], the lower end of the inner wall surface of the opening may be continuous with the upper end of the inner wall surface of the first recess. In this case, parasitic resistance and current collapse are easily suppressed.

[5] In [1] to [3], the inner wall surface of the opening may be located inside the inner wall surface of the first recess. In this case, it is easy to reduce parasitic capacitance around the gate electrode.

[6] In any of [1] to [5], a second recess is formed in the semiconductor layer on the substrate side of the source electrode, and a third recess is formed on the substrate side of the drain electrode, the second recess and the third recess reaching the first channel layer, the semiconductor layer having a source region formed in the second recess and having a lower electrical resistance than the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer, and a drain region formed in the third recess and having a lower electrical resistance than the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer, the source electrode may be in contact with the source region, and the drain electrode may be in contact with the drain region. In this case, it is easy to reduce the electrical resistance between the source electrode and the drain electrode.

[7] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes the steps of: forming a semiconductor layer on a substrate; forming a source electrode and a drain electrode in ohmic contact with the semiconductor layer; forming an insulating film covering a portion of the semiconductor layer between the source electrode and the drain electrode; forming an opening in the insulating film; and forming a gate electrode in contact with the semiconductor layer through the opening. The step of forming the semiconductor layer includes the steps of: forming a first channel layer; forming a first barrier layer having a first band gap on the first channel layer; forming a second channel layer on the first barrier layer; forming a second barrier layer having a second band gap smaller than the first band gap on the second channel layer; and forming a first recess in the second barrier layer by photoelectrochemical etching while irradiating the semiconductor layer with light having energy smaller than the first band gap and greater than the second band gap. The gate electrode is formed so as to contact the bottom surface of the first recess through the opening.

During photoelectrochemical etching, the second barrier layer is irradiated with light having energy smaller than the first bandgap and larger than the second bandgap, so the first recess can be formed without changing the thickness of the first barrier layer. Because the thickness of the first barrier layer does not change during photoelectrochemical etching, adjusting the thickness of the first barrier layer makes it easier to adjust the threshold voltage of the transistor.

[Details of the embodiment of the present disclosure]
Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description.

(First embodiment)
The first embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT) whose main constituent material is a nitride semiconductor. Fig. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

As shown in FIG. 1, the semiconductor device 100 according to the first embodiment includes a substrate 10 and a stacked structure 20 of multiple semiconductor layers disposed on the substrate 10. For example, the substrate 10 is a SiC substrate with a (0001) plane on its upper surface, and the stacking direction of the stacked structure 20 is the [0001] direction. The stacked structure 20 includes, formed in this order from the substrate 10 side, a first channel layer 21, a first barrier layer 22, a second channel layer 23, and a second barrier layer 24. The stacked structure 20 is an example of a semiconductor layer. The stacked structure 20 may include a buffer layer disposed between the substrate 10 and the first channel layer 21, and may include a cap layer disposed on the second barrier layer 24.

The first channel layer 21 is, for example, an undoped GaN layer having a thickness of 10 nm or more and 500 nm or less. The first barrier layer 22 is, for example, an n-type Al _x Ga _1-x N layer having a thickness of 5 nm or more and 30 nm or less. The second channel layer 23 is, for example, an undoped GaN layer having a thickness of 5 nm or more and 10 nm or less. The second barrier layer 24 is, for example, an n-type Al _y Ga _1-y N layer having a thickness of 5 nm or more and 30 nm or less. A portion of the first channel layer 21 may be a buffer layer. The first barrier layer 22 has a first band gap Eg1, and the second barrier layer 24 has a second band gap Eg2. The value of y is smaller than the value of x. The second band gap Eg2 is smaller than the first band gap by Eg1. For example, the value of x is 0.32, and the value of y is 0.28. In this case, the first band gap Eg1 is 4.05 eV, and the second band gap Eg2 is 3.97 eV. The n-type impurities contained in the first barrier layer 22 and the second barrier layer 24 are, for example, Si or Ge. The first band gap Eg1 and the second band gap Eg2 are larger than the band gap of the first channel layer 21 and the band gap of the second channel layer 23. The n-type Al _x Ga _1-x N layer is an example of a first nitride semiconductor layer, and the n-type Al _y Ga _1-y N layer is an example of a second nitride semiconductor layer.

The semiconductor device 100 has a source electrode 31 and a drain electrode 32 provided on a stacked structure 20. The source electrode 31 and the drain electrode 32 include, for example, a Ta film and an Al film thereon. The semiconductor device 100 has an insulating film 60 that covers the portion of the stacked structure 20 between the source electrode 31 and the drain electrode 32. The insulating film 60 is formed on the stacked structure 20. A source opening 61 and a drain opening 62 are formed in the insulating film 60. The source electrode 31 is provided inside the source opening 61, and the drain electrode 32 is provided inside the drain opening 62. The insulating film 60 is, for example, a silicon nitride film. A gate opening 50 is formed in the insulating film 60 between the source electrode 31 and the drain electrode 32. The opening 50 has an inner wall surface 52.

A recess 40 is formed in the second barrier layer 24. The recess 40 has a bottom surface 41 and an inner wall surface 42. The lower end of the inner wall surface 52 of the opening 50 is continuous with the upper end of the inner wall surface 42 of the recess 40. The bottom surface 41 is located above (away from) the interface between the second channel layer 23 and the second barrier layer 24. The recess 40 is an example of a first recess.

The semiconductor device 100 has a gate electrode 33 that contacts the stacked structure 20 through the opening 50. The gate electrode 33 is also provided within the recess 40, and contacts the bottom surface 41 and inner wall surface 42 of the recess 40. The gate electrode 33 includes, for example, a Ni film and an Au film thereon. The gate electrode 33 has, for example, a T-shape in cross section, and includes a portion above the insulating film 60.

In the semiconductor device 100, 2DEG 71 exists near the top surface of the first channel layer 21. Also, 2DEG 72 exists near the top surface of the second channel layer 23. However, on the substrate 10 side of the bottom surface 41 of the recess 40, when no voltage is applied to the gate electrode 33, 2DEG 71 exists in the first channel layer 21, but 2DEG 72 does not exist in the second channel layer 23.

Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 2 to 7 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.

First, as shown in FIG. 2, a layered structure 20 including a first channel layer 21, a first barrier layer 22, a second channel layer 23, and a second barrier layer 24 is formed on a substrate 10. The layered structure 20 is formed, for example, by metal organic chemical vapor deposition (MOCVD).

Next, as shown in Figure 3, an insulating film 60 is formed on the layered structure 20.

Next, as shown in FIG. 4, an opening 61 for the source and an opening 62 for the drain are formed in the insulating film 60. To form the openings 61 and 62, reactive ion etching (RIE) is performed using, for example, an electron beam resist (not shown) as a mask. A reactive gas containing fluorine (F) is used to etch the insulating film 60. After the openings 61 and 62 are formed, the mask is removed.

Next, the source electrode 31 is formed inside the opening 61, and the drain electrode 32 is formed inside the opening 62. The source electrode 31 and the drain electrode 32 can be formed, for example, by vapor deposition, lift-off, and alloying heat treatment. The source electrode 31 and the drain electrode 32 include, for example, a Ta film and an Al film thereon. The source electrode 31 and the drain electrode 32 each make ohmic contact with the stacked structure 20.

Next, as shown in FIG. 5, an opening 50 for a gate is formed in the insulating film 60. To form the opening 50, for example, RIE is performed using an electron beam resist (not shown) as a mask. A reactive gas containing F is used to etch the insulating film 60. After the opening 50 is formed, the mask is removed.

Next, as shown in FIG. 6 , using the insulating film 60 with the opening 50 formed therein as a mask, a recess 40 is formed in the second barrier layer 24 by PEC etching. In the PEC etching, for example, a solution obtained by mixing an aqueous solution of potassium hydroxide (KOH) and an aqueous solution of potassium peroxodisulfate (K ₂ S ₂ O ₈ ) is used as an etching solution. This solution contains hydroxide ions (OH ⁻ ) and peroxodisulfate ions (S ₂ O ₈ ²⁻ ). Furthermore, the stacked structure 20 is irradiated with light, such as ultraviolet light, having energy smaller than the first band gap Eg1 of the first barrier layer 22 and larger than the second band gap Eg2 of the second barrier layer 24. For example, when the first band gap Eg1 is 4.05 eV and the second band gap Eg2 is 3.97 eV, extreme ultraviolet light with a wavelength of 310 nm is irradiated. The energy E _UV of extreme ultraviolet light with a wavelength of 310 nm is 4.01 eV.

Here, the progress of PEC etching in this embodiment will be described. Figures 8 to 9 are diagrams showing the band structures of the first channel layer 21, the first barrier layer 22, the second channel layer 23, and the second barrier layer 24. Figures 8 to 9 show the band structures along the dashed line A in Figure 6. E and _F in Figures 8 to 9 indicate the Fermi levels.

Immediately after the start of PEC etching, as shown in FIG. 8 , on the substrate 10 side of the gate opening 50, a 2DEG 71 exists in the first channel layer 21, and a 2DEG 72 exists in the second channel layer 23. When ultraviolet light 65 is incident on the second barrier layer 24, the second band gap Eg2 is smaller than the energy E _UV of the ultraviolet light 65, so the second barrier layer 24 absorbs the ultraviolet light 65, generating electron-hole pairs in the second barrier layer 24 and decomposing the second barrier layer 24. At this time, the holes are consumed at the surface of the second barrier layer 24. Electrons flow into the 2DEG 72, then reach the source electrode 31 or the drain electrode 32, and are consumed at the surface of the source electrode 31 or the drain electrode 32.

Then, as the PEC etching progresses, the recess 40 deepens. As the recess 40 deepens, the portion of the second barrier layer 24 closer to the substrate 10 than the bottom surface 41 of the recess 40 becomes thinner, and the 2DEG 72 decreases on the substrate 10 side of the bottom surface 41 of the recess 40. When the thickness of this portion reaches a certain thickness, the 2DEG 72 in the second channel layer 23 on the substrate 10 side of the bottom surface 41 of the recess 40 is depleted.

Although the ultraviolet light 65 is also incident on the first barrier layer 22, the first band gap Eg1 is larger than the energy E _UV of the ultraviolet light 65, so the first barrier layer 22 does not absorb the ultraviolet light 65, and no electron-hole pairs are generated in the first barrier layer 22. Therefore, as shown in FIG. 9 , even if electron-hole pairs are generated in the second barrier layer 24, the electrons cannot move to the 2DEG 71. For this reason, when the 2DEG 72 in the second channel layer 23 is depleted, the PEC etching stops. Therefore, when the recess 40 is formed by PEC etching, the second channel layer 23, the first barrier layer 22, and the first channel layer 21 are not etched, and the thickness of the first barrier layer 22 does not change.

In this way, the recess 40 can be formed by PEC etching. As the recess 40 is formed, the 2DEG 71 disappears from the second channel layer 23 on the substrate 10 side of the bottom surface 41 of the recess 40.

After forming the recess 40, as shown in FIG. 7, a gate electrode 33 is formed in contact with the stacked structure 20 through the opening 50. The gate electrode 33 contacts the bottom surface 41 and inner wall surface 42 of the recess 40. The gate electrode 33 may be formed to include a portion above the insulating film 60. The gate electrode 33 can be formed by, for example, vapor deposition and lift-off. The gate electrode 33 includes, for example, a Ni film and an Au film thereon.

After that, wiring and other elements are formed as needed. In this way, the semiconductor device 100 according to the first embodiment can be manufactured.

In the first embodiment, the second bandgap Eg2 of the second barrier layer 24 is smaller than the first bandgap Eg1 of the first barrier layer 22. Therefore, during PEC etching, the second barrier layer 24 is irradiated with ultraviolet light 65 having an energy E _UV smaller than the first bandgap Eg1 but larger than the second bandgap Eg2, thereby forming the recess 40 without changing the thickness of the first barrier layer 22. Forming the recess 40 by PEC etching can suppress damage to the stacked structure 20 that would occur if dry etching were performed. Furthermore, because the thickness of the first barrier layer 22 does not change due to PEC etching, adjusting the thickness of the first barrier layer 22 makes it easier to adjust the threshold voltage of the HEMT. For example, it is also possible to configure a normally-on HEMT.

Furthermore, when no voltage is applied to the gate electrode 33, 2DEG 71 exists in the first channel layer 21 on the substrate 10 side of the bottom surface 41 of the recess 40, but 2DEG 72 does not exist in the second channel layer 23. This allows for normally-on operation.

In addition, the lower end of the inner wall surface 52 of the opening 50 is continuous with the upper end of the inner wall surface 42 of the recess 40. This makes it easier to separate the interface between the stacked structure 20 and the insulating film 60 from the 2DEGs 71 and 72, making it easier to suppress parasitic resistance and current collapse.

Second Embodiment
Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the stacked structure 20. Fig. 10 is a cross-sectional view showing a semiconductor device according to the second embodiment.

In the semiconductor device 200 according to the second embodiment, as shown in FIG. 10 , a recess 81 for the source and a recess 82 for the drain are formed in the stacked structure 20. The recesses 81 and 82 reach the first channel layer 21. The bottom surfaces of the recesses 81 and 82 are located closer to the substrate 10 than the top surface of the first channel layer 21. The bottom surfaces of the recesses 81 and 82 are located deeper toward the substrate 10 than the top surface of the first channel layer 21. The recess 81 is an example of a second recess, and the recess 82 is an example of a third recess.

The stacked structure 20 includes a first channel layer 21, a first barrier layer 22, a second channel layer 23, and a second barrier layer 24, as well as a source region 25 provided in a recess 81 and a drain region 26 provided in a recess 82. The electrical resistance of each of the source region 25 and the drain region 26 is lower than the electrical resistance of the first channel layer 21, the first barrier layer 22, the second channel layer 23, and the second barrier layer 24. The source region 25 and the drain region 26 are, for example, n-type GaN layers.

The source electrode 31 is provided on and in contact with the source region 25. The drain electrode 32 is provided on and in contact with the drain region 26.

Other configurations are the same as in the first embodiment.

Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Figures 11 and 12 are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment.

First, similarly to the first embodiment, the first channel layer 21, first barrier layer 22, second channel layer 23, and second barrier layer 24 are formed (see FIG. 2). Next, as shown in FIG. 11, a source recess 81 and a drain recess 82 are formed in the first channel layer 21, first barrier layer 22, second channel layer 23, and second barrier layer 24. To form the recesses 81 and 82, for example, RIE is performed using an electron beam resist (not shown) as a mask. A reactive gas containing chlorine (Cl) is used to etch the first channel layer 21, first barrier layer 22, second channel layer 23, and second barrier layer 24. After the recesses 81 and 82 are formed, the mask is removed.

Next, as shown in FIG. 12, a source region 25 is formed in the recess 81, and a drain region 26 is formed in the recess 82. For example, an n-type GaN layer is formed as the source region 25 and the drain region 26. The n-type GaN layer can be formed by, for example, sputtering, MOCVD, or molecular beam epitaxy (MBE). In this way, the stacked structure 20 is formed.

After the layered structure 20 is formed, the processes following the formation of the insulating film 60 (see Figure 3) are carried out in the same manner as in the first embodiment.

In this manner, the semiconductor device 200 according to the second embodiment can be manufactured.

The second embodiment also achieves the same effects as the first embodiment. Furthermore, in the second embodiment, the stacked structure 20 has a source region 25 and a drain region 26. Therefore, the electrical resistance between the source electrode 31 and the 2DEG 71 and the electrical resistance between the drain electrode 32 and the 2DEG 71 can be reduced compared to the first embodiment. Furthermore, the electrical resistance between the source electrode 31 and the 2DEG 72 and the electrical resistance between the drain electrode 32 and the 2DEG 72 can also be reduced compared to the first embodiment. In other words, the electrical resistance between the source electrode 31 and the drain electrode 32 can be reduced.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the recess 40 in the second barrier layer 24. Fig. 13 is a cross-sectional view showing a semiconductor device according to the third embodiment.

In the semiconductor device 300 according to the third embodiment, as shown in FIG. 13, the recess 40 is formed wider than in the first embodiment. The insulating film 60 is also formed on the bottom surface 41 of the recess 40. The opening 50 is formed inside the recess 40. Therefore, the inner wall surface 42 of the recess 40 is located outside the inner wall surface 52 of the opening 50. In other words, the inner wall surface 52 of the opening 50 is located inside the inner wall surface 42 of the recess 40.

The gate electrode 33 contacts the stacked structure 20 through the opening 50. The gate electrode 33 contacts the bottom surface 41 of the recess 40, but unlike the first embodiment, it does not contact the inner wall surface 42 of the recess 40. The gate electrode 33 has, for example, a T-shape in cross section, and includes a portion on the insulating film 60.

Other configurations are the same as in the first embodiment.

Next, a method for manufacturing a semiconductor device 300 according to the third embodiment will be described. Figures 14 to 17 are cross-sectional views showing the method for manufacturing a semiconductor device according to the third embodiment.

First, similar to the first embodiment, the laminated structure 20 is formed (see FIG. 2). Next, as shown in FIG. 14, the source electrode 31 and the drain electrode 32 are formed on the laminated structure 20.

Next, as shown in FIG. 15 , a mask (not shown) having an opening corresponding to the recess 40 to be formed is used to form the recess 40 in the second barrier layer 24 by PEC etching. The mask is, for example, a photoresist mask. After the recess 40 is formed, the mask is removed. As the recess 40 is formed, the 2DEG 71 disappears from the second channel layer 23 on the substrate 10 side of the bottom surface 41 of the recess 40.

Next, as shown in FIG. 16, an insulating film 60 is formed on the stacked structure 20. An opening 50 for a gate is also formed in the insulating film 60. The insulating film 60 may be formed to cover the source electrode 31 and the drain electrode 32.

Next, as shown in FIG. 17, the gate electrode 33 is formed. The gate electrode 33 contacts the bottom surface 41 of the recess 40. The gate electrode 33 may be formed so as to include the upper portion of the insulating film 60.

After that, wiring and other elements are formed as needed. In this way, the semiconductor device 300 according to the third embodiment can be manufactured.

The third embodiment also achieves the same effects as the first embodiment. Furthermore, in the third embodiment, the inner wall surface 52 of the opening 50 is located inside the inner wall surface 42 of the recess 40, and the gate electrode 33 does not contact the inner wall surface 42 of the recess 40. This makes it easier to reduce the parasitic capacitance around the gate electrode 33.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment differs from the third embodiment mainly in the configuration of the stacked structure 20. Fig. 18 is a cross-sectional view showing a semiconductor device according to the fourth embodiment.

In the semiconductor device 400 according to the fourth embodiment, as shown in FIG. 18 , a recess 81 for the source and a recess 82 for the drain are formed in the stacked layer structure 20. In addition to a first channel layer 21, a first barrier layer 22, a second channel layer 23, and a second barrier layer 24, the stacked layer structure 20 also has a source region 25 provided in the recess 81 and a drain region 26 provided in the recess 82.

Other configurations are the same as those of the third embodiment. In this way, the fourth embodiment has a configuration that combines the second and third embodiments.

When manufacturing the semiconductor device 400 according to the fourth embodiment, for example, the stacked structure 20 is formed in the same manner as in the second embodiment, and then the same processing as in the third embodiment is performed.

The fourth embodiment provides the same effects as the second embodiment and the fourth embodiment.

Note that, as long as the first band gap Eg1 of the first barrier layer 22 is larger than the second band gap Eg2 of the second barrier layer 24, the material of the first barrier layer 22 and the second barrier layer 24 is not limited to AlGaN. For example, the material of the first barrier layer 22 may be AlN, InAlN, or InAlGaN. Furthermore, the first barrier layer 22 and the second barrier layer 24 may be undoped layers.

Although the embodiments have been described in detail above, they are not limited to specific embodiments, and various modifications and variations are possible within the scope of the claims.

10: Substrate 20: Laminated structure 21: First channel layer 22: First barrier layer 23: Second channel layer 24: Second barrier layer 25: Source region 26: Drain region 31: Source electrode 32: Drain electrode 33: Gate electrode 40: Recess 41: Bottom surface 42: Inner wall surface 50: Opening 52: Inner wall surface 60: Insulating film 61, 62: Opening 65: Ultraviolet light 71, 72: 2DEG
81, 82: Recessed portion 100, 200, 300, 400: Semiconductor device

Claims (6)

A substrate;
a semiconductor layer provided on the substrate;
a source electrode and a drain electrode in ohmic contact with the semiconductor layer;
an insulating film covering a portion of the semiconductor layer between the source electrode and the drain electrode and having an opening;
a gate electrode contacting the semiconductor layer through the opening;
and
The semiconductor layer is
a first channel layer;
a first barrier layer disposed on the first channel layer and having a first bandgap;
a second channel layer provided on the first barrier layer;
a second barrier layer overlying the second channel layer and having a second bandgap smaller than the first bandgap;
and
a first recess formed in the second barrier layer;
the gate electrode contacts a bottom surface of the first recess through the opening ;
When no voltage is applied to the gate electrode, on the substrate side of the bottom surface of the first recess,
a two-dimensional electron gas exists in the first channel layer;
A semiconductor device in which no binary electron gas exists in the second channel layer . the first barrier layer is a first nitride semiconductor layer containing Al at a first concentration;
2. The semiconductor device according to claim 1, wherein the second barrier layer is a second nitride semiconductor layer containing Al at a second concentration lower than the first concentration. 3. The semiconductor device according to claim 1 , wherein a lower end of the inner wall surface of the opening is continuous with an upper end of the inner wall surface of the first recess. 3. The semiconductor device according to claim 1 , wherein an inner wall surface of the opening is located inside an inner wall surface of the first recess. a second recess is formed in the semiconductor layer on the substrate side of the source electrode, and a third recess is formed on the substrate side of the drain electrode;
the second recess and the third recess reach the first channel layer,
The semiconductor layer is
a source region formed in the second recess and having an electrical resistance lower than that of the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer;
a drain region formed in the third recess and having an electrical resistance lower than that of the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer;
and
the source electrode contacts the source region;
5. The semiconductor device according to claim 1 , wherein the drain electrode is in contact with the drain region. forming a semiconductor layer on a substrate;
forming a source electrode and a drain electrode in ohmic contact with the semiconductor layer;
forming an insulating film covering a portion of the semiconductor layer between the source electrode and the drain electrode;
forming an opening in the insulating film;
forming a gate electrode in contact with the semiconductor layer through the opening;
and
The step of forming the semiconductor layer includes:
forming a first channel layer;
forming a first barrier layer over the first channel layer, the first barrier layer having a first bandgap;
forming a second channel layer on the first barrier layer;
forming a second barrier layer over the second channel layer, the second barrier layer having a second bandgap smaller than the first bandgap;
forming a first recess in the second barrier layer by photoelectrochemical etching while irradiating the semiconductor layer with light having energy smaller than the first band gap and larger than the second band gap;
and
The method for manufacturing a semiconductor device includes forming the gate electrode so as to contact the bottom surface of the first recess through the opening.