JP7815966B2 - Semiconductor Devices - Google Patents

Description

The present invention relates to a semiconductor device.

2. Description of the Related Art Conventionally, semiconductor devices using compound semiconductors have been known (see, for example, Patent Documents 1 to 3).
Patent Document 1: WO2018/055719 Patent Document 2: JP 2020-96202 A Patent Document 3: WO2019/092871

In semiconductor devices, it is desirable to suppress dielectric breakdown of insulating films.

In order to solve the above problems, one aspect of the present invention provides a semiconductor device.
The semiconductor device may include a semiconductor substrate containing gallium and nitrogen. The semiconductor device may include a drift layer of a first conductivity type provided above the semiconductor substrate. The semiconductor device may include a first gate wiring provided above the drift layer. The semiconductor device may include a well region of a second conductivity type provided in the drift layer and exposed at an upper surface of the drift layer. The semiconductor device may include an insulating film provided between the well region and the first gate wiring. The semiconductor device may include a metal layer provided below the first gate wiring between the insulating film and the well region and making ohmic contact with the well region.

In any of the above semiconductor devices, the metal layer may contain at least one of nickel and palladium in the portion that contacts the well region.

In any of the above semiconductor devices, the well region may have a doping concentration of 1×10 ¹⁹ /cm ³ or more in a portion in contact with the metal layer.

In any of the above semiconductor devices, the metal layer may be provided over the entire area where the first gate wiring and the well region overlap when viewed from above.

In any of the above semiconductor devices, the well region may have a high-concentration region that is in contact with the metal layer and has a higher doping concentration than other portions of the well region.

In any of the above semiconductor devices, the well region may include a portion that does not overlap with the metal layer in a top view. At least a portion of the high-concentration region may be located in the portion that does not overlap with the metal layer.

Any of the above semiconductor devices may further include a source pad provided above the upper surface of the semiconductor substrate and separated from the first gate wiring. The high concentration region may be connected to the source pad.

Any of the above semiconductor devices may further include a source pad provided above the top surface of the semiconductor substrate and separated from the first gate wiring. The metal layer may be connected to the source pad.

In any of the above semiconductor devices, the insulating film may be provided closer to the source pad than the first gate wiring and may have a first contact hole connecting the source pad and the metal layer.

In any of the above semiconductor devices, the insulating film may have a second contact hole connecting the source pad to the upper surface of the semiconductor substrate. The opening width of the first contact hole may be larger than the opening width of the second contact hole.

Any of the above semiconductor devices may further include a source pad provided above the drift layer and separated from the first gate wiring. The metal layer may be separated from the source pad.

Any of the above semiconductor devices may further include a second gate wiring made of polysilicon, which is provided between the first gate wiring and the drift layer and connected to the first gate wiring. In a top view, the metal layer may be provided in an area that does not overlap with the second gate wiring.

Any of the above semiconductor devices may further include a second gate wiring made of polysilicon, provided between the first gate wiring and the drift layer and connected to the first gate wiring. The semiconductor device may further include an active portion surrounded by the well region in a top view. The semiconductor device may further include a breakdown voltage structure portion provided outside the well region in a top view. The first gate wiring may extend closer to the breakdown voltage structure portion than the second gate wiring in a top view.

Any of the above semiconductor devices may further include a second gate wiring made of polysilicon, provided between the first gate wiring and the drift layer and connected to the first gate wiring. The semiconductor device may further include an active portion surrounded by the well region in a top view. The semiconductor device may further include a breakdown voltage structure portion provided outside the well region in a top view. The semiconductor device may further include a source pad provided above the drift layer in the active portion and separated from the first gate wiring. In a top view, the second gate wiring may have a protruding portion that protrudes further toward the breakdown voltage structure portion than the first gate wiring. The semiconductor device may further include a source connection portion provided above the protruding portion and connected to the source pad.

Any of the above semiconductor devices may further include an active portion surrounded by the well region in a top view. The semiconductor device may further include a breakdown voltage structure portion provided outside the well region in a top view. A plurality of the metal layers may be arranged at intervals in a direction connecting the active portion and the breakdown voltage structure portion.

Any of the above semiconductor devices may further include an active portion surrounded by the well region in a top view. The semiconductor device may include a breakdown voltage structure portion located outside the well region in a top view. The semiconductor device may include a source pad located above the drift layer and separated from the first gate wiring. The semiconductor device may include a source connection portion located closer to the breakdown voltage structure portion than the metal layer in a top view, connecting the well region to the source pad.

The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also constitute inventions.

1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of a cross section taken along the line AA in FIG. 1. FIG. 10 is a diagram showing another example of the AA cross section. FIG. 10 is a diagram showing another example of the AA cross section. FIG. 10 is a diagram showing another example of the AA cross section. FIG. 10 is a diagram showing another example of the AA cross section. 7 is a diagram showing an example of the arrangement of the metal layer 70 in the example of FIG. 6 as viewed from above. 1 is a diagram showing an example of a cross section of the semiconductor device 100 taken along the line BB. FIG. 10 is a diagram showing an example of the arrangement of the source connection portion 66 in a top view. FIG. 10 is a diagram showing another example of the AA cross section. FIG. 10 is a diagram showing another example of the AA cross section. FIG. 10 is a diagram showing another example of the AA cross section. FIG. 10 is a diagram showing another example of the AA cross section. FIG. 10 is a diagram showing another example of the AA cross section. 1A to 1C are diagrams illustrating an example of a method for manufacturing the semiconductor device 100. FIG. 10 is a diagram showing a process following step S303. FIG. 10 is a diagram showing another example of the AA cross section.

The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "top" and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the top surface and the other surface is referred to as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

In this specification, technical matters may be explained using the Cartesian coordinate axes of the X, Y, and Z axes. The Cartesian coordinate axes merely identify the relative positions of components and do not limit specific directions. For example, the Z axis does not limit the height direction relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the Z axis direction is referred to without specifying positive or negative, it means the direction parallel to the +Z axis and the -Z axis.

In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

In this specification, terms such as "same" or "equal" may include cases where there is a margin of error due to manufacturing variations, etc. Such an error is, for example, within 10%.

In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is used in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system used in this specification is the SI unit system unless otherwise specified. In this specification, an example is described in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may also be P type and the second conductivity type may also be N type.

If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the donor, acceptor, or net doping concentration in that region. In cases where the donor, acceptor, or net doping concentration is approximately uniform, the average value of the donor, acceptor, or net doping concentration in that region may be taken as the donor, acceptor, or net doping concentration.

Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. Figure 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Figure 1 shows only some of the components of the semiconductor device 100, with some components omitted.

The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material containing gallium (Ga) and nitrogen (N). As an example, the semiconductor substrate 10 is a GaN substrate, but the semiconductor substrate 10 may be a GaN-based substrate such as AlGaN. The semiconductor substrate 10 has edges 102 when viewed from above. In this specification, the term "top view" refers to a view from the top surface of the semiconductor substrate 10. In the top view, each component may be projected onto the top surface of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 102 that face each other when viewed from above. In FIG. 1, the X-axis and Y-axis are parallel to either edge 102. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

The semiconductor substrate 10 has an active portion 80. The active portion 80 is a region through which a main current, such as a collector current, a drain current, or an anode-cathode current, flows when the semiconductor device 100 is operating. The semiconductor device 100 in this example is a vertical device in which a main current flows between the top and bottom surfaces of the semiconductor substrate 10. In this case, the active portion 80 is a region between the top and bottom surfaces of the semiconductor substrate 10 through which a main current flows in the depth direction. The semiconductor device 100 may also be a horizontal device in which a main current flows in a direction parallel to the top surface of the semiconductor substrate 10.

This specification describes an example in which a MOS transistor is provided in the active section 80, but the active section 80 may also be provided with an IGBT (Insulated Gate Bipolar Transistor). In this case, "MOS transistor" in this specification may be replaced with "IGBT," "source" with "emitter," and "drain" with "collector." Furthermore, if an IGBT is provided in the active section 80, a P-type collector region is formed in at least a portion of the underside of the semiconductor substrate 10 in the active section 80. The active section 80 may also be provided with a free wheel diode (FWD) connected in anti-parallel to the MOS transistor or IGBT.

The semiconductor device 100 of this example is a vertical device in which a MOS (Metal Oxide Semiconductor) transistor is formed in the active section 80. A source pad 60 may be provided above the active section 80. The area covered by the source pad 60 may also be referred to as the active section 80. A source voltage is applied to the source pad 60. The source pad 60 is also connected to the source region of the MOS transistor in the active section 80.

The semiconductor device 100 has a gate pad 50 located above the semiconductor substrate 10. The gate pad 50 is located between the active portion 80 and the edge 102. While the gate pad 50 in FIG. 1 is located at a corner of the semiconductor substrate 10, the location of the gate pad 50 is not limited to this. A gate voltage is applied to the gate pad 50. The gate pad 50 is connected to the gate electrode of the MOS transistor in the active portion 80. The source pad 60 and gate pad 50 may be formed of a metal such as aluminum.

The semiconductor device 100 has a first gate wiring 52 disposed above the semiconductor substrate 10. The first gate wiring 52 connects the gate pad 50 to the gate electrode of the MOS transistor in the active portion 80. The first gate wiring 52 may be formed of the same material as the gate pad 50. The gate pad 50 and the first gate wiring 52 may surround the active portion 80 in a top view. The area surrounded by the gate pad 50 and the first gate wiring 52 in a top view may be defined as the active portion 80. A P-type well region is formed below the gate pad 50 and the first gate wiring 52, but is omitted from FIG. 1 . This well region may also surround the active portion 80 along the gate pad 50 and the first gate wiring 52. The area surrounded by the well region may be defined as the active portion 80.

The gate pad 50 and first gate wiring 52 are separated from the source pad 60. In top view, an interlayer insulating film 38 may be disposed between the gate pad 50 and first gate wiring 52 and the source pad 60. The interlayer insulating film 38 may be an insulating film such as phosphorus-doped silicate glass (PSG) or phosphorus- and boron-doped silicate glass (PBSG).

When viewed from above, the semiconductor device 100 may have a breakdown voltage structure 90 between the active section 80 and the edge 102. In this example, the breakdown voltage structure 90 surrounds the active section 80. In this example, the gate pad 50 and first gate wiring 52 are arranged between the active section 80 and the breakdown voltage structure 90. The breakdown voltage structure 90 extends the depletion layer outside the active section 80, thereby alleviating electric field concentration and improving the breakdown voltage of the semiconductor device 100. The breakdown voltage structure 90 may have at least one of a P-type guard ring and a field plate.

Figure 2 is a diagram showing an example of the A-A cross section in Figure 1. The A-A cross section is an XZ plane that passes through part of the active section 80, the first gate wiring 52, and part of the breakdown voltage structure section 90. In this cross section, the semiconductor device 100 includes a semiconductor substrate 10, a drift layer 16, a drain electrode 24, a source pad 60, and a first gate wiring 52. In this example, a gate insulating film 39, an interlayer insulating film 38, a field insulating film 40, a gate electrode 56, a second gate wiring 54, and a metal layer 70 are provided above the drift layer 16. The gate insulating film 39, the interlayer insulating film 38, and the field insulating film 40 are each an example of an insulating film.

In this example, the semiconductor substrate 10 is N-type. A drain electrode 24 is formed on the underside of the semiconductor substrate 10. The drain electrode 24 is made of a metal such as aluminum. The semiconductor substrate 10 may function as the drain region of a MOS transistor.

The drift layer 16 is provided above the semiconductor substrate 10. In this example, the drift layer 16 is stacked on the upper surface of the semiconductor substrate 10. The drift layer 16 contains gallium and nitrogen. The material of the drift layer 16 may be the same as that of the semiconductor substrate 10. The drift layer 16 may be formed by epitaxial growth. In this example, the drift layer 16 is N-type, with a lower doping concentration than the semiconductor substrate 10.

In the active section 80, a P-type base region 14 and an N+-type source region 12 are disposed on the upper surface of the drift layer 16. The doping concentration of the source region 12 is higher than that of the drift layer 16. The source region 12 may be surrounded by the base region 14. The base region 14 has a portion on the upper surface of the drift layer 16 that is sandwiched between the source region 12 and the drift layer 16. A channel is formed in this portion, allowing current to flow between the source region 12 and the drift layer 16.

In the breakdown voltage structure 90, a P-type guard ring 20 is disposed on the upper surface of the drift layer 16. Multiple guard rings 20 may be disposed between the active portion 80 and the edge 102 of the semiconductor substrate 10.

A P-type well region 18 is exposed on the upper surface of the drift layer 16 between the active portion 80 and the breakdown voltage structure portion 90. The well region 18 may be provided deeper than the base region 14, or may be provided to the same depth as the base region 14. The area in which the well region 18 is provided in a top view is referred to as an isolation region 85. In this example, the isolation region 85 surrounds the active portion 80. The gate pad 50 and first gate wiring 52 may be provided in the isolation region 85. The end of the well region 18 on the active portion 80 side may be the boundary between the active portion 80 and the isolation region 85. The end of the well region 18 on the breakdown voltage structure portion 90 side may be the boundary between the breakdown voltage structure portion 90 and the isolation region 85.

The upper surface of the drift layer 16 in the active portion 80 is covered with a gate insulating film 39 and an interlayer insulating film 38. The gate insulating film 39 may be a silicon oxide film or nitride film, or an aluminum oxide film. The source pad 60 is connected to the source region 12 through a contact hole 61 provided in the gate insulating film 39 and the interlayer insulating film 38.

The gate electrode 56 is disposed above the drift layer 16. A gate insulating film 39 is provided between the gate electrode 56 and the drift layer 16. The gate electrode 56 is formed, for example, from polysilicon doped with impurities. The gate electrode 56 may also be formed from a metal such as aluminum. The gate electrode 56 is electrically connected to the first gate wiring 52 or the gate pad 50. The gate electrode 56 is disposed above a portion of the base region 14 that is sandwiched between the source region 12 and the drift layer 16. When a gate voltage is applied to the gate electrode 56, the surface layer of that portion of the base region 14 is inverted to N-type, forming a channel.

The upper surface of the drift layer 16 in the breakdown voltage structure 90 is covered with at least one of the following insulating films: a field insulating film 40, a gate insulating film 39, and an interlayer insulating film 38. In the example of FIG. 2, three layers, namely, a field insulating film 40, a gate insulating film 39, and an interlayer insulating film 38, are stacked on the upper surface of the drift layer 16. The field insulating film 40 may be a silicon oxide film or a silicon nitride film, or may be an aluminum oxide film. The gate insulating film 39 may be formed on the field insulating film 40. The interlayer insulating film 38 may be formed on the gate insulating film 39.

The upper surface of the drift layer 16 in the isolation region 85 is covered with the gate insulating film 39 and the interlayer insulating film 38. The source pad 60 may be connected to the well region 18 through contact holes provided in the gate insulating film 39 and the interlayer insulating film 38.

The first gate wiring 52 is provided above the drift layer 16. In this example, the first gate wiring 52 is disposed above a well region 18 formed in the drift layer 16. In this example, the first gate wiring 52 is insulated from the well region 18 by an interlayer insulating film 38. In other words, at least a portion of the interlayer insulating film 38 is provided between the first gate wiring 52 and the well region 18.

A second gate wiring 54 may be provided between the first gate wiring 52 and the drift layer 16. The second gate wiring 54 is formed, for example, of polysilicon doped with impurities. The second gate wiring 54 may be provided along the first gate wiring 52 and the gate pad 50 and surround the active portion 80. An insulating layer such as an interlayer insulating film 38 is provided between the first gate wiring 52 and the second gate wiring 54. However, the first gate wiring 52 and the second gate wiring 54 are connected via a contact hole provided in the insulating layer. The contact hole may also be provided along the second gate wiring 54 and surround the active portion 80. The second gate wiring 54 is disposed above the well region 18. At least one of a gate insulating film 39 and a field insulating film 40 may be provided between the second gate wiring 54 and the well region 18.

The metal layer 70 is provided below the first gate wiring 52, between the interlayer insulating film 38 and the well region 18. The metal layer 70 may have a portion that does not overlap with the first gate wiring 52 in a top view. In this example, the metal layer 70 is provided extending toward the active section 80 beyond the first gate wiring 52.

The metal layer 70 is in ohmic contact with the well region 18. Ohmic contact refers to a state in which the current-voltage characteristics are linear when a current and a voltage are applied to the contact portion (i.e., the resistance value is approximately constant regardless of the voltage or current). The metal layer 70 may contain at least one of nickel and palladium in the portion in contact with the well region 18. The metal layer 70 may contain titanium or titanium nitride in the portion in contact with the well region 18. The metal layer 70 may contain at least one of platinum (Pt) and gold (Au). The metal layer 70 may be a single layer of these metals or alloys, or may have a laminated structure. An ohmic contact may be defined when the contact resistance between the metal layer 70 and the well region ¹⁸ is 0.1 Ωcm² or less, 0.01 ^Ωcm² or less, or 0.005 ^Ωcm² or less.

The doping concentration of the well region 18 may be 1×10 ¹⁷ /cm ³ or more, or may be 1×10 ¹⁸ /cm ³ or more. Increasing the doping concentration of the well region 18 also reduces the contact resistance. The doping concentration of the portion of the well region 18 that contacts the metal layer 70 may be 1×10 ¹⁹ /cm ³ or more. The doping concentration of this portion may be 1×10 ²⁰ /cm ³ or more. The doping concentration of the well region 18 may be 1×10 ²¹ /cm ³ or less.

When the MOS transistor provided in the active portion 80 transitions from on to off, the voltage of the drain electrode 24 rises sharply. In this case, a displacement current flows in both the well region 18 and the semiconductor substrate 10 via the depletion layer capacitance between the well region 18 and the semiconductor substrate 10. The magnitude of the displacement current is proportional to the rate of change of the source-drain voltage over time (dV/dt). Therefore, the faster the switching operation of the semiconductor device 100, the larger the displacement current that flows.

The hole carriers of the displacement current that reach the well region 18 move through the well region 18 in a direction parallel to the top surface of the drift layer 16 and flow to the source pad 60. As a result, the potential of the well region 18 rises in accordance with the resistance in the well region 18 and the magnitude of the displacement current. When the potential of the well region 18 rises, the potential difference with the first gate wiring 52 (or second gate wiring 54) increases, and a large voltage is applied to insulating films such as the field insulating film 40 and gate insulating film 39. Therefore, if the resistance of the well region 18 is high, the potential fluctuation in the well region 18 increases, and a large voltage is applied to insulating films such as the field insulating film 40 and gate insulating film 39, which may cause dielectric breakdown.

In the semiconductor device 100 of this example, a metal layer 70 is provided in ohmic contact with the well region 18. The sheet resistance of the metal layer 70 is smaller than the sheet resistance of the well region 18. By providing the metal layer 70, at least a portion of the hole carriers that reach the well region 18 move within the metal layer 70. This reduces the effective sheet resistance of the well region 18, and suppresses potential fluctuations in the well region 18. This prevents dielectric breakdown of insulating films such as the field insulating film 40 and gate insulating film 39.

The metal layer 70 may be arranged so as to overlap with at least half the width of the first gate wiring 52 in the X-axis direction. The metal layer 70 may be arranged so as to overlap with the entire first gate wiring 52 in the X-axis direction. Note that "overlapping" refers to overlapping in position when viewed from above.

The position of the X-axis end of the contact hole 62 connecting the source pad 60 to the well region 18 is designated X1. Position X1 is the position of the end of the contact hole 62 closest to the breakdown voltage structure 90. The position of the end of the first gate wiring 52 closest to the active portion 80 in the X-axis direction is designated X2. The metal layer 70 may be provided over more than half of the region from position X2 to position X1 in the X-axis direction, or may be provided over the entire region. The metal layer 70 may be directly connected to the source pad 60. In this case, the potential of the metal layer 70 can be fixed. Furthermore, the effective sheet resistance of the well region 18 can be reduced, thereby suppressing potential fluctuations in the well region 18. The metal layer 70 does not have to be connected to the source pad 60. The metal layer 70 may be electrically floating, without being connected to an electrode or wiring. Even in this case, providing the metal layer 70 reduces the effective sheet resistance of the well region 18 and suppresses potential fluctuations in the well region 18.

The metal layer 70 only needs to be thick enough to allow hole carriers to move in the XY plane. In this specification, "thickness" refers to the length in the Z-axis direction. The metal layer 70 may have a thickness of 1 nm or more. The thickness of the metal layer 70 may be 10 nm or more. If the metal layer 70 is too thick, the flatness above the drift layer 16 will deteriorate. The thickness of the metal layer 70 may be 500 nm or less, 300 nm or less, 100 nm or less, 50 nm or less, or 10 nm or less. The thickness of the metal layer 70 may be smaller than the thickness of the field insulating film 40 and may be smaller than the thickness of the interlayer insulating film 38. This prevents the flatness above the drift layer 16 from deteriorating. The metal layer 70 may be entirely formed on the well region 18, or at least partially embedded in the well region 18. As an example, the thickness of the field insulating film 40 is 200 nm to 800 nm, the thickness of the interlayer insulating film 38 is 500 nm to 2000 nm, the thickness of the gate insulating film 39 is 50 nm to 200 nm, the thickness of the well region 18 is 300 nm to 1000 nm, and the thickness of the source pad 60 and first gate wiring 52 is 3 μm to 5 μm.

When viewed from above, the metal layer 70 may be provided in an area that does not overlap with the second gate wiring 54. In this example, the second gate wiring 54 is disposed above the field insulating film 40, and the metal layer 70 is disposed in an area where the field insulating film 40 is not provided.

Figure 3 is a diagram showing another example of the A-A cross section. The semiconductor device 100 of this example further includes a high-concentration region 19 in addition to the configuration shown in Figure 2. The configuration other than the high-concentration region 19 is the same as the example described in Figures 1 and 2.

The high concentration region 19 is a part of the well region 18. The high concentration region 19 is in contact with the metal layer 70 and has a higher doping concentration than other parts of the well region 18. The doping concentration of the high concentration region 19 may be 1×10 ¹⁹ /cm ³ or more. The doping concentration of the well region 18 other than the high concentration region 19 may be 1×10 ¹⁸ /cm ³ or less.

In this cross section, the high concentration region 19 may be provided in more than half of the well region 18 that contacts the metal layer 70, or may be provided in the entire well region 18. The high concentration region 19 may be provided over the entire surface of the well region 18. The high concentration region 19 may be in contact with the source pad 60.

Figure 4 is a diagram showing another example of the A-A cross section. The semiconductor device 100 of this example differs from the configuration shown in Figure 3 in the range in which the high concentration region 19 is provided. The configuration other than the high concentration region 19 is the same as any of the examples described in Figures 1 to 3.

In this example, the well region 18 has a portion 22 that does not overlap with the metal layer 70 in a top view. At least a portion of the high-concentration region 19 in this example is located in portion 22. The high-concentration region 19 may be provided over the entire portion 22. With this configuration, at least one of the metal layer 70 and the high-concentration region 19 is provided on the upper surface of the well region 18. This reduces the sheet resistance over the entire well region 18. The high-concentration region 19 may be connected to the source pad 60. As shown in FIG. 4, the high-concentration region 19 may be provided over the entire upper surface of the well region 18.

Figure 5 is a diagram showing another example of the A-A cross section. The semiconductor device 100 of this example differs from the examples described in Figures 1 to 4 in the range in which the metal layer 70 is provided. The structure other than the metal layer 70 is the same as any of the examples described in Figures 1 to 4.

In this example, the metal layer 70 is not connected to the source pad 60. An interlayer insulating film 38 may be provided between the metal layer 70 and the source pad 60. Even in this example, the metal layer 70 may be provided over more than half of the region from position X2 to position X1 in the X-axis direction, or may be provided over the entire region.

Figure 6 is a diagram showing another example of the A-A cross section. The semiconductor device 100 of this example differs from the examples described in Figures 1 to 5 in the structure of the metal layer 70. The structure other than the metal layer 70 is the same as any of the examples described in Figures 1 to 5.

In this example, multiple metal layers 70 are arranged at intervals in the direction connecting the active section 80 and the breakdown voltage structure section 90. The direction connecting the active section 80 and the breakdown voltage structure section 90 is, for example, the X-axis direction or the Y-axis direction perpendicular to the edge 102 of the semiconductor substrate 10. In the direction connecting the active section 80 and the breakdown voltage structure section 90, the range in which the multiple metal layers 70 are provided is the same as the range of any of the metal layers 70 described in Figures 1 to 5. In the example of Figure 6, the metal layers 70 are provided at predetermined intervals from the position in contact with the source pad 60 to the position in contact with the field insulating film 40.

The surface of the well region 18 is prone to numerous defects due to factors such as interface damage during the formation of the insulating film. Therefore, the surface of the well region 18 is prone to becoming a leakage path for current in the direction from the active section 80 toward the breakdown voltage structure section 90. If the metal layer 70 is formed continuously in the direction from the active section 80 toward the breakdown voltage structure section 90, current leakage may be accelerated.

In this example, the metal layers 70 are separated in the direction from the active section 80 toward the breakdown voltage structure section 90, thereby preventing current leakage caused by the metal layers 70. Two or more metal layers 70 may be provided in this direction, or three or more metal layers 70 may be provided. The metal layer 70 arranged closest to the active section 80 may or may not be connected to the source pad 60.

The metal layers 70 may be electrically isolated from each other. In another example, the semiconductor device 100 may have a connection portion that electrically connects the metal layers 70 at a position away from the surface of the well region 18. In this case, the potential of the metal layers 70 can be the same.

The spacing between each metal layer 70 may or may not be constant. In the direction from the active section 80 toward the breakdown voltage structure section 90, the distance between the metal layers 70 may be smaller than the width of one metal layer 70. The distance between the metal layers 70 may be less than half the width of one metal layer 70, or may be less than 10%. The distance between the metal layers 70 may be 1 μm or more, 5 μm or more, or 10 μm or more. The distance between the metal layers 70 may be 50 μm or less. The spacing and width of the metal layers 70 may also be changed depending on the position when viewed from above. For example, the spacing between the metal layers 70 may be larger in areas where current leakage is likely to occur than in other areas.

Figure 7 is a diagram showing an example of the arrangement of the metal layer 70 in the example of Figure 6 when viewed from above. In Figure 7, the metal layer 70 is shown by a thick line or a filled-in black rectangle. As shown in Figure 7, two or more metal layers 70 are provided to surround the active section 80. In addition, in the region overlapping with the gate pad 50, the metal layers 70 are arranged at predetermined intervals in both the X-axis direction and the Y-axis direction.

As described above, the distance between the metal layers 70 surrounding the active portion 80 may vary depending on the position when viewed from above. The semiconductor substrate 10 has a corner 11, a region B, and a region C. The corner 11 is the vertex of the semiconductor substrate 10 when viewed from above. Region B is an isolation region 85 near the corner 11. Region C is an isolation region 85 that is further away from the corner 11 than region B. The distance between the metal layers 70 in region B may be greater than the distance between the metal layers 70 in region C. Leakage current is likely to occur near the corner 11, but this configuration can suppress the leakage current near the corner 11.

Figure 8 is a diagram showing an example of the B-B cross section of the semiconductor device 100. The B-B cross section is a cross section obtained by excluding the active portion 80 from the A-A cross section. In addition to the configuration of the semiconductor device 100 described in Figures 1 to 7, the semiconductor device 100 of this example further includes a source connection portion 66 connected to the well region 18. The source connection portion 66 is a conductive member electrically connected to the source pad 60. The source connection portion 66 may be formed from the same material as the source pad 60.

The source connection portion 66 is located closer to the breakdown voltage structure portion 90 than the metal layer 70 when viewed from above. In this example, the source connection portion 66 is connected to the well region 18 via a contact hole 64 that penetrates the interlayer insulating film 38, gate insulating film 39, and field insulating film 40. By electrically connecting the well region 18 to the source pad 60 on both sides of the metal layer 70, it is possible to suppress a rise in the potential of the well region 18.

The longer the distance that holes travel in the X direction through the well region 18, the higher the potential of the well region 18. In this example, the distance traveled by holes that reach the well region 18 in the center between the contact holes 62 and 64 is the longest when they travel through the well region 18 toward the contact hole 62 or the contact hole 64. For this reason, the potential of the well region 18 in the center between the contact holes 62 and 64 is relatively likely to rise. The metal layer 70 may be provided in a range that includes the center between the contact holes 62 and 64.

The metal layer 70 may be connected to the source connection portion 66. When the metal layer 70 and the source connection portion 66 are separated as shown in FIG. 8, a high concentration region 19 may be provided between the metal layer 70 and the source connection portion 66. The high concentration region 19 may be connected to both the metal layer 70 and the source connection portion 66.

Figure 9 shows an example of the arrangement of the source connection portion 66 when viewed from above. Figure 9 shows the semiconductor substrate 10, active portion 80, source pad 60, gate pad 50, first gate wiring 52, source connection portion 66, and interlayer insulating film 38, and omits other components.

The source connection portion 66 surrounds the active portion 80 outside the gate pad 50 and the first gate wiring 52. In this example, the first gate wiring 52 has a gap 53 that connects the inner region surrounded by the first gate wiring 52 (the region where the source pad 60 is provided) with the outer region of the first gate wiring 52 (the region where the source connection portion 66 is provided). In other words, in this example, the first gate wiring 52 is interrupted at the gap 53. The source connection portion 66 connects to the source pad 60 through the gap 53. With this configuration, the source connection portion 66 can be at the same potential as the source pad 60. Only one gap 53 may be provided.

Figure 10 is a diagram showing another example of the A-A cross section. The semiconductor device 100 of this example has contact holes 61, 62, and 63. The other structures are the same as any of the examples described in Figures 1 to 9.

The contact hole 62 is provided through the interlayer insulating film 38, closer to the source pad 60 than the first gate wiring 52. The contact hole 62 connects the source pad 60 and the metal layer 70. In this example, the well region 18 is not exposed at the bottom of the contact hole 62, but the well region 18 may be partially exposed. In this example, the metal layer 70 is exposed over the entire bottom surface of the contact hole 62. The contact hole 62 is an example of a first contact hole. The contact hole 62 may surround the active portion 80 in a top view.

In this example, contact holes 61 and 63 are provided through interlayer insulating film 38 and gate insulating film 39. Contact hole 61 connects source pad 60 to source region 12. Contact hole 63 connects source pad 60 to well region 18. Metal layer 70 is not exposed in contact hole 63. Contact holes 61 and 63 are examples of second contact holes.

Contact holes 61 and 63 may be formed by dry etching. Contact holes 61 and 63 penetrate the relatively thick interlayer insulating film 38. When semiconductor device 100 is miniaturized, contact holes 61 and 63 are also miniaturized, but it is difficult to form fine contact holes using wet etching.

The contact holes 62 may be formed by wet etching. The metal layer 70 is exposed at the bottom of the contact holes 62. Therefore, if the contact holes 62 are formed by dry etching, impurities may be scattered from the metal layer 70, contaminating the etching equipment. When formed by wet etching, the opening width of the contact holes becomes relatively large, but the area near the first gate wiring 52 has a larger margin for arranging components than the area near the active section 80, so the contact holes 62 can be formed by wet etching.

The opening width W2 of contact hole 62 may be larger than the opening width W1 of contact hole 61. The opening width W2 of contact hole 62 may be larger than the opening width W3 of contact hole 63. Each opening width is the width in the direction from the active portion 80 toward the breakdown voltage structure portion 90 (in this example, the X-axis direction). The opening width may be measured on the top surface of the interlayer insulating film 38, or at the center position of the thickness of the interlayer insulating film 38. The opening width W2 may be 1.5 times or more larger than the opening width W1 and the opening width W3, or may be 2 times or more larger.

Figure 11 is a diagram showing another example of the A-A cross section. The semiconductor device 100 of this example differs from the examples shown in Figures 1 to 10 in the range in which the first gate wiring 52 is provided. The rest of the structure is the same as any of the examples described in Figures 1 to 10.

In this example, the first gate wiring 52 extends closer to the breakdown voltage structure 90 than the second gate wiring 54 in a top view. In the example of FIG. 11 , end position X4 of the first gate wiring 52 in the X-axis direction is closer to the breakdown voltage structure 90 than end position X3 of the second gate wiring 54 in the X-axis direction. The thickness of the insulating films (interlayer insulating film 38, gate insulating film 39, and field insulating film 40 in this example) located below the first gate wiring 52 at position X4 is greater than the thickness of the insulating films (gate insulating film 39 and field insulating film 40 in this example) located below the second gate wiring 54 at position X3. In this example, the electric field is dispersed to the extending portion of the first gate wiring 52, thereby mitigating electric field concentration in the insulating film. Furthermore, because the insulating film below the extending portion is relatively thick, dielectric breakdown in that portion is suppressed.

Position X4 may be located above the well region 18, above the edge of the well region 18, or in the breakdown voltage structure 90. The longer the first gate wiring 52 is extended, the more electric field concentration can be alleviated. Furthermore, the extension length of the first gate wiring 52 (the distance between positions X4 and X3) may be uniform or may vary at each position when viewed from above. For example, the extension length of the first gate wiring 52 in region B shown in Figure 7 may be longer than the extension length of the first gate wiring 52 in region C. This allows electric field concentration to be alleviated near the corners 11 where electric fields tend to concentrate.

Figure 12 is a diagram showing another example of the A-A cross section. The semiconductor device 100 of this example differs from the examples of Figures 1 to 10 in that a source connection portion 65 is provided. The other structures are the same as any of the examples described in Figures 1 to 10. The source connection portion 65 of this example differs from the source connection portion 66 described in Figures 8 and 9 in that it is not connected to the well region 18. In other respects, it may be the same as the source connection portion 66. For example, the source connection portion 65 is electrically connected to the source pad 60, similar to the source connection portion 66 described in Figures 8 and 9. The arrangement of the source connection portion 65 in a top view may be the same as the source connection portion 66 described in Figures 8 and 9.

In this example, the second gate wiring 54 has a protruding portion 55 that protrudes further toward the breakdown voltage structure 90 than the first gate wiring 52. The source connection portion 65 is provided above the protruding portion 55. The source connection portion 65 may be arranged so as to cover the end of the protruding portion 55 on the breakdown voltage structure 90 side. This structure can mitigate electric field concentration near the end of the second gate wiring 54.

Figure 13 is a diagram showing another example of the A-A cross section. The semiconductor device 100 of this example differs from the example of Figure 12 in the range in which the source connection portion 65 is provided. The other structures are similar to the example of Figure 12. The source connection portion 65 of this example extends up to above the guard ring 20 of the breakdown voltage structure portion 90 that is closest to the isolation region 85. This allows the source connection portion 65 to also function as a field plate for the breakdown voltage structure portion 90.

Figure 14 is a diagram showing another example of the A-A cross section. The semiconductor device 100 of this example differs from the examples of Figures 1 to 13 in the area where the metal layer 70 is provided. The rest of the structure is similar to the examples of Figures 1 to 13. In this example, the metal layer 70 is provided over the entire area where the first gate wiring 52 and the well region 18 overlap in a top view. The metal layer 70 may also be provided over the entire area where the second gate wiring 54 and the well region 18 overlap. This configuration makes it possible to suppress breakdown of the insulating film over a wider area. The metal layer 70 may extend to the breakdown voltage structure portion 90. The metal layer 70 of this example may also be separated into multiple parts, as in the example of Figure 6.

Figure 15 is a diagram illustrating an example of a method for manufacturing a semiconductor device 100. First, in step S301, a drift layer 16 is formed on the upper surface of a semiconductor substrate 10. The drift layer 16 may be formed by epitaxial growth. A base region 14, a well region 18, and a guard ring 20 are formed on the upper surface of the drift layer 16. A source region 12 is formed within the base region 14. Each region may be formed by ion implantation or epitaxial growth.

Next, in step S302, a field insulating film 40 and a gate insulating film 39 are formed on the upper surface of the drift layer 16. The gate insulating film 39 may be formed by, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD). The field insulating film 40 may be formed by, for example, chemical vapor deposition (CVD).

Next, in step S303, a gate electrode 56 and a second gate wiring 54 are formed on the upper surface of the gate insulating film 39. The gate electrode 56 and the second gate wiring 54 may be formed by, for example, chemical vapor deposition (CVD). A metal layer 70 is also formed. The metal layer 70 may be formed by evaporation or the like.

Figure 16 shows the process following step S303. In step S304, an interlayer insulating film 38 is formed, and contact holes are formed in the interlayer insulating film 38. The interlayer insulating film 38 may be formed by, for example, chemical vapor deposition (CVD). The contact holes are formed by wet etching or dry etching.

Next, in step S305, the source pad 60, drain electrode 24, and first gate wiring 52 are formed. The source pad 60 and first gate wiring 52 may be formed by, for example, a vapor deposition method. The semiconductor device 100 can be manufactured using a manufacturing method including these steps.

Figure 17 is a diagram showing another example of the A-A cross section. The semiconductor device 100 of this example differs from the examples described in Figures 1 to 16 in the structure of the transistor provided in the active portion 80. The other structures are the same as any of the examples described in Figures 1 to 16.

The active portion 80 in this example has a trench gate 37. The trench gate 37 is formed to penetrate the source region 12 and base region 14 and reach the N-type region. A gate insulating film 39 is formed on the inner wall of the trench gate 37, and the region surrounded by the gate insulating film 39 is filled with a gate electrode 56. When a predetermined gate voltage is applied to the gate electrode 56, the surface layer of the base region 14 in contact with the gate insulating film 39 is inverted to N-type, forming a channel.

The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

The order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," or the like, and it should be noted that processes can be performed in any order, unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that it is necessary to perform the processes in that order.

10: Semiconductor substrate, 11: Corner, 12: Source region, 14: Base region, 16: Drift layer, 18: Well region, 19: High-concentration region, 20: Guard ring, 22: Portion, 24: Drain electrode, 37: Trench gate, 38: Interlayer insulating film, 39: Gate insulating film, 40: Field insulating film, 50: Gate pad, 52: First gate wiring, 53: Gap, 54: Second gate wiring, 55: Protrusion, 56: Gate electrode, 60: Source pad, 61, 62, 63, 64: Contact holes, 65, 66: Source connection portion, 70: Metal layer, 80: Active portion, 85: Isolation region, 90: Breakdown structure portion, 100: Semiconductor device, 102: Edge

Claims (16)

a semiconductor substrate comprising gallium and nitrogen;
a drift layer of a first conductivity type provided above the semiconductor substrate;
a first gate wiring provided above the drift layer;
a second conductivity type well region provided in the drift layer and exposed on an upper surface of the drift layer;
an insulating film provided between the well region and the first gate wiring;
a metal layer provided between the insulating film and the well region below the first gate wiring, the metal layer making ohmic contact with the well region. The semiconductor device according to claim 1 , wherein the metal layer contains at least one of nickel and palladium in a portion that contacts the well region. 2. The semiconductor device according to claim 1, wherein the well region has a doping concentration of 1×10 ¹⁹ /cm ³ or more in a portion in contact with the metal layer. The semiconductor device according to claim 1 , wherein the metal layer is provided over an entire area where the first gate wiring and the well region overlap in a top view. The semiconductor device according to claim 1 , wherein the well region has a high concentration region that is in contact with the metal layer and has a doping concentration higher than that of other portions of the well region. the well region includes a portion that does not overlap with the metal layer in a top view;
The semiconductor device according to claim 5 , wherein at least a part of the high concentration region is disposed in a portion that does not overlap with the metal layer. a source pad provided above the upper surface of the semiconductor substrate and separated from the first gate wiring;
The semiconductor device according to claim 5 , wherein the high concentration region is connected to the source pad. a source pad provided above the upper surface of the semiconductor substrate and separated from the first gate wiring;
The semiconductor device according to claim 1 , wherein the metal layer is connected to the source pad. The semiconductor device according to claim 8 , wherein the insulating film is provided closer to the source pad than the first gate wiring, and has a first contact hole connecting the source pad and the metal layer. the insulating film has a second contact hole connecting the source pad to the upper surface of the semiconductor substrate;
The semiconductor device according to claim 9 , wherein the opening width of the first contact hole is larger than the opening width of the second contact hole. a source pad provided above the drift layer and separated from the first gate wiring;
The semiconductor device according to claim 1 , wherein the metal layer is separated from the source pad. a second gate wiring made of polysilicon provided between the first gate wiring and the drift layer and connected to the first gate wiring;
The semiconductor device according to claim 1 , wherein the metal layer is provided in a range that does not overlap the second gate wiring when viewed from above. a second gate wiring made of polysilicon provided between the first gate wiring and the drift layer and connected to the first gate wiring;
an active portion surrounded by the well region in top view;
a breakdown voltage structure provided outside the well region when viewed from above,
The semiconductor device according to claim 1 , wherein the first gate wiring is provided so as to extend closer to the breakdown voltage structure portion than the second gate wiring when viewed from above. a second gate wiring made of polysilicon provided between the first gate wiring and the drift layer and connected to the first gate wiring;
an active portion surrounded by the well region in top view;
a breakdown voltage structure provided outside the well region when viewed from above;
a source pad provided above the drift layer in the active portion and separated from the first gate wiring;
the second gate wiring has a protruding portion that protrudes further toward the breakdown voltage structure than the first gate wiring when viewed from above,
The semiconductor device according to claim 1 , further comprising a source connection portion provided above the protruding portion and connected to the source pad. an active portion surrounded by the well region in top view;
a breakdown voltage structure provided outside the well region in top view,
The semiconductor device according to claim 1 , wherein a plurality of the metal layers are arranged at intervals in a direction connecting the active section and the breakdown voltage structure section. an active portion surrounded by the well region in top view;
a breakdown voltage structure provided outside the well region when viewed from above;
a source pad provided above the drift layer and separated from the first gate wiring;
The semiconductor device according to claim 1 , further comprising: a source connection portion that is provided closer to the breakdown voltage structure portion than the metal layer in top view, and that connects the well region to the source pad.