JP7820565B2 - Method and apparatus for task scheduling across heterogeneous chips based on sequence generation - Google Patents

Description

The present invention relates to the field of computer technology, and in particular to a method and apparatus for task scheduling across heterogeneous chips based on sequence generation.

Currently, with the rapid development of computer technology, the application of heterogeneous chips in people's lives is gradually expanding. Here, heterogeneous chips can refer to different types of chips within the same electronic device, or to chips of the same type but with different model numbers within the same electronic device.

In the prior art, a commonly used method for scheduling heterogeneous chips is to treat each chip in the same electronic device or computing cluster as a chip of the same type and manually assign priorities to tasks to be scheduled on the electronic device. When a chip is idle, the highest priority task to be scheduled is selected from the unassigned tasks to be scheduled based on the priority of the tasks to be scheduled and assigned to the chip. The chip can then execute the tasks to be scheduled that have been assigned to it.

However, if each chip is a different type, model number, and processing power, it may be assigned an inappropriate task, causing the chip to take a long time to complete the task, thereby resulting in low utilization of the computing cluster corresponding to the chip.

Based on this, the present invention provides a task scheduling method for heterogeneous chips based on sequence generation.

The present invention provides a method and apparatus for task scheduling across heterogeneous chips based on sequence generation to solve the above-mentioned problems present in the prior art.

The technical ideas adopted in this invention are as follows:

The present invention provides a heterogeneous chip task scheduling method based on sequence generation, which is applied to a scheduling node in a computing cluster, wherein the computing cluster includes the scheduling node and multiple chips, and the computing resources of each chip are not completely the same;
determining, for each of a plurality of tasks to be scheduled, execution time data corresponding to the task to be scheduled based on task information of the task to be scheduled, the execution time data including respective execution times required for the plurality of chips to execute the task to be scheduled;
determining an idle time corresponding to each of the plurality of chips;
generating a scheduling sequence in response to a scheduling request based on task information for each of the plurality of tasks to be scheduled, idle times corresponding to each of the plurality of chips, and execution time data corresponding to each of the plurality of tasks to be scheduled, wherein the scheduling sequence includes a specified number of tasks to be scheduled, a scheduling order corresponding to each of the specified number of tasks to be scheduled, and chips corresponding to each of the specified number of tasks to be scheduled;
and scheduling each task to be scheduled of the specified number of tasks to be scheduled to a corresponding chip based on the scheduling sequence for execution.

Optionally, the step of determining execution time data corresponding to the task to be scheduled based on task information of the task to be scheduled comprises:
determining at least one of a timeout time of the task to be scheduled, a priority of the task to be scheduled, a data length of task data of the task to be scheduled, and a task type of the task to be scheduled as task information of the task to be scheduled;
The method includes a step of combining, for each of the plurality of chips, chip information of the chip with task information of the task to be scheduled, inputting the combined result into a pre-trained prediction model, and obtaining the execution time required for the chip to execute the task to be scheduled, output by the prediction model.

Optionally, generating a scheduling sequence based on task information of each of the plurality of tasks to be scheduled, idle times corresponding to each of the plurality of chips, and execution time data corresponding to each of the plurality of tasks to be scheduled comprises:
determining first and second designated attributes of the plurality of tasks to be scheduled, wherein the first and second designated attributes are selected from execution times of the tasks to be scheduled and task information of the tasks to be scheduled, the task information including at least one of a timeout time, a priority, a data length of task data, and a task type;
determining a target chip based on idle times corresponding to each of the plurality of chips; determining a correlation between the plurality of tasks to be scheduled and the target chip based on a first designated attribute and a second designated attribute corresponding to each of the plurality of tasks to be scheduled; determining a specific number of target tasks to be executed by the target chip as a specific number of initial tasks based on the correlation; and updating the idle times of the target chip for each of the specific number of initial tasks;
For each initial task,
re-determine a target chip based on the idle time of the updated target chip and idle times corresponding to each of the other chips among the plurality of chips until the number of tasks assigned to the plurality of chips reaches the specified number; determine a correlation between the remaining tasks to be scheduled among the plurality of tasks to be scheduled and the target chip based on a first specified attribute and a second specified attribute corresponding to each of the plurality of tasks to be scheduled; re-determine a target task from the remaining tasks to be scheduled based on the correlation, and update the idle time of the target chip;
generating a candidate sequence corresponding to the initial task based on the initial task and all target tasks redetermined after the initial task;
determining the scheduling sequence based on candidate sequences corresponding to each of the specified number of initial tasks.

Optionally, the step of determining a specific number of target tasks to be executed by the target chip as a specific number of initial tasks based on the degree of correlation comprises:
sorting the plurality of tasks to be scheduled based on the correlation degree, and determining the specific number of target tasks as the specific number of initial tasks from the sorting result;
The step of re-determining one target task from the remaining tasks to be scheduled based on the correlation degree includes:
The method includes a step of determining, from the remaining tasks to be scheduled, a task to be scheduled that has the highest correlation with the target chip as the target task based on the correlation.

Optionally, determining the scheduling sequence based on candidate sequences corresponding to each of the specified number of initial tasks comprises:
The method includes a step of determining a candidate sequence that does not include a timeout task from candidate sequences corresponding to each of the specific number of initial tasks, and determining the candidate sequence that does not include a timeout task, from the candidate sequences that do not include the timeout task, as the scheduling sequence.

Optionally, the scheduling node includes: a cluster state detection unit, an information storage unit, a scheduling sequence generation unit, and a task allocation unit;
the cluster state detection unit is used to determine an idle time corresponding to each of the plurality of chips in the computing cluster;
the information storage unit is used for determining and storing task information corresponding to each of the plurality of tasks to be scheduled and execution time data corresponding to each of the plurality of tasks to be scheduled;
the scheduling sequence generation unit is used to generate the scheduling sequence;
The task allocation unit is used to allocate each task to be scheduled among the specified number of tasks to be scheduled to a corresponding chip based on the scheduling sequence.

The present invention provides a task scheduling apparatus for heterogeneous chips based on sequence generation applied to a scheduling node in a computing cluster, wherein the computing cluster includes the scheduling node and a plurality of chips, and the computing resources of each chip are not completely the same;
a task information determination module for determining, for each of a plurality of tasks to be scheduled, execution time data corresponding to the task to be scheduled based on task information of the task to be scheduled, the execution time data including respective execution times required for the plurality of chips to execute the task to be scheduled;
a chip state determination module for determining an idle time corresponding to each of the plurality of chips;
a scheduling sequence generation module for generating a scheduling sequence in response to a scheduling request based on task information of each of the plurality of tasks to be scheduled, idle times corresponding to each of the plurality of chips, and execution time data corresponding to each of the plurality of tasks to be scheduled, wherein the scheduling sequence includes a specified number of tasks to be scheduled, a scheduling order corresponding to each of the specified number of tasks to be scheduled, and chips corresponding to each of the specified number of tasks to be scheduled;
and a scheduling module for scheduling each task to be scheduled among the specified number of tasks to be scheduled to a corresponding chip based on the scheduling sequence, for execution.

The present invention provides a computer-readable storage medium on which a computer program is stored, which, when executed by a processor, implements the above-described heterogeneous chip task scheduling method based on sequence generation.

The present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, which, when executed by the processor, implements the above-described heterogeneous chip task scheduling method based on sequence generation.

At least one of the above technical solutions adopted in the present invention can achieve the following beneficial effects:

For each of the multiple tasks to be scheduled in the scheduling node, the system determines execution time data corresponding to the task based on task information for the task, determines idle times corresponding to each of the multiple chips, and, in response to a scheduling request, generates a scheduling sequence based on the task information for each of the multiple tasks to be scheduled, the idle times corresponding to each of the multiple chips, and the execution time data corresponding to each of the multiple tasks to be scheduled. Based on the scheduling sequence, each task to be scheduled in the scheduling sequence is scheduled to the corresponding chip for execution. In this way, if there is an idle chip in a computing cluster containing heterogeneous chips, appropriate tasks are assigned to the idle chip as much as possible, ensuring task execution efficiency.

The drawings described herein are intended to provide a further understanding of the present invention and constitute a part of this specification. The schematic examples and their descriptions in this specification are intended to help interpret the present invention and are not intended to constitute an undue limitation of the present invention.
FIG. 1 is a schematic diagram illustrating the flow of a heterogeneous chip task scheduling method based on sequence generation provided by the present invention; FIG. 2 is a schematic diagram showing a flow of determining a target task provided by the present invention. FIG. 2 is a schematic diagram illustrating a flow for determining a scheduling sequence provided by the present invention. FIG. 2 is a schematic diagram illustrating the structure of a scheduling node provided by the present invention; 1 is a schematic diagram showing the structure of a heterogeneous chip task scheduling device based on sequence generation provided by the present invention; 1 is a schematic diagram showing the structure of an electronic device for task scheduling of heterogeneous chips based on sequence generation provided by the present invention; FIG.

In order to clarify the objectives, technical solutions, and advantages of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments of the present invention and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, and do not represent all of the embodiments. All other embodiments that can be obtained by those skilled in the art based on the embodiments described in this specification without requiring any creative effort fall within the scope of protection of the present invention.

The technical solutions provided by each embodiment of the present invention are described in detail below with reference to the drawings.

Currently, with the rapid development of computer technology, the application of heterogeneous chips in people's lives is gradually expanding. Here, heterogeneous chips may be chips of different types within the same electronic device, such as a central processing unit (CPU), a graphics processing unit (GPU), or a tensor processing unit (TPU) within the same server. Alternatively, heterogeneous chips may be chips of the same type but with different model numbers within the same electronic device, such as CPUs with different model numbers within the same electronic device.

Different chips require different execution times to process the same task. If the task to be scheduled is a convolution task, the execution time required by the GPU is usually shorter than the execution time required by the CPU. Therefore, one of the technical problems currently being solved is how to process each task to be scheduled based on each chip in the computing cluster after receiving the task to be scheduled, and ensure high utilization of each chip in the processing process.

A commonly used scheduling method is to treat each chip in the same electronic device or computing cluster as the same type of chip and manually assign priorities to tasks to be scheduled in the electronic device. When a chip is idle, the highest priority task to be scheduled is selected from the unassigned tasks to be scheduled based on the priority of the tasks to be scheduled and assigned to the chip. The chip can then execute the tasks to be scheduled that have been assigned to it.

However, if each chip is a different type, model number, and processing power, the chip may be assigned an inappropriate task, causing it to take a long time to complete the task, thereby resulting in low utilization of the computing cluster.

Based on this, the present invention provides a task scheduling method for heterogeneous chips based on sequence generation.

Figure 1 shows a heterogeneous chip task scheduling method based on sequence generation provided by the present invention. The method is applied to a scheduling node in a computing cluster. The computing cluster includes the scheduling node and multiple chips, and the computing resources of each chip are not completely identical. The method includes the following steps:

S100: For each of a plurality of tasks to be scheduled, execution time data corresponding to the task to be scheduled is determined based on task information for the task to be scheduled, and the execution time data includes the execution times required for each of the plurality of chips to execute the task to be scheduled.

Based on the above brief description of the heterogeneous chip task scheduling method based on sequence generation provided by the present invention, the heterogeneous chip task scheduling method based on sequence generation provided by the present invention can be executed by a scheduling node in a computing cluster. The scheduling node may be a server, a terminal, a smart device, an electronic device, etc. The computing cluster includes a scheduling node and multiple chips. That is, the chip task scheduling method provided by the present invention is essentially a method of calling a chip to process a task to be scheduled. The computing cluster may be an electronic device in which multiple chips and a scheduling unit for task scheduling are arranged, or may be a cluster consisting of a scheduling node and a computing node in which multiple chips are arranged.

Specifically, for each task to be scheduled, the execution time of the task to be scheduled on each chip is not exactly the same. Therefore, the scheduling node may determine task information for each task to be scheduled, input the task information into a pre-trained prediction model, and obtain execution time data corresponding to the task to be scheduled output by the prediction model, where the execution time data includes the execution times required for the multiple chips to execute the task to be scheduled. Here, for each task to be scheduled, the task information for the task to be scheduled may be at least one of the timeout time of the task to be scheduled, the priority of the task to be scheduled, the data length of the task data of the task to be scheduled, and the task type of the task to be scheduled.

Of course, to easily determine the correspondence between execution time and chips, when determining execution time, the scheduling node may combine, for each chip, the chip information of that chip with the task information of the task to be scheduled, and use the combined result as input data for the prediction model to obtain the execution time required for that chip to execute the task to be scheduled, output by the prediction model. Then, the execution times required for the multiple chips to execute the task to be scheduled, output by the prediction model, are determined as execution time data corresponding to the task to be scheduled.

In one embodiment, the scheduling node may determine tasks to be scheduled that were executed in the past as historical tasks, and determine chips corresponding to each of the multiple historical tasks and execution times corresponding to each of the multiple historical tasks. Here, for each historical task, the chip corresponding to the historical task is the chip that executes the historical task.

The scheduling node may then determine, for each task to be scheduled, the similarity between the task to be scheduled and each historical task, and, for each historical task, use the similarity between the task to be scheduled and the historical task as the weight of the historical task.

Finally, execution time data corresponding to the task to be scheduled is determined based on the chips corresponding to each of the multiple history tasks, the execution times corresponding to each of the multiple history tasks, and the weights corresponding to each of the multiple history tasks, and the execution time data includes the execution times required for each of the multiple chips to execute the task to be scheduled.

The above two methods are merely examples for determining the execution time data corresponding to the task to be scheduled. The execution time data corresponding to the task to be scheduled may be set based on other methods; the present invention is not limited to these.

S102: Determine the idle time corresponding to each of the multiple chips.

In one or more embodiments provided by the present invention, for each task to be scheduled, the scheduling node may determine an idle time corresponding to each of the plurality of chips, since the task to be scheduled can only be executed when the chip is idle, and may determine a task to be scheduled to be assigned to each of the plurality of chips based on the idle time corresponding to each of the plurality of chips.

Specifically, the scheduling node may determine, for each chip, the current task being executed by the chip and the remaining execution time corresponding to the current task. The scheduling node may then determine an idle time for the chip based on the remaining execution time corresponding to the current task. The idle time is used to indicate that the chip is in an idle state when the idle time is reached.

Here, the idle time may be a specific time, or it may be text that indicates the difference between the idle time and the current time, such as "remaining execution time is 10 seconds."

Of course, the idle time corresponding to each of the above-mentioned multiple chips may be determined after a task is assigned to each chip, may be determined according to a preset time interval, or may be determined when a scheduling request is received. The specific time at which the idle time corresponding to each chip is determined may be set as needed, and the present invention is not limited thereto.

S104: In response to a scheduling request, a scheduling sequence is generated based on task information for each of the plurality of tasks to be scheduled, idle times corresponding to each of the plurality of chips, and execution time data corresponding to each of the plurality of tasks to be scheduled, wherein the scheduling sequence includes a specified number of tasks to be scheduled, a scheduling order corresponding to each of the specified number of tasks to be scheduled, and a chip corresponding to each of the specified number of tasks to be scheduled.

In one or more embodiments provided by the present invention, as described above, the scheduling node may assign appropriate tasks to each chip as much as possible based on the task information for each of the multiple tasks to be scheduled, the idle time corresponding to each of the multiple chips, and the execution time data corresponding to each of the multiple tasks to be scheduled, and generate a scheduling sequence based thereon.

Specifically, the scheduling node can receive a scheduling request, which is used to generate a scheduling sequence, and the scheduling request includes information indicating the specified number.

The scheduling node may therefore analyze the scheduling request to determine the specified number in the scheduling request.

The scheduling node may then determine a specified number of tasks to be scheduled from the plurality of tasks to be scheduled based on task information for each of the plurality of tasks to be scheduled, idle times corresponding to each of the plurality of chips, and execution time data corresponding to each of the plurality of tasks to be scheduled.

Finally, the scheduling node may generate a scheduling sequence based on the determined specified number of tasks to be scheduled.

Here, for example, assume that the task information corresponding to each of the multiple tasks to be scheduled includes a timeout time. The scheduling node may sort each of the multiple tasks to be scheduled based on the timeout time corresponding to each of the multiple tasks to be scheduled, and based on the determined sorting, determine a designated number of tasks to be scheduled that have relatively early timeout times. The scheduling node may then determine the task to be scheduled with the earliest timeout time from the designated number of tasks to be scheduled, and assign the task to be scheduled with the earliest timeout time to the corresponding chip based on the execution time data corresponding to the multiple tasks to be scheduled and the idle time corresponding to each of the multiple chips. The above assignment process may be repeated until all of the designated number of tasks to be scheduled have been assigned to the corresponding chips. Finally, the scheduling node may generate a scheduling sequence based on the chips corresponding to each of the designated number of tasks to be scheduled and the execution order corresponding to each of the designated number of tasks to be scheduled.

S106: Based on the scheduling sequence, each task to be scheduled among the specified number of tasks to be scheduled is scheduled to the corresponding chip for execution.

In one or more embodiments provided by the present invention, after a scheduling sequence is generated, the scheduling node may schedule each task in the scheduling sequence to a chip corresponding to the task for processing.

Specifically, the scheduling sequence includes chips corresponding to each of the specified number of tasks to be scheduled, and a scheduling order corresponding to each of the specified number of tasks to be scheduled.

Therefore, for each chip, based on the scheduling sequence, the scheduling node may assign to the chip a task to be scheduled that corresponds to the chip in the scheduling sequence when the chip is in an idle state.

The chip can receive and process tasks to be scheduled assigned by the scheduling node and submit the processing results.

Furthermore, there may be multiple tasks to be scheduled corresponding to the chip. Therefore, the scheduling node may determine the scheduling order of the tasks to be scheduled corresponding to the chip based on the scheduling sequence. Therefore, the scheduling node may sequentially assign the tasks to be scheduled corresponding to the chip to the chip based on the scheduling order of the tasks to be scheduled corresponding to the chip.

Unlike current methods that assign tasks to each chip in a computing cluster based solely on the priority of the task to be scheduled, resulting in low processing efficiency of the computing cluster, the present invention provides a task scheduling method for heterogeneous chips based on sequence generation, as shown in Figure 1. For each of multiple tasks to be scheduled in a scheduling node, execution time data corresponding to the task to be scheduled is determined, and idle times corresponding to each of multiple chips are determined. In response to a scheduling request, a scheduling sequence is generated based on the task information for each of the multiple tasks to be scheduled, the idle times corresponding to each of the multiple chips, and the execution time data corresponding to each of the multiple tasks to be scheduled. Each task to be scheduled in the scheduling sequence is scheduled to the corresponding chip for execution based on the scheduling sequence. In this way, if there is an idle chip in a computing cluster containing heterogeneous chips, appropriate tasks are assigned to the idle chip as much as possible, ensuring task execution efficiency.

Furthermore, the task information for the tasks to be scheduled may include data corresponding to each of a plurality of task attributes. Therefore, the scheduling node may determine the specified number of tasks to be scheduled based on the task information corresponding to each of the plurality of tasks to be scheduled, the idle time corresponding to each of the plurality of chips, and the execution time data corresponding to each of the plurality of tasks to be scheduled.

Specifically, the scheduling node determines first and second designated attributes of the plurality of tasks to be scheduled, where the first and second designated attributes are selected from the execution times of the tasks to be scheduled and task information of the tasks to be scheduled, and the task information includes at least one of a timeout time, priority, data length of task data, and task type.

The scheduling node may then determine, based on the idle times corresponding to each of the plurality of chips, the chip that will enter the idle state earliest from the plurality of chips, i.e., the chip that can execute the task to be scheduled in the current scheduling process earliest, as the target chip.

The scheduling node may then determine a degree of correlation between the plurality of tasks to be scheduled and the target chip based on a first specified attribute and a second specified attribute corresponding to each of the plurality of tasks to be scheduled, determine a specific number of target tasks to be executed by the target chip as a specific number of initial tasks based on the degree of correlation, and update the idle time of the target chip for each of the specific number of initial tasks.

Then, the scheduling node may generate, for each initial task, a candidate sequence corresponding to the initial task. Specifically, for each initial task, generating a candidate sequence corresponding to the initial task includes: redetermining a target chip based on the idle time of the updated target chip and idle times corresponding to each of the other chips among the plurality of chips until the number of tasks assigned to the plurality of chips reaches the specified number; determining a correlation between the target chip and the remaining tasks to be scheduled among the plurality of tasks to be scheduled based on a first specified attribute and a second specified attribute corresponding to each of the plurality of tasks to be scheduled; redetermining a target task from the remaining tasks to be scheduled based on the correlation and updating the idle time of the target chip; and generating a candidate sequence corresponding to the initial task based on the initial task and all target tasks redetermined after the initial task.

Finally, the scheduling node may determine the scheduling sequence based on the candidate sequences corresponding to each of the specified number of initial tasks.

Here, the step of determining a specific number of target tasks to be executed by the target chip as a specific number of initial tasks based on the degree of correlation specifically includes a step of sorting the plurality of tasks to be scheduled based on the degree of correlation and determining the specific number of target tasks as the specific number of initial tasks from the sorting result, and the step of re-determining one target task from the remaining tasks to be scheduled based on the degree of correlation includes a step of determining, from the remaining tasks to be scheduled, the task to be scheduled that has the highest degree of correlation with the target chip based on the degree of correlation as the target task.

Below, with reference to Figure 2, we will explain in detail an example in which the scheduling node determines one initial task (i.e., the specific number is 1).

2 is a schematic diagram showing the flow of determining a target task provided by the present invention. In the figure, a solid rectangle represents a task assigned to chip x for execution, a dashed rectangle represents a task assigned to chip y for execution, and a bold rectangle represents a task assigned to chip z for execution. Assume that the execution times of different tasks on different chips and the remaining time corresponding to each task are shown in Table 1.

As shown in Table 1, the computing cluster includes three chips: chip x, chip y, and chip z, and the scheduling node has five tasks to be scheduled, namely tasks A, B, C, D, and E. The execution time is the time required for each chip to execute each task, and the remaining time is used to represent the time from the current time until the timeout time of the task.

If chip x is currently idle, chip y's idle time is 3 seconds from now, and chip z's idle time is 5 seconds from now, the scheduling node may determine that the target chip is chip x based on the idle times corresponding to chips x, y, and z.

The scheduling node may then determine the degree of correlation between each task to be scheduled and the target chip based on the first and second specified attributes of the tasks to be scheduled. In the following example, the first specified attribute is the timeout time (expressed as remaining time) and the second specified attribute is the execution time.

The scheduling node may determine N candidate target tasks with the shortest remaining times based on the remaining times corresponding to each of tasks A, B, C, D, and E, where N is greater than or equal to 2 and less than the specified number. If N is 2, the two candidate target tasks are task A and task C.

The scheduling node may then select one target task from the N candidate target tasks as the initial task. Continuing with the example where N is 2, the scheduling node may determine task C, which has the shortest execution time, as the target task based on the execution times of tasks A and C on chip x, and update the idle time of chip x to 8 seconds later with it as the initial task.

The scheduling node may then re-determine target chips based on the idle times corresponding to chips x, y, and z, and re-determine target tasks based on the first and second specified attributes corresponding to the remaining tasks A, B, D, and E, respectively. The above process is repeated until the number of determined target tasks reaches the specified number.

Specifically, in FIG. 2, the scheduling node may determine that chip y is the target chip based on the idle times of chips x, y, and z being 8 seconds, 3 seconds, and 5 seconds, respectively; determine that tasks A and D are candidate target tasks from tasks A, B, D, and E based on the first specified attribute (remaining time); determine that task A is the target task based on the second specified attribute (execution time); and update the idle time of chip y to 7 seconds. In the next iteration, the scheduling node may determine that chip z is the target chip based on the idle times of chips x, y, and z being 8 seconds, 7 seconds, and 5 seconds, respectively; determine that tasks D and B are candidate target tasks from tasks B, D, and E based on the remaining time; determine that task D is the target task based on the execution time; and update the idle time of chip z to 10 seconds. In the next iteration, the scheduling node may determine that chip y is the target chip based on the idle times of chips x, y, and z being 8 seconds, 7 seconds, and 10 seconds later, respectively, determine that task B and task E are candidate target tasks, determine that task E is the target task based on their execution times, and update chip y's idle time to 15 seconds later. Finally, in the final iteration, the scheduling node may determine that chip x is the target chip based on the idle times of chips x, y, and z being 8 seconds, 15 seconds, and 10 seconds later, respectively, determine that task B is the target task, and update chip x's idle time to 17 seconds later.

In the figure, the scheduling node has five tasks to schedule, and the scheduling sequence includes five or more tasks to schedule. Finally, when determining the chip corresponding to task B, the scheduling node determines that the chip corresponding to task B is chip x based on the currently idle chips and the execution time of task B on chips x, y, and z. The scheduling node may then generate a candidate sequence based on the initial task (task C) and all target tasks (tasks A, D, E, and B) redetermined after the initial task. The candidate sequence is then directly determined as the scheduling sequence. The above method for determining the target chips and target tasks is merely illustrative, and other methods may also be used; the present invention is not limited to these.

In addition, to avoid the determined sequence being locally optimal, the scheduling node may determine multiple candidate sequences and determine a scheduling sequence from the candidate sequences. Below, with reference to FIG. 3, a detailed description will be given of an example in which the scheduling node determines two initial tasks (i.e., the specific number is 2). In this case, the scheduling node can determine two candidate sequences.

Figure 3 is a schematic diagram showing the flow for determining a scheduling sequence provided by the present invention. As in Figure 2, solid rectangles represent tasks assigned to chip x for execution, dashed rectangles represent tasks assigned to chip y for execution, and bold rectangles represent tasks assigned to chip z for execution. The computing cluster includes three chips: chip x, chip y, and chip z. The scheduling node has five tasks to be scheduled, namely tasks A, B, C, D, and E. The execution time is the time required for each chip to execute each task, and the remaining time is used to represent the time from the current time until the timeout time of the task.

If chip x is currently idle, chip y's idle time is 3 seconds from now, and chip z's idle time is 5 seconds from now, the scheduling node may determine that the target chip is chip x based on the idle times corresponding to chips x, y, and z.

The scheduling node may then determine the degree of correlation between each task to be scheduled and the target chip based on the first and second specified attributes of the tasks to be scheduled. In the following example, the first specified attribute is the timeout time (expressed as remaining time) and the second specified attribute is the execution time.

The scheduling node may determine N candidate target tasks with the shortest remaining times based on the remaining times corresponding to tasks A, B, C, D, and E. If N is 2, the two candidate target tasks are task A and task C.

Then, the scheduling node may select two target tasks from the N candidate target tasks as initial tasks. Continuing with the example where N is 2, the scheduling node may directly select tasks A and C as target tasks and set them as initial tasks. For task C, the idle time of chip x is updated to 8 seconds later, and for task A, the idle time of chip x is updated to 9 seconds later.

When the scheduling node first determines the target tasks, it determines both task A and task C as initial tasks and, for each initial task, generates a candidate sequence corresponding to the initial task.

The process for determining candidate sequences with task C as the initial task is explained in the related explanation for Figure 2, and will not be explained here. Below, we will explain in detail the process for determining candidate sequences with task A as the initial task, with reference to Figure 3.

As described above, the scheduling node may determine task A as the initial task and update the idle time of chip x to 9 seconds later. Thereafter, the scheduling node may determine chip y to be the target chip based on the idle times of chips x, y, and z being 9 seconds, 3 seconds, and 5 seconds later, respectively. Based on the first specified attribute (remaining time), the scheduling node may determine tasks C and D from tasks B, C, D, and E to be candidate target tasks. Based on the second specified attribute (execution time), the scheduling node may determine task D to be the target task, and update the idle time of chip y to 8 seconds later. In the next iteration, the scheduling node may determine chip z to be the target chip based on the idle times of chips x, y, and z being 9 seconds, 8 seconds, and 5 seconds later, respectively. Based on the remaining time, the scheduling node may determine tasks C and B from tasks B, C, and E to be candidate target tasks. Based on the execution time, the scheduling node may determine task C to be the target task, and update the idle time of chip z to 8 seconds later. In the next iteration, the scheduling node may determine that chip y is the target chip based on the idle times of chips x, y, and z being 9 seconds, 8 seconds, and 8 seconds later, respectively (if the idle times of chips are the same, it may randomly select one target chip), determine that tasks B and E are candidate target tasks, determine that task E is the target task based on its execution time, and update chip y's idle time to 16 seconds later. Finally, in the final iteration, the scheduling node may determine that chip z is the target chip based on the idle times of chips x, y, and z being 9 seconds, 16 seconds, and 8 seconds later, respectively, determine that task B is the target task, and update chip z's idle time to 16 seconds later.

The scheduling node may then generate candidate sequences based on the initial task (task A) and all target tasks (tasks D, C, E, and B) that are re-determined after the initial task.

In the example corresponding to FIG. 3, the scheduling node generates a candidate sequence with task C as the initial task and a candidate sequence with task A as the initial task. The scheduling node may then determine a scheduling sequence based on the two candidate sequences.

Furthermore, for computing clusters, the number of timed-out tasks is one of the important evaluation indicators. Therefore, it is increasingly important to execute tasks before they time out. Therefore, the scheduling node may determine a scheduling sequence from candidate sequences that do not include timed-out tasks.

Specifically, the scheduling node may determine a candidate sequence that does not include a timeout task from the candidate sequences corresponding to each of the specified number of initial tasks.

Next, from the candidate sequences that do not include timeout tasks, the candidate sequence with the shortest execution time is determined as the scheduling sequence.

If the scheduling node determines that a timeout task exists in any of the candidate sequences corresponding to the specified number of initial tasks, it determines the candidate sequence with the fewest number of timeout tasks as the scheduling sequence.

Based on the same idea, the present invention provides a schematic diagram showing the structure of a scheduling node, as shown in Figure 4.

Figure 4 is a schematic diagram showing the structure of a scheduling node provided by the present invention, which includes a cluster state detection unit, an information storage unit, a scheduling sequence generation unit, and a task allocation unit.

Here, the cluster state detection unit is used to determine idle times corresponding to each of the plurality of chips in the computing cluster. The information storage unit is used to determine and store task information corresponding to each of the plurality of tasks to be scheduled and execution time data corresponding to each of the plurality of tasks to be scheduled. The scheduling sequence generation unit is used to generate the scheduling sequence. The task allocation unit is used to allocate each task to be scheduled of the specified number of tasks to be scheduled to a corresponding chip based on the scheduling sequence.

Note that for each task to be scheduled within the scheduling node, the task to be scheduled may be a task that the scheduling node did not schedule in the previous scheduling process. That is, the reception time of the task to be scheduled may be before the scheduling node received the previous scheduling request. The reception time of the task to be scheduled may be between the time the scheduling node received the current scheduling request and the time corresponding to the previously received scheduling request. The specific time at which the scheduling node receives the task to be scheduled may be set as needed, and the present invention is not limited thereto. Of course, for each task to be scheduled, there is a timeout time corresponding to the task to be scheduled. If the current time reaches the timeout time of the task to be scheduled but the task to be scheduled has not yet been executed, the scheduling center may mark the task to be scheduled as a timeout task and send a notification message to the user who sent the timeout task based on the identifier of the timeout task. Here, the notification message is used to inform the user that the task has timed out.

Based on the same idea, the present invention further provides a task scheduling device for heterogeneous chips based on sequence generation, as shown in Figure 5.

Figure 5 shows a task scheduling device for heterogeneous chips based on sequence generation provided by the present invention, which is applied to a scheduling node in a computing cluster, where the computing cluster includes the scheduling node and multiple chips, and the computing resources of each chip are not completely the same.

The task information determination module 200 is used to determine, for each of a plurality of tasks to be scheduled, execution time data corresponding to the task to be scheduled based on the task information of the task to be scheduled, and the execution time data includes the execution times required for the plurality of chips to execute the task to be scheduled.

The chip state determination module 202 is used to determine the idle time corresponding to each of the plurality of chips.

The sequence generation module 204 is used to generate a scheduling sequence in response to a scheduling request based on task information for each of the plurality of tasks to be scheduled, idle times corresponding to each of the plurality of chips, and execution time data corresponding to each of the plurality of tasks to be scheduled, wherein the scheduling sequence includes a specified number of tasks to be scheduled, a scheduling order corresponding to each of the specified number of tasks to be scheduled, and chips corresponding to each of the specified number of tasks to be scheduled.

The scheduling module 206 is used to schedule and execute each task among the specified number of tasks to be scheduled on the corresponding chip based on the scheduling sequence.

Optionally, the task information determination module 200 specifically:
determining at least one of a timeout time of the task to be scheduled, a priority of the task to be scheduled, a data length of task data of the task to be scheduled, and a task type of the task to be scheduled as task information of the task to be scheduled;
For each of the plurality of chips, the chip information of the chip is combined with the task information of the task to be scheduled, and the combined result is input into a pre-trained prediction model, which is used to obtain the execution time required for the chip to execute the task to be scheduled, output by the prediction model.

Optionally, the sequence generation module 204 specifically:
determining first and second designated attributes of the plurality of tasks to be scheduled, the first and second designated attributes being selected from execution times of the tasks to be scheduled and task information of the tasks to be scheduled, the task information including at least one of a timeout time, a priority, a data length of task data, and a task type;
determining a target chip based on idle times corresponding to each of the plurality of chips; determining a correlation between the plurality of tasks to be scheduled and the target chip based on a first designated attribute and a second designated attribute corresponding to each of the plurality of tasks to be scheduled; determining a specific number of target tasks to be executed by the target chip as a specific number of initial tasks based on the correlation; and updating the idle times of the target chip for each of the specific number of initial tasks;
For each initial task,
re-determine a target chip based on the idle time of the updated target chip and idle times corresponding to each of the other chips among the plurality of chips until the number of tasks assigned to the plurality of chips reaches the specified number; determine a correlation between the remaining tasks to be scheduled among the plurality of tasks to be scheduled and the target chip based on a first specified attribute and a second specified attribute corresponding to each of the plurality of tasks to be scheduled; re-determine a target task from the remaining tasks to be scheduled based on the correlation, and update the idle time of the target chip;
generating a candidate sequence corresponding to the initial task based on the initial task and all target tasks redetermined after the initial task;
The scheduling sequence is determined based on candidate sequences corresponding to each of the specified number of initial tasks.

Optionally, the sequence generation module 204 specifically:
sorting the plurality of tasks to be scheduled based on the correlation degree, and determining the specific number of target tasks as the specific number of initial tasks from the sorting result;
Based on the correlation, a task to be scheduled that has the highest correlation with the target chip is determined as the target task from the remaining tasks to be scheduled.

Optionally, the sequence generation module 204 specifically:
From the candidate sequences corresponding to each of the specified number of initial tasks, a candidate sequence that does not include a timeout task is determined, and from the candidate sequences that do not include a timeout task, the candidate sequence that has the shortest execution time is used to determine as the scheduling sequence.

Optionally, the scheduling node includes: a cluster state detection unit, an information storage unit, a scheduling sequence generation unit, and a task allocation unit;
the cluster state detection unit is used to determine an idle time corresponding to each of the plurality of chips in the computing cluster;
the information storage unit is used for determining and storing task information corresponding to each of the plurality of tasks to be scheduled and execution time data corresponding to each of the plurality of tasks to be scheduled;
the scheduling sequence generation unit is used to generate the scheduling sequence;
The task allocation unit is used to allocate each task to be scheduled among the specified number of tasks to be scheduled to a corresponding chip based on the scheduling sequence.

The present invention further provides a computer-readable storage medium having a computer program stored thereon, which can be used to execute the task scheduling method for heterogeneous chips based on the sequence generation provided by FIG. 1 above.

The present invention further provides a diagram showing the structure of an electronic device, as shown in Figure 6. As shown in Figure 6, at the hardware level, the electronic device includes a processor, an internal bus, a network interface, internal memory, and non-volatile memory, and may also include hardware necessary for other operations. The processor loads the corresponding computer program from the non-volatile memory into the internal memory and executes it, thereby realizing the heterogeneous chip task scheduling method based on sequence generation described in Figure 1 above. Of course, in addition to software realization, the present invention does not exclude other realization methods, such as logical devices or a combination of hardware and software. In other words, the execution entity of the following processing process is not limited to each logical unit, but may also be hardware or a logical device.

In the 1990s, technological improvements could be clearly divided into hardware improvements (such as improvements to circuit structures like diodes, transistors, and switches) and software improvements (such as improvements to method flow). However, with technological advances, many current method flow improvements can be considered direct improvements to hardware circuit structures. Designers often obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that method flow improvements cannot be realized using physical hardware modules. For example, programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs)) are such integrated circuits, whose logical functions are determined by user programming of the device. Instead of chip manufacturers designing and manufacturing dedicated integrated circuit chips, designers program and "integrate" digital systems onto a single PLD. Nowadays, instead of handcrafting integrated circuit chips, this programming is mostly achieved using software called a "logic compiler," which is similar to a software compiler used when writing a program. In order to compile the original code, it must be written in a specific programming language, called a Hardware Description Language (HDL). There is not just one type of HDL; there are several: ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, and JHDL (Java Hardware Description Language). There are many types of hardware description languages, including RHDL (Ruby Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language), but the most commonly used currently are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. It will be clear to those skilled in the art that by simply logically programming a method flow in one of the above hardware description languages and programming it into an integrated circuit, a hardware circuit that implements the logical method flow can be easily obtained.

The controller may be implemented in any suitable manner, for example, a microprocessor or processor and a computer-readable storage medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, and may take the form of logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, microcontrollers such as the ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller may also be implemented as part of the control logic of the memory. It will also be apparent to those skilled in the art that in addition to implementing a controller purely with computer-readable program code, it is entirely possible to logically program method steps to cause a controller to perform the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, embedded microcontrollers, and the like. Therefore, such a controller may be considered a hardware component, and the devices included therein for implementing various functions may also be considered structures within the hardware component. Alternatively, the devices for implementing various functions may also be considered to be software modules that implement a method, or structures within the hardware component.

The systems, devices, modules, or units described in the above embodiments may be specifically realized by a computer chip, entity, or product having some functionality. A typical realizing device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a mobile phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet, a wearable device, or any combination of these devices.

For ease of explanation, the above device will be described by dividing it into various units according to their functions. Of course, when implementing the present invention, it is also possible to realize the functions of each unit using the same or multiple pieces of software and/or hardware.

As will be appreciated by those skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an embodiment consisting entirely of hardware, an embodiment consisting entirely of software, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product embodied in one or more computer-usable storage media (including, but not limited to, magnetic disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

The present invention will be described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and/or block in the flowcharts and/or block diagrams, and combinations of flows and/or blocks in the flowcharts and/or block diagrams, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, whereby the instructions, executed by the processor of the computer or other programmable data processing device, generate an apparatus for implementing the functions specified in one or more flows in the flowcharts and/or one or more blocks in the block diagrams.

These computer program instructions may be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, resulting in an article of manufacture that includes an instruction apparatus that implements the functions specified in one or more flows of the flowcharts and/or one or more blocks of the block diagrams, as a result of the instructions stored in the computer-readable memory.

These computer program instructions may be loaded into a computer or other programmable data processing device, and a series of operational steps executed on the computer or other programmable device to generate computer-implemented processes, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more flows of the flowcharts and/or one or more blocks of the block diagrams.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

Memory may include computer-readable storage media in the form of volatile memory, random access memory (RAM), and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is one example of a computer-readable storage medium.

Computer-readable storage media include non-volatile and volatile media, removable and non-removable media, and may implement information storage using any method or technology. Information may be computer-readable instructions, data structures, program modules, or other data. Computer storage media may be Phase Change Memory (PRAM), Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Flash Memory or other memory technologies, Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disk (DV), or other memory technologies. This includes, but is not limited to, digital Versatile Disc (DVD) or other optical storage, magnetic cassette tape, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device. As defined herein, computer-readable storage media does not include transient computer-readable storage media, such as modulated data signals and carriers.

Additionally, the terms "comprise," "contain," or any other variation thereof, are intended to include a non-exclusive inclusion, whereby a process, method, article, or device that includes a set of elements not only includes those elements, but also includes other elements not expressly listed, or includes the inherent elements of such process, method, article, or device. Absent more limitations, elements qualified by the phrase "comprise..." do not exclude the presence of additional identical elements in a process, method, article, or device that includes said elements.

As will be appreciated by those skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an embodiment consisting entirely of hardware, an embodiment consisting entirely of software, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product embodied in one or more computer-usable storage media (including, but not limited to, magnetic disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

The invention may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media, including storage devices.

Each embodiment of the present invention will be described in a step-by-step manner, and the same or similar parts between the embodiments may be referred to. The emphasis in the description of each embodiment will be on the differences from other embodiments. In particular, the system embodiments will be described briefly, as they are essentially similar to the method embodiments, and relevant parts may be referred to in the description of some of the method embodiments.

The above is merely an example of the present invention and is not intended to limit the present invention. Those skilled in the art will appreciate that the present invention may undergo various modifications and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are intended to be included within the scope of the claims of the present invention.

Claims (8)

A task scheduling method for heterogeneous chips based on sequence generation executed by a scheduling node in a computing cluster, wherein the computing cluster includes the scheduling node and multiple chips, and the computing resources of each chip are not completely the same;
determining, for each of a plurality of tasks to be scheduled, execution time data corresponding to the task to be scheduled based on task information of the task to be scheduled, the execution time data including respective execution times required for the plurality of chips to execute the task to be scheduled;
determining an idle time corresponding to each of the plurality of chips;
generating a scheduling sequence in response to a scheduling request based on task information for each of the plurality of tasks to be scheduled, idle times corresponding to each of the plurality of chips, and execution time data corresponding to each of the plurality of tasks to be scheduled, wherein the scheduling sequence includes a specified number of tasks to be scheduled, a scheduling order corresponding to each of the specified number of tasks to be scheduled, and chips corresponding to each of the specified number of tasks to be scheduled;
scheduling and executing each task to be scheduled among the designated number of tasks to be scheduled on a corresponding chip based on the scheduling sequence;
generating a scheduling sequence based on task information of each of the plurality of tasks to be scheduled, idle times corresponding to each of the plurality of chips, and execution time data corresponding to each of the plurality of tasks to be scheduled,
determining first and second designated attributes of the plurality of tasks to be scheduled, wherein the first and second designated attributes are selected from execution times of the tasks to be scheduled and task information of the tasks to be scheduled, the task information including at least one of a timeout time, a priority, a data length of task data, and a task type;
determining a target chip based on idle times corresponding to each of the plurality of chips; determining a correlation between the plurality of tasks to be scheduled and the target chip based on a first designated attribute and a second designated attribute corresponding to each of the plurality of tasks to be scheduled; determining a specific number of target tasks to be executed by the target chip as a specific number of initial tasks based on the correlation; and updating the idle times of the target chip for each of the specific number of initial tasks;
For each initial task,
re-determine a target chip based on the idle time of the updated target chip and idle times corresponding to each of the other chips among the plurality of chips until the number of tasks assigned to the plurality of chips reaches the specified number; determine a correlation between the remaining tasks to be scheduled among the plurality of tasks to be scheduled and the target chip based on a first specified attribute and a second specified attribute corresponding to each of the plurality of tasks to be scheduled; re-determine a target task from the remaining tasks to be scheduled based on the correlation, and update the idle time of the target chip;
generating a candidate sequence corresponding to the initial task based on the initial task and all target tasks redetermined after the initial task;
determining the scheduling sequence based on candidate sequences corresponding to each of the specified number of initial tasks;
A heterogeneous chip task scheduling method based on sequence generation, characterized in that: The step of determining execution time data corresponding to the task to be scheduled based on task information of the task to be scheduled includes:
determining at least one of a timeout time of the task to be scheduled, a priority of the task to be scheduled, a data length of task data of the task to be scheduled, and a task type of the task to be scheduled as task information of the task to be scheduled;
For each of the plurality of chips, combining chip information of the chip with task information of the task to be scheduled, inputting the combined result into a pre-trained prediction model, and obtaining an execution time required for the chip to execute the task to be scheduled, output by the prediction model.
2. The method of claim 1 . determining a specific number of target tasks to be executed by the target chip as a specific number of initial tasks based on the correlation degree,
sorting the plurality of tasks to be scheduled based on the correlation degree, and determining the specific number of target tasks as the specific number of initial tasks from the sorting result;
The step of re-determining one target task from the remaining tasks to be scheduled based on the correlation degree includes:
determining, as the target task, a task to be scheduled that has the highest correlation with the target chip from among the remaining tasks to be scheduled based on the correlation;
2. The method of claim 1 . determining the scheduling sequence based on candidate sequences corresponding to each of the specified number of initial tasks,
determining a candidate sequence that does not include a timeout task from candidate sequences corresponding to each of the specific number of initial tasks, and determining a candidate sequence that has the shortest execution time from the candidate sequences that do not include a timeout task as the scheduling sequence;
2. The method of claim 1 . The scheduling node includes a cluster state detection unit, an information storage unit, a scheduling sequence generation unit, and a task allocation unit;
the cluster state detection unit is used to determine an idle time corresponding to each of the plurality of chips in the computing cluster;
the information storage unit is used for determining and storing task information corresponding to each of the plurality of tasks to be scheduled and execution time data corresponding to each of the plurality of tasks to be scheduled;
the scheduling sequence generation unit is used to generate the scheduling sequence;
the task allocation unit is used to allocate each task to be scheduled among the specified number of tasks to be scheduled to a corresponding chip based on the scheduling sequence;
2. The method of claim 1 . A task scheduling apparatus for heterogeneous chips based on sequence generation applied to a scheduling node in a computing cluster, wherein the computing cluster includes the scheduling node and a plurality of chips, and the computing resources of each chip are not completely the same;
a task information determination module for determining, for each of a plurality of tasks to be scheduled, execution time data corresponding to the task to be scheduled based on task information of the task to be scheduled, the execution time data including respective execution times required for the plurality of chips to execute the task to be scheduled;
a chip state determination module for determining an idle time corresponding to each of the plurality of chips;
a scheduling sequence generation module for generating a scheduling sequence in response to a scheduling request based on task information of each of the plurality of tasks to be scheduled, idle times corresponding to each of the plurality of chips, and execution time data corresponding to each of the plurality of tasks to be scheduled, wherein the scheduling sequence includes a specified number of tasks to be scheduled, a scheduling order corresponding to each of the specified number of tasks to be scheduled, and chips corresponding to each of the specified number of tasks to be scheduled;
a scheduling module for scheduling and executing each task to be scheduled among the specified number of tasks to be scheduled on a corresponding chip based on the scheduling sequence;
The sequence generation module specifically includes:
determining first and second designated attributes of the plurality of tasks to be scheduled, the first and second designated attributes being selected from execution times of the tasks to be scheduled and task information of the tasks to be scheduled, the task information including at least one of a timeout time, a priority, a data length of task data, and a task type;
determining a target chip based on idle times corresponding to each of the plurality of chips; determining a correlation between the plurality of tasks to be scheduled and the target chip based on a first designated attribute and a second designated attribute corresponding to each of the plurality of tasks to be scheduled; determining a specific number of target tasks to be executed by the target chip as a specific number of initial tasks based on the correlation; and updating the idle times of the target chip for each of the specific number of initial tasks;
For each initial task,
re-determine a target chip based on the idle time of the updated target chip and idle times corresponding to each of the other chips among the plurality of chips until the number of tasks assigned to the plurality of chips reaches the specified number; determine a correlation between the remaining tasks to be scheduled among the plurality of tasks to be scheduled and the target chip based on a first specified attribute and a second specified attribute corresponding to each of the plurality of tasks to be scheduled; re-determine a target task from the remaining tasks to be scheduled based on the correlation, and update the idle time of the target chip;
generating a candidate sequence corresponding to the initial task based on the initial task and all target tasks redetermined after the initial task;
used to determine the scheduling sequence based on candidate sequences corresponding to each of the specified number of initial tasks .
A task scheduling device for heterogeneous chips based on sequence generation, characterized in that: A computer-readable storage medium having stored thereon a computer program, the computer program being executed by a processor to perform the method of any one of claims 1 to 5.
A computer-readable storage medium comprising: An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the electronic device performing the method of any one of claims 1 to 5 when the processor executes the computer program.
An electronic device characterized by: