JP7822227B2 - Data transfer device and data transfer system including the same - Google Patents

Description

This disclosure relates to a data transfer device and a data transfer system equipped with the same.

In a computer system, a CPU (Central Processing Unit) and multiple peripheral circuits are connected by a system bus, and data is transferred between each component. If the CPU were to directly operate the system bus to perform the data transfer, calculations would not be possible during that time, so data transfers using DMA (Direct Memory Access), which does not involve the CPU, are used.

For example, Japanese Patent Application Laid-Open Publication No. 2007-183692 (Patent Document 1) discloses a technology that reduces the system bus occupancy rate and enables efficient data transfer by providing a dedicated line for making DMA transfer requests in addition to the system bus on which DMA transfers are performed.

JP 2007-183692 A

In conventional DMA data transfers, when multiple components simultaneously request data transfers, the data transfers are often performed based on predefined priorities. For example, data transfers with a first peripheral circuit are performed with high priority, and data transfers with a second peripheral circuit are performed with low priority.

However, with this data transfer method, the priority of data transfer is fixed, so if high-priority data and low-priority data are transferred together, the data cannot be transferred with the appropriate priority.

For example, even if a first peripheral circuit wishes to transfer low-priority data, it may end up being transferred as high-priority data, which could interfere with the data transfer of a second peripheral circuit. Furthermore, if a first peripheral circuit wishes to transfer high-priority data, and another component is transferring data with an even higher priority, the data transfer of the first peripheral circuit may be delayed longer than expected.

Therefore, the primary objective of this disclosure is to provide a data transfer device and a data transfer system equipped with the same that are capable of properly transferring data even when high-priority data and low-priority data are mixed.

The data transfer device disclosed herein is a data transfer device that transfers data in accordance with multiple transfer requests. Each transfer request includes first information related to the required transfer time to execute the transfer request, and second information indicating the allowed transfer time, which is the maximum time allowed for completing the data transfer for that transfer request. This data transfer device includes a calculation unit that sets the order in which the multiple transfer requests will be executed based on the first and second information for each transfer request, and a transfer control circuit that executes the multiple transfer requests in the order set by the calculation unit.

The data transfer device disclosed herein sets the order in which transfer requests are executed for each transfer request, allowing for appropriate data transfer even when high-priority data and low-priority data are mixed.

FIG. 1 is a block diagram showing a configuration of a data transfer system according to a first embodiment. FIG. 2 is a diagram illustrating the operation of the data transfer system shown in FIG. 1. FIG. 4 is another diagram illustrating the operation of the data transfer system shown in FIG. 1. FIG. 4 is yet another diagram illustrating the operation of the data transfer system shown in FIG. 1. FIG. 4 is yet another diagram illustrating the operation of the data transfer system shown in FIG. 6 is a flowchart showing part of the operation of the transfer control circuit shown in FIGS. 2 to 5. 7 is a flowchart showing the remaining part of the operation of the transfer control circuit shown in FIG. 6. 6 is a flowchart showing the operation of an individual counter included in the transfer time counter shown in FIGS. 2 to 5 . 6 is a flowchart showing part of the operation of the transfer time calculation unit shown in FIGS. 2 to 5 . 10 is a flowchart showing the remaining part of the operation of the required transfer time calculation unit shown in FIG. 9 . 10 is a flowchart showing a part of the operation of a modification of the first embodiment. 12 is a flowchart showing the remaining part of the operation of the modified example shown in FIG. 11 . FIG. 10 is a block diagram showing a configuration of a data transfer system according to a second embodiment. 14 is a flowchart showing a main part of the operation of the transfer time calculation unit shown in FIG. 13 . FIG. 11 is a block diagram showing a configuration of a data transfer system according to a third embodiment. 16 is a flowchart showing a main part of the operation of the transfer time calculation unit shown in FIG. 15 .

Embodiment 1.
1 is a block diagram showing the configuration of a data transfer system according to the first embodiment. In this data transfer system, when each component wishes to transfer a mixture of high-priority data and low-priority data, the data with the highest priority is transferred first. In FIG. 1, this data transfer system includes a DMA unit 1, a system bus 2, a RAM (Random Access Memory) 3, peripheral circuits 4 and 5, and an MPU (Micro Processor Unit) 6.

DMA unit 1 (data transfer device) is a circuit used when transferring data from one component to another. Peripheral circuits 4 and 5 are blocks that output data transfer requests to DMA unit 1. Examples of peripheral circuits 4 and 5 include a GPU (Graphics Processing Unit), FPGA (Field Programmable Gate Array), and IF (Interface) for communicating with the outside world. MPU 6 includes a CPU and performs various calculations and controls. In this data transfer system, data is transferred by DMA without going through the CPU of MPU 6.

In a typical data transfer system, a data transfer request includes a source address, a destination address, and a transfer data capacity. The transfer data capacity constitutes one example of first information related to the required transfer time TR. In this first embodiment, the data transfer request further includes second information indicating the allowable transfer time TA. The required transfer time TR and the allowable transfer time TA will be described later.

RAM 3 is memory shared by DMA unit 1, peripheral circuit 4, peripheral circuit 5, and MPU 6. RAM 3 writes and reads data in response to a data transfer request from DMA unit 1. In this embodiment 1, peripheral circuits 4 and 5 send data transfer requests to DMA unit 1 via system bus 2, and DMA unit 1 transfers the data to RAM 3.

The DMA unit 1 includes an allowable transfer time holding unit 11, a data buffer 12, a BUS/IF (Interface) 13, a required transfer time calculation unit 14, a transfer control circuit 15, a transfer time counter 16, a destination address pointer 17, and a source address pointer 18. Hereinafter, the allowable transfer time holding unit 11 and the required transfer time calculation unit 14 may be simply referred to as the "holding unit 11" and the "calculation unit 14," respectively.

The data buffer 12 temporarily stores data read from the data source by the transfer control circuit 15. Furthermore, when a write request is output from the transfer control circuit 15, the data buffer 12 writes the data stored in the data buffer 12 to the transfer destination.

BUS/IF 13 is a block that aligns the bus protocol between the system bus 2 and the data buffer 12. In accordance with the system bus 2 standard, BUS/IF 13 exchanges signals in accordance with the rules required for transfer, such as transfer method and data capacity.

The holding unit 11 holds the allowable transfer time TA for transfer from the transfer request source and outputs this allowable transfer time TA to the calculation unit 14. The calculation unit 14 calculates the required transfer time TR. The required transfer time TR is the time required from when the DMA unit 1 receives a transfer request from the transfer request source until the DMA unit 1 sends a completion notification to the transfer request source.

The calculation unit 14 calculates the required transfer time TR based on the calculation request, transfer data capacity, transfer request, and current transfer order sent from the transfer control circuit 15, as well as information on the bus protocol (bus bit width, burst length, transfer interval, etc.). The method for calculating the required transfer time TR will be described later.

The calculation unit 14 also receives the allowable transfer time TA for each data transfer request from the holding unit 11 and determines whether the transfer will be completed within the allowable transfer time TA. If the required transfer time TR exceeds the allowable transfer time TA, the data transfer cannot be completed within the requested allowable transfer time TA, and an error is notified to the transfer request source (peripheral circuits 4 and 5 in this example).

In addition, regardless of the relationship between the required transfer time TR and the allowable transfer time TA, the calculation unit 14 responds to the transfer control circuit 15 with the transfer order determined from the calculation result of the required transfer time TR as the new transfer order. In other words, the calculation unit 14 reconsiders the appropriate transfer order based on the current transfer order and the recalculation result of the required transfer time TR, and responds with the new transfer order.

If a second or third transfer request is input to the DMA unit 1 while a transfer is in progress, the calculation unit 14 recalculates the required transfer time TR. Based on the result, the calculation unit 14 determines in what order the newly input transfer requests should be inserted into the current transfer order, and notifies the transfer control circuit 15 of the new transfer order determined as a result. The detailed operation of the calculation unit 14 will be described later.

When a transfer request is made to the DMA unit 1 from the peripheral circuits 4 and 5, the transfer control circuit 15 acquires the right to use the system bus 2 and outputs the data to be transferred from the data buffer 12 to the RAM 3 and the peripheral circuits 4 and 5.

In addition, the transfer control circuit 15 outputs a start command to the transfer time counter 16 when it receives a transfer request from the peripheral circuits 4, 5, etc. The transfer control circuit 15 also outputs a calculation command for the required transfer time TR to the calculation unit 14, as well as the currently held transfer order. The transfer control circuit 15 also holds the transfer order received from the calculation unit 14.

When a transfer request arrives from a peripheral component of the DMA unit 1, the transfer time counter 16 (timekeeping unit) measures the time that has elapsed since that request. This elapsed time corresponds to the "processed time" described below, and is used to reference the remaining transfer time, which is the value obtained by subtracting the time measured by the counter from the first transfer allowable time TA, when a second data transfer request arrives. When multiple transfer requests arrive, the transfer time counter 16 calculates the remaining transfer time for each, and therefore has a counter for the maximum number of transfer requests that can occur during a single transfer.

The destination address pointer 17 indicates the address of the transfer destination. The source address pointer 18 indicates the address of the transfer source. The transfer control circuit 15 transfers data from the source address indicated by the source address pointer 18 to the destination address indicated by the destination address pointer 17.

The DMA unit 1 in this first embodiment is characterized by receiving an additional constraint, the transfer allowable time TA, from the transfer request source (peripheral circuits 4 and 5 in this example), which is not present in general DMA, allowing it to flexibly determine the priority of data transfers and transfer data accordingly.

Here, the allowed transfer time TA is the maximum allowable time from when a transfer request source requests a data transfer until the transfer request source receives notification that the data transfer has completed. In other words, the allowed transfer time TA is the time limit within which the data transfer requested by the transfer request source must be completed. Each transfer request source sets a short allowed transfer time TA for high-priority data transfer requests and a long allowed transfer time TA for low-priority data transfer requests.

The DMA unit 1 prioritizes the order in which data transfer requests should be executed, based on the allowable transfer time TA and related information (such as the required transfer time TR, described below), so that the data transfer for each data transfer request is completed within the allowable transfer time TA.

If the transfer cannot be completed within the allowed time TA, the DMA unit 1 notifies the transfer request source that the transfer cannot be completed in time as an error. By adopting this allowed transfer time TA, the DMA unit 1 can determine the highest priority transfer request from multiple data transfer requests, and can prioritize the highest priority transfer even when data transfers with mixed priorities are performed.

Figure 2 shows the data transfer operation of this data transfer system. In Figure 2, we consider a case where there are data transfer requests from two transfer request sources, RS1 (peripheral circuit 4 in this example) and RS2 (peripheral circuit 5 in this example), and the transfer data is read from transfer request source RS1 and transfer request source RS2 and written to the same RAM 3. When actually using this data transfer system, the data transfer request source, transfer source (source address), transfer destination (destination address), and the number and type of components are not important.

When a data transfer request R1 is sent from data transfer request source RS1 to transfer control circuit 15, transfer control circuit 15 first outputs a start command to counter C1 in transfer time counter 16, and counter C1 counts the time from the time data transfer request R1 was accepted. This transfer time counter 16 and transfer control circuit 15 are required to perform calculations to determine the priority of transfer requests R1 and R2 when a second data transfer request R2 occurs.

At the same time, the transfer control circuit 15 writes the allowable transfer time TA1 to the holding unit 11. The holding unit 11 notifies the calculation unit 14 of the allowable transfer time TA1. The transfer control circuit 15 then requests the calculation unit 14 to calculate the required transfer time TR1. This required transfer time TR1 is the time required from receiving the data transfer request R1 from the transfer request source RS1 until the data transfer to the transfer destination (RAM3) is completed.

The transfer time TR1 is calculated from the transfer data capacity, system frequency, and bus protocol (bus bit width, burst length, transfer interval, etc.). The transfer data capacity is the size of data D1 specified by transfer request source RS1. The system frequency is the clock frequency that operates DMA unit 1 itself, and is determined by the system design. The burst length is the data size that can be transferred in one transaction (read and write), as determined by the bus protocol. The transfer interval is the time that must be left between the end of the previous transaction and the start of the current transaction when multiple transactions are issued consecutively.

The transfer rate (bits/sec) per unit time of data transfer is calculated from the system frequency and bus protocol. The required transfer time TR is then calculated by dividing the transfer data capacity (bits) by the transfer rate. The calculation unit 14 (Figure 1) calculates the required transfer time TR from the data transfer request information in this way, and notifies the transfer control circuit 15 of the transfer order determined from the result.

Here, if the transfer rate is Rt [bit/sec], the bus data bit width is Wb, the burst length is Lb, the number of clocks required per burst is Nc [clk], the system frequency is Fs [clk/sec], and the transfer interval is Dt [sec], then Rt = (Wb x Lb) / [(Nc/Fs) + Dt]. Furthermore, if the time required for transfer is TR [sec] and the transfer data capacity is Dc [bit], then TR = Dc/Rt.

The calculation unit 14 compares the calculated required transfer time TR1 with the allowable transfer time TA1 notified by the holding unit 11, and if TR1≦TA1, it responds with the transfer order to the transfer control circuit 15. Since there is only one transfer request R1 at this point, the transfer order sent from the calculation unit 14 to the transfer control circuit 15 indicates that data D1 for which transfer request R1 was made will be transferred first. The transfer control circuit 15 then reads data D1 from the data transfer source (transfer request source RS1 in this example) and stores that data D1 in the data buffer 12. Note that the operation when TR1>TA1 will be described later (Figure 4).

Next, the transfer control circuit 15 starts the transfer process from the data buffer 12 to the transfer destination (RAM3 in this example). Specifically, the transfer control circuit 15 receives the transfer data from the data buffer 12 in the amount that can be transferred at one time, and starts writing it to RAM3. The amount of data that can be transferred at one time depends on the bus protocol.

Regarding the operation of reading transfer data D1 from data transfer request source RS1 and storing it in data buffer 12, and the operation of writing it to RAM 3, in Figure 2, data D1 is written to RAM 3 after all data D1 has been written to data buffer 12, but if the bus protocol or the like has independent data read and write channels, the two operations may be performed in parallel.

Next, suppose that a second data transfer request R2 is issued from data transfer request source RS2 while data transfer based on data transfer request R1 is in progress. In this case, transfer control circuit 15 temporarily stops writing data to RAM3 and suspends the data transfer. At the same time, transfer control circuit 15 activates counter C2 in transfer time counter 16 and writes the allowed transfer time TA2 to holding unit 11.

The transfer control circuit 15 then commands the calculation unit 14 to calculate the required transfer times TR1 and TR2. In this case, the required transfer time TR1 is recalculated. At this point, a certain amount of data has already been transferred in response to transfer request R1, so the calculation unit 14 replaces the transfer data capacity in the calculation formula with the remaining amount of data that must be transferred (remaining data amount). The remaining amount of data D1 is notified to the calculation unit 14 by the data buffer 12.

At the same time, the transfer control circuit 15 outputs a count value output command to counters C1 and C2 in the transfer time counter 16 to output the times they have measured as processed times TP1 and TP2 to the calculation unit 14, so that the calculation unit 14 can calculate a new transfer order according to the priority from among the multiple transfer requests. The holding unit 11 also notifies the calculation unit 14 of the allowed transfer times TA1 and TA2.

Here, consider a case where, as a result of calculation by the calculation unit 14, the following condition (1) is false and the following condition (2) is true.
Condition (1): TR1+TR2≦TA2-TP2
Condition (2): TR1+TR2≦TA1-TP1

In this case, if condition (1) is false, it means that the remaining required time (TR1 + TR2) is greater than the remaining allowable time (TA2 - TP2), and therefore data D2 must be transferred before data D1 in order to complete the transfer of data D2 within the remaining allowable time (TA2 - TP2).

Furthermore, if condition (2) is true, it means that the remaining required time (TR1 + TR2) is less than or equal to the remaining allowable time (TA1 - TP1), and that the order in which data D2 and data D1 are transferred can be either, as long as the transfer of data D1 is completed within the remaining allowable time (TA1 - TP1).

Therefore, if condition (1) is false and condition (2) is true, the calculation unit 14 determines that data D2 needs to be transferred before data D1, and sends information indicating this to the transfer control circuit 15 as the transfer order.

In other words, the calculation unit 14 sets the order in which transfer requests R1 and R2 are executed so that the sum of the recalculated required transfer time TR1 and the waiting time TR2 required to execute another transfer request R2 scheduled before the start of transfer request R1 falls within the allowable transfer time (TA1-TP1) for transfer request R1.

Further details on which transfer request is given priority based on the required transfer time TR will be discussed later. If condition (1) is false and condition (2) is true, the transfer control circuit 15 receives the transfer order (information that data D2 will be transferred with priority over data D1) from the calculation unit 14, then reads data D2 from the transfer request source RS2 and writes that data D2 to RAM3. At this time, the transfer control circuit 15 writes data D2 read from transfer request source RS2 to data buffer 12, just like data D1, and writes data D2 read from data buffer 12 to RAM3.

When writing of data D2 to RAM3 is complete, the transfer control circuit 15 notifies the data transfer request source RS2 that the data transfer is complete. At the same time, the transfer control circuit 15 outputs a command to the transfer time counter 16 to stop counter C2.

Then, the transfer control circuit 15 resumes the interrupted writing of data D1. When the transfer control circuit 15 completes writing of data D1 and outputs a data transfer completion notification to the data transfer request source RS1, it simultaneously outputs an initialization command to counter C1 in the transfer time counter 16.

Figure 3 is another diagram showing the data transfer operation of this data transfer system. Figure 3 shows the operation when, when data transfer request R2 occurs while data transfer request R1 is being executed, transfer request R1 is given priority and transfer request R2 is executed next. This operation is the same as the operation shown in Figure 2 until data transfer request R2 occurs, but differs from the operation shown in Figure 2 in that the calculation unit 14 then determines that transfer request R1 should be executed with priority.

That is, when a transfer request R2 is sent from data transfer request source RS2 to transfer control circuit 15, transfer control circuit 15 outputs a command to calculation unit 14 to recalculate required transfer times TR1 and TR2.

Here, consider a case where, as a result of the calculation unit 14 recalculating the required transfer times TR1 and TR2, the following condition (1) is true and the following condition (3) is true.
Condition (1): TR1+TR2≦TA2-TP2
Condition (3): TA1-TP1-TR1≦TA2-TP2-TR2

Condition (1) being true means that the remaining required time (TR1 + TR2) is less than or equal to the remaining allowable time (TA2 - TP2), and that the order in which data D1 and data D2 are transferred can be either, as long as the transfer of data D2 is completed within the remaining allowable time (TA2 - TP2).

Furthermore, condition (3) indicates that the difference between the remaining allowable time (TA1-TP1) and the required time TR1 (i.e., the time available for transferring data D1) is less than or equal to the difference between the remaining allowable time (TA2-TP2) and the required time TR2 (i.e., the time available for transferring data D2). Therefore, the calculation unit 14 determines that data D1 needs to be transferred before data D2, and transmits this transfer order to the transfer control circuit 15.

In this case, the sum of the required transfer time TR2 and the waiting time TR1 required to execute another transfer request R1 scheduled before the start of transfer request R2 (TR2 + TR1) falls within the remaining allowable time for transfer request R2 (TA2 - TP2).

The transfer control circuit 15 resumes writing data D1 to RAM3 in the order of transfer from the calculation unit 14. After the transfer of data D1 is complete, the transfer control circuit 15 transfers a data transfer completion notification to the data transfer request source RS1 and starts transferring data D2. After the transfer of data D2 to RAM3 is complete, the transfer control circuit 15 sends a data D2 transfer completion notification to the data transfer request source RS2.

On the other hand, if condition (1) is true and condition (3) is false, the available time for transferring data D1 is greater than the available time for transferring data D2. Therefore, the calculation unit 14 determines that data D2 needs to be transferred before data D1, and transmits this transfer order to the transfer control circuit 15. In this case, the operation of the transfer control circuit 15 is the same as in Figure 2. Furthermore, the transfer time TR2 is the waiting time until the transfer of data D1 is resumed.

Figure 4 is yet another diagram showing the data transfer operation of this data transfer system. Figure 4 shows the operation when the required transfer time TR1 calculated by the calculation unit 14 in response to the first transfer request R1 from the transfer request source RS1 exceeds the allowable transfer time TA1 (TR1 > TA1).

When the transfer request source RS1 sends the destination address, source address, size of transfer data D1, and allowable transfer time TA1 to the transfer control circuit 15, the transfer control circuit 15 outputs a counter start command to counter C1 in the transfer time counter 16 and writes the allowable transfer time TA1 to the holding unit 11.

Next, the transfer control circuit 15 transmits the capacity of the transfer data D1 to the calculation unit 14, and the holding unit 11 outputs the allowable transfer time TA1 to the calculation unit 14. The calculation unit 14 calculates the required transfer time TR1 from the capacity of the transfer data D1 and the transfer interval based on the bus protocol, etc., and compares the required transfer time TR1 with the allowable transfer time TA1.

Here, we will explain the case where TR1≦TA1 is false, that is, the required transfer time TR1 is greater than the allowable transfer time TA1, and the data transfer cannot be completed within the allowable transfer time TA1. In this case, the calculation unit 14 sends the transfer order and an error detection signal indicating that an error has been detected to the transfer control circuit 15. At this point, only one transfer request R1 has been generated, so the transfer order indicates that data D1 corresponding to transfer request R1 will be transferred first. In response to the error detection signal, the transfer control circuit 15 sends an error notification E1 to the transfer request source RS1.

After error notification E1 is issued, the user can choose whether to execute transfer request R1 or abandon transfer request R1. If the user abandons transfer request R1, DMA unit 1 returns to the state it was in before receiving data transfer request R1 and enters a standby state.

The following describes the operation when executing transfer request R1. After outputting error notification E1, the transfer control circuit 15 reads transfer data D1 from transfer request source RS1, and transfer request source RS1 writes data D1 to the data buffer 12.

Then, the transfer control circuit 15 writes the data in the data buffer 12 to RAM 3. When the transfer of data D1 is complete, the transfer control circuit 15 outputs a transfer completion notification for data D1 to the transfer request source RS1, and at the same time outputs an initialization command to counter C1 in the transfer time counter 16.

Figure 5 is yet another diagram showing the data transfer operation of this data transfer system. Figure 5 shows the operation when a request to transfer data D2 is made while data D1 is being transferred, and if data D1 is transferred first, data D2 cannot be transferred within the allowed transfer time TA2, and if data D2 is transferred first, data D1 cannot be transferred within the allowed transfer time TA1.

That is, when a transfer request R1 is output from the transfer request source RS1 to the transfer control circuit 15, the transfer control circuit 15 activates counter C1 in the transfer time counter 16 and writes the allowed transfer time TA1 to the holding unit 11.

Next, the transfer control circuit 15 requests the calculation unit 14 to calculate the required transfer time TR1, and the holding unit 11 outputs the allowable transfer time TA1 to the calculation unit 14. The calculation unit 14 calculates the required transfer time TR1 and outputs the transfer order to the transfer control circuit 15. This transfer order indicates that data D1 will be transferred first. The transfer control circuit 15 reads data D1 from transfer request source RS1 and writes it to RAM3 until a second data transfer request R2 is input from transfer request source RS2.

When transfer request R2 is output from transfer request source RS2 to transfer control circuit 15, transfer control circuit 15 outputs a command to start counter C2 to transfer time counter 16. At the same time, transfer control circuit 15 stops writing data D1 from data buffer 12 to RAM3, outputs a command to calculate required times TR1 and TR2 to calculation unit 14, and outputs count value output commands to counters C1 and C2 within transfer time counter 16, causing calculation unit 14 to output processed times TP1 and TP2. At the same time, transfer control circuit 15 outputs the current transfer order to calculation unit 14.

The calculation unit 14 receives from the transfer time counter 16 the processed times TP1 and TP2 elapsed since the start of counters C1 and C2 for transfer requests R1 and R2, respectively, receives the amount of data D2 for transfer request R2 from the transfer control circuit 15, receives the amount of data D1 from the data buffer 12, and receives the allowable transfer times TA1 and TA2 from the holding unit 11.

Here, consider a case where, as a result of the calculation of the required transfer times TR1 and TR2 by the calculation unit 14, the following condition (1) is false and the following condition (2) is false.
Condition (1): TR1+TR2≦TA2-TP2
Condition (2): TR1+TR2≦TA1-TP1

Condition (1) being false means that the remaining required time (TR1 + TR2) is greater than the remaining allowable time (TA2 - TP2), and therefore data D2 must be transferred before data D1 in order to complete the transfer of data D2 within the remaining allowable time (TA2 - TP2).

Furthermore, if condition (2) is false, it means that the remaining required time (TR1 + TR2) is greater than the remaining allowable time (TA1 - TP1), and therefore data D1 must be transferred before data D2 in order to complete the transfer of data D1 within the remaining allowable time (TA1 - TP1).

In this case, since only one of the allowable times (TA1-TP1) and (TA2-TP2) can be met, priority is given to the transfer request R1 that was already in progress. The calculation unit 14 sends an error detection signal to the transfer control circuit 15 and notifies it of the transfer order. This transfer order indicates that data D1 will be transferred first, and data D2 will be transferred second.

After receiving the error detection signal and transfer order from the calculation unit 14, the transfer control circuit 15 outputs an error notification E2 to the transfer request source RS2. The transfer control circuit 15 then resumes writing data D1 to RAM3, and when writing of data D1 is complete, outputs a transfer completion notification for data D1 to the transfer request source RS1, and outputs an initialization command to counter C1 in the transfer time counter 16.

The user can then choose whether or not to execute transfer request R2. If transfer request R2 is executed, transfer control circuit 15 begins writing data D2 to RAM3. When the transfer of data D2 is complete, transfer control circuit 15 outputs a transfer completion notification for data D2 to transfer request source RS2, and outputs an initialization command to counter C2 within transfer time counter 16.

Figure 6 is a flowchart showing part of the operation of the transfer control circuit 15 shown in Figures 2 to 5, and Figure 7 is a flowchart showing the remaining part of that operation. When the transfer control circuit 15 is started, the transfer control circuit 15 is initialized in step S1. In step S2, the transfer control circuit 15 waits until a data transfer request is input from a system component.

When a data transfer request R1 is input from the transfer request source RS1 (peripheral circuit 4 in this example), in step S3 the transfer control circuit 15 outputs a start command (activation command) to counter C1 in the transfer time counter 16, activating counter C1.

In step S4, the transfer control circuit 15 transfers the allowable transfer time TA1 sent from the transfer request source RS1 to the holding unit 11. In step S5, the transfer control circuit 15 outputs a calculation request for the required transfer time TR1 to the calculation unit 14. In step S6, the transfer control circuit 15 waits until the calculation unit 14 sends a transfer order or error detection signal.

In step S7, the transfer control circuit 15 determines whether an error detection signal has been sent. If it determines that an error detection signal has been sent, in step S8 it outputs an error notification E1 to the transfer request source RS1, and then in step S8A it determines whether the user has abandoned the transfer request R1.

Whether the user has abandoned transfer request R1 may be determined in any manner. For example, one method is to preset in DMA unit 1 whether or not to abandon transfer request R1 when it is determined in step S7 that an error detection signal has been sent. Alternatively, when it is determined in step S7 that an error detection signal has been sent, this may be notified to transfer request source RS1, and an instruction as to whether or not to abandon transfer request R1 may be received from transfer request source RS1, thereby determining whether or not the user has abandoned transfer request R1.

If the transfer control circuit 15 determines in step S8A that the user has discarded the transfer request R1, it returns to step S2; if it determines that the user has not discarded the transfer request R1, it proceeds to step S10.

If it is determined in step S7 that an error detection signal has not been sent, the transfer control circuit 15 determines in step S9 whether or not there is a transfer request R2 from the transfer request source RS2 (in this example, the peripheral circuit 5). If there is a transfer request R2, the process proceeds to step S14 (Figure 7); if there is no transfer request R2, the process proceeds to step S10.

In step S10, the transfer control circuit 15 acquires data D1 from the transfer data source DS1 (peripheral circuit 4 in this example) and continues to transfer data D1 to the transfer destination DD1 (RAM 3 in this example). In step S11, the transfer control circuit 15 determines whether the transfer of data D1 is complete. If the transfer of data D1 is not complete, the process returns to step S9; if the transfer of data D1 is complete, the process proceeds to step S12.

In step S12, the transfer control circuit 15 sends a data transfer completion notification to the transfer request source RS1. In step S13, the transfer control circuit 15 outputs an initialization command to counter C1 in the transfer time counter 16, and then returns to step S2 to wait until the next transfer request is generated.

If a second data transfer request R2 occurs in step S9, in step S14 (Figure 7), the transfer control circuit 15 outputs a start command to counter C2 in the transfer time counter 16 to measure the time that has elapsed since the data transfer request R2 was generated.

In step S15, the transfer control circuit 15 writes the allowable transfer time TA2 transmitted from the transfer request source RS2 into the holding unit 11. In step S16, the transfer control circuit 15 outputs a command to the calculation unit 14 to recalculate the required transfer times TR1 and TR2. In step S16A, the transfer control circuit 15 outputs a count value output command to the transfer time counter 16 to output the processed times TP1 and TP2. In step S17, the transfer control circuit 15 waits until the calculation unit 14 transmits a transfer order or error detection signal.

In step S18, the transfer control circuit 15 determines whether an error detection signal has been sent, and if it determines that an error detection signal has been sent, in step S19 it outputs an error notification E2 to the transfer request source RS2, and then in step S19A it determines whether the user has abandoned the transfer request R2.

Whether the user has discarded transfer request R2 may be determined in any manner. For example, one method is to preset in DMA unit 1 whether or not to discard transfer request R2 when it is determined in step S18 that an error detection signal has been sent. Alternatively, when it is determined in step S18 that an error detection signal has been sent, this may be notified to transfer request source RS2, and an instruction as to whether or not to discard transfer request R2 may be received from transfer request source RS2, thereby determining whether or not the user has discarded transfer request R2.

If the transfer control circuit 15 determines in step S19A that the user has discarded transfer request R2, it proceeds to step S29; if it determines that the user has not discarded transfer request R2, it proceeds to step S21. If it determines in step S18 that an error detection signal has not been sent, it proceeds to step S20.

In step S20, the transfer control circuit 15 determines whether or not to prioritize transfer request R1 based on the transfer order sent from the calculation unit 14. If it determines that transfer request R1 is not prioritized, it proceeds to step S27; if it determines that transfer request R1 is prioritized, it proceeds to step S21.

In step S21, the transfer control circuit 15 transfers all data D1 from the transfer data source DS1 to the transfer destination DD1, in step S22 it sends a data transfer completion notification to the transfer request source RS1, and in step S23 it outputs an initialization command to counter C1 in the transfer time counter 16.

Next, in step S24, the transfer control circuit 15 transfers all data D2 from the transfer data source DS2 (peripheral circuit 5 in this example) to the transfer destination DD2 (RAM3 in this example), sends a data transfer completion notification to the transfer request source RS2 in step S25, and outputs an initialization command to counter C2 in the transfer time counter 16 in step S26. The transfer control circuit 15 then returns to step S2 (Figure 6) and waits until the next transfer request R1 is input.

If it is determined in step S20 that transfer request R1 does not have priority, the transfer control circuit 15 transfers all data D2 from the transfer data source DS2 (peripheral circuit 5 in this example) to the transfer destination DD2 (RAM3 in this example) in step S27, sends a data transfer completion notification to the transfer request source RS2 in step S28, and outputs an initialization command to counter C2 in the transfer time counter 16 in step S29.

Next, in step S30, the transfer control circuit 15 transfers all of the data D1 from the transfer data source DS1 to the transfer destination DD1, sends a data transfer completion notification to the transfer request source RS1 in step S31, and outputs an initialization command to counter C1 in the transfer time counter 16 in step S32. The transfer control circuit 15 then returns to step S2 (Figure 6) and waits until the next transfer request R1 is input.

Figure 8 is a flowchart showing the operation of the individual counter C included in the transfer time counter 16. The transfer time counter 16 includes multiple independent individual counters C. Each individual counter C operates independently for each data transfer and measures the processing time TP for each data transfer.

When the DMA unit 1 is started, the individual counter C is initialized in step S60. At this time, the count value of the individual counter C is set to its initial value. In step S61, the individual counter C waits until a start command is input from the transfer control circuit 15.

In step S62, the count value of the individual counter C to which the start command has been input is incremented (+1) in response to each pulse of the system clock. In step S63, the individual counter C determines whether or not there is a count value output command from the transfer control circuit 15. If it determines that there is a count value output command, it proceeds to step S65; if it determines that there is no count value output command, it proceeds to step S64.

In step S64, individual counter C determines whether or not there is an initialization command from the transfer control circuit 15. If it determines that there is an initialization command, it returns to step S60; if it determines that there is no initialization command, it returns to step S62.

If it is determined in step S63 that there is a count value output command, in step S65 the individual counter C transmits the current count value to the calculation unit 14, and then the process returns to step S62.

Next, we will explain the method for determining which of the transfer request R1, which was input first, or the transfer request R2, which was input later, should be given priority. We assume that the required transfer time TR1 for transfer request R1 is less than or equal to the allowable transfer time TA1 (TR1≦TA1), and similarly, the required transfer time TR2 for transfer request R2 is less than or equal to the allowable transfer time TA2 (TR2≦TA2). If this assumption is not met, an error notification will be sent to the transfer request source when the data transfer request is accepted, as shown in steps S6-S8 (Figure 6) and steps S17-S19 (Figure 7) above.

First, we will explain case CA1, where when transfer request R2 is executed after transfer request R1 is executed, it falls within the allowed transfer time TA2 and the slack time TM1 is less than or equal to the slack time TM2. Here, slack time TM is time information that indicates how much leeway there is in the time required to issue a transfer completion notification for a given data transfer request compared to its own allowed transfer time TA.

Before a certain data transfer request (e.g., R2) can begin to be executed, another data transfer request (e.g., R1) may be executed first. In such cases, the start of the transfer request (in this case, R2) must wait the time required (in this case, TR1) for the other data transfer request (in this case, R1). For this reason, the slack time TM is calculated as follows:

Here, if there are a total of n data transfer requests, each transfer request is distinguished from the others by the lowercase n, and is represented as transfer request R1, transfer request R2, ..., transfer request Rn, and the uppercase N indicates the order in which each transfer request is executed, and is represented as 1st, 2nd, ..., Nth.

The slack time TMn when transfer request Rn is transferred Nth is TMn = TAn - SUM(N-1) - TRn - TPn. Here, SUM(N-1) = [TR1 + TR2 + ... + TR(N-1)], and SUM(N-1) is the sum of the transfer times TR required for the transfer requests executed from the first to the (N-1)th.

In the above example, a determination is being made as to which of two transfer requests R1 and R2 will be transferred first, so there are no transfer requests made before transfer requests R1 and R2. Therefore, the "sum of transfer times TR required for transfers executed before transfer request Rn (SUM(N-1))" in the above formula is 0. In other words, SUM(1-1) = SUM(0) = 0. Therefore, TM1 = TA1 - TP1 - TR1, and TM2 = TA2 - TP2 - TR2.

If data transfer based on transfer request R1 is resumed and then data transfer based on transfer request R2 is performed, and the data transfer falls within the allowable transfer time TA2, and the slack time TM1 is less than or equal to the slack time TM2 (TM1 ≤ TM2, i.e., TA1 - TP1 - TR1 ≤ TA2 - TP2 - TR2), transfer request R2 will be executed after transfer request R1.

For case CA1 to be true, condition (1) must be true, i.e., TR1 + TR2 ≦ TA2 - TP2, and condition (3) must be true, i.e., TA1 - TP1 - TR1 ≦ TA2 - TP2 - TR2.

Next, we will explain case CA2, where when transfer request R2 is executed after transfer request R1 is executed, it falls within the transfer allowable time TA2 and the leeway time TM1 is greater than the leeway time TM2 (TM1 > TM2, i.e., TA1 - TP1 - TR1 > TA2 - TP2 - TR2).

In this case, even if the transfer of data D1 is resumed and then data D2 is transferred, it will still fall within the allowable transfer time TA2, but the leeway time TM2 is shorter than the leeway time TM1. Therefore, if data D2 is transferred after data D1 and a new data transfer request R3 occurs, if data transfer request R3 is executed before data transfer request R2, there is a high possibility that the allowable time TA2 for data transfer request R2 will not be met. For this reason, in order to meet the allowable time TA as much as possible when there are multiple data transfer requests, transfer request R2 is executed first, followed by transfer request R1.

For case CA2 to occur, condition (1) - TR1 + TR2 ≦ TA2 - TP2 - must be true, and condition (3) - TA1 - TP1 - TR1 ≦ TA2 - TP2 - TR2 - must be false.

Next, we will explain case CA3, where data D2 cannot be transferred in time after data D1 has been transferred, but by transferring data D2 first, the allowable transfer time TA2 is met, and then data D1 is transferred, so the allowable transfer time TA1 is met. In this case, if data D2 is transferred first and then data D1 is transferred, the allowable transfer time TA will not be exceeded, so data D2 is transferred first.

For case CA3 to be true, condition (1), i.e., TR1 + TR2 ≦ TA2 - TP2, must be false, and condition (2), i.e., TR1 + TR2 ≦ TA1 - TP1, must be true.

Next, we will explain case CA4, where if data D2 is transferred first, the transfer of data D2 will be completed in time, but the transfer of data D1 will not be completed in time. In this case, data D1, which was already being transferred, is transferred first, and an error notification E2 is sent to the transfer request source RS2.

For case CA4 to exist, condition (1) - TR1 + TR2 ≦ TA2 - TP2 - must be false, and condition (2) - TR1 + TR2 ≦ TA1 - TP1 - must be false.

As a supplementary note, in cases CA1 and CA2, the transfer order is determined based on the slack time TM. Transfers that meet the allowable transfer time TA can be achieved without this, and regardless of which transfer request R1 or R2 is executed first, the respective allowable times TA will be met. Therefore, whether or not to perform the determination based on the slack time TM is optional. If the determination based on the slack time TM is not performed, then if condition (1) is true, i.e., TR1 + TR2 ≦ TA2 - TP2, then transfer request R1 is executed first, and transfer request R2 is executed second.

Figure 9 is a flowchart showing part of the operation of the calculation unit 14, and Figure 10 is a flowchart showing the remaining part of that operation. When the calculation unit 14 is started, the calculation unit 14 is initialized in step S81. In step S82, the calculation unit 14 waits until a calculation request is input from the transfer control circuit 15.

When a calculation request is input, in step S83 the calculation unit 14 determines whether the calculation request is due to the first data transfer request R1. If the calculation unit 14 determines that the calculation request is not due to data transfer request R1 (if it is due to a second or subsequent data transfer request), it proceeds to step S90 (Figure 10). If the calculation unit 14 determines that the calculation request is due to data transfer request R1 (if there are no other data transfer requests), it proceeds to step S84.

In step S84, the calculation unit 14 obtains the allowable transfer time TA1 from the holding unit 11, and in step S85 obtains the size of data D1 from the transfer control circuit 15. In step S86, the calculation unit 14 calculates the required transfer time TR1 based on the size of data D1, the clock frequency, and the transfer interval according to the bus protocol.

In step S87, the calculation unit 14 compares the calculated required transfer time TR1 with the allowable transfer time TA1 transferred from the transfer control circuit 15, and determines whether TR1 is less than or equal to TA1.

If TR1≦TA1 is not true, then in step S88 the calculation unit 14 outputs the transfer order and error notification E1 to the transfer control circuit 15, and the process returns to step S82. If TR1≦TA1 is true, then in step S89 the calculation unit 14 outputs the transfer order to the transfer control circuit 15, and the process returns to step S82.

If it is determined in step S83 (Figure 9) that the data transfer is not caused by data transfer request R1 (if the data transfer is caused by a second or subsequent data transfer request), then in step S90 (Figure 10), the calculation unit 14 obtains the allowable transfer times TA1 and TA2 from the storage unit 11.

In step S91, the calculation unit 14 obtains the capacity of data D1 and D2 from the data buffer 12 and obtains the transfer order from the transfer control circuit 15. In step S92, the calculation unit 14 obtains the count values from counters C1 and C2 in the counter 16. In step S93, the calculation unit 14 recalculates the transfer times TR1 and TR2.

In step S94, the calculation unit 14 compares the calculated required transfer time TR2 with the allowable transfer time TA2 transferred from the transfer control circuit 15, and determines whether TR2 is less than or equal to TA2.

If TR2≦TA2 (YES in step S94), then in step S95 the calculation unit 14 determines whether condition (1), i.e., TR1 + TR2≦TA2-TP2, is true. If condition (1) is true (YES in step S95), then in step S96 the calculation unit 14 determines whether condition (3), i.e., TA1-TP1-TR1≦TA2-TP2-TR2, is true.

If condition (3) is true (YES in step S96), the above case CA1 applies, so in step S97 the calculation unit 14 outputs a transfer order to the transfer control circuit 15 indicating that data D1 will be sent first and data D2 will be sent second, and the process returns to step S82 (Figure 9).

If condition (3) is false (NO in step S96), the above case CA2 applies, so in step S98 the calculation unit 14 outputs a transfer order to the transfer control circuit 15 indicating that data D2 will be sent first and data D1 will be sent second, and the process returns to step S82.

If condition (1) is false (NO in step S95), in step S99, the calculation unit 14 determines whether condition (2), i.e., TR1 + TR2 ≦ TA1 - TP1, is true.

If condition (2) is true (YES in step S99), the above case CA3 applies, so in step S98 the calculation unit 14 outputs a transfer order to the transfer control circuit 15 indicating that data D2 will be sent first and data D1 will be sent second, and then the process returns to step S82.

If condition (2) is false (NO in step S99), the above case CA4 applies, so in step S100 the calculation unit 14 sends an error notification E2 to the transfer request source RS2 and outputs a transfer order to the transfer control circuit 15 indicating that data D1 will be sent first and data D2 will be sent second, and then returns to step S82. However, as mentioned above, the user can choose whether to transfer data D2 or discard transfer request R2.

If TR2≦TA2 is not satisfied (NO in step S94), in step S100, the calculation unit 14 sends an error notification E2 to the transfer request source RS2 and outputs a transfer order indicating that data D1 will be sent first and data D2 will be sent second to the transfer control circuit 15, and then returns to step S82. However, in this case, too, the user can select whether to transfer data D2 or discard transfer request R2.

As described above, in this first embodiment, the required transfer time TR is calculated for each transfer request, and the order in which multiple transfer requests are executed is set so that the required transfer time TR for each transfer request falls within the allowable transfer time TA for that transfer request. Furthermore, the allowable transfer time TA is set to a shorter time the higher the priority of the transfer request. Therefore, even when high-priority data and low-priority data are mixed, the high-priority data can be transferred before the low-priority data.

Furthermore, Figure 11 is a flowchart showing part of the operation of the calculation unit 14 included in the modified example of the first embodiment, and Figure 12 is a flowchart showing the remaining part of the operation. In the first embodiment, a case where two transfer requests R1 and R2 are generated is described, but the transfer order can also be determined in a similar manner when three or more transfer requests are generated. In this modified example, a data transfer system is described that is capable of transferring high priority data before low priority data, even when any number of transfer requests are generated.

In Figure 11, steps S120 to S128 are the same as steps S81 to S89 (Figure 9). That is, when the calculation unit 14 is started, it is initialized and waits until a calculation request is input from the transfer control circuit 15 (steps S120 and S121).

When a calculation request is input, the calculation unit 14 determines whether the calculation request is due to the first data transfer request R1 (step S122). If it determines that the calculation request is not due to data transfer request R1 (if it is due to a second or subsequent data transfer request), the calculation unit 14 proceeds to step S129 (Figure 12). If it determines that the calculation request is due to data transfer request R1 (if there are no other data transfer requests), the calculation unit 14 proceeds to step S123.

The calculation unit 14 obtains the allowable transfer time TA1 from the holding unit 11 (step S123), obtains the size of the data D1 from the transfer control circuit 15 (step S124), and calculates the required transfer time TR1 based on the allowable transfer time TA1, the size of the data D1, the clock frequency, and the transfer interval according to the bus protocol (step S125).

Next, the calculation unit 14 compares the calculated required transfer time TR1 with the allowable transfer time TA1 transferred from the transfer control circuit 15, and determines whether TR1 is less than or equal to TA1 (step S126).

If TR1≦TA1 is not true, the calculation unit 14 outputs the transfer order and error notification E1 to the transfer control circuit 15 and returns to step S121 (step S127). If TR1≦TA1 is true, the calculation unit 14 outputs the transfer order to the transfer control circuit 15 and returns to step S121 (step S128).

If it is determined in step S122 (Figure 11) that the data transfer is not caused by the first data transfer request R1 (if the data transfer is caused by a second or subsequent data transfer request), then in step S129 (Figure 12), the calculation unit 14 obtains the allowable transfer time TA stored in the storage unit 11.

In step S130, the calculation unit 14 obtains the capacity of data D from the data buffer 12 and transfer control circuit 15, and obtains the transfer order from the transfer control circuit 15. In step S131, the calculation unit 14 obtains the count value from counter C in counter 16. In step S132, the calculation unit 14 recalculates all required transfer times TR. Although the required transfer times TR may have been calculated in the past, they are recalculated because the transfer process may have progressed due to data transfer and the amount of data transferred may have decreased.

In step S133, if the total number of transfer requests R is n, the calculation unit 14 sets X = N-1. Now, let's consider a newly generated data transfer request Rn, where n is an integer greater than or equal to 2. There are only (n-1) data transfer requests R scheduled to be transferred prior to data transfer request Rn, and the transfer order of data D1 to D(n-1) is anywhere from 1st to (N-1).

The calculation unit 14 repeatedly determines whether transfer request Rn can be executed before transfer requests R1 to R(n-1) that were scheduled before transfer request Rn, starting from the last scheduled transfer request (i.e., the transfer request whose transfer order is (N-1)). For this reason, in step S133, the initial value of the variable X for the repetitive process is expressed as (N-1).

Here, we will explain the method for determining whether to execute transfer request Rn before transfer requests R1 to R(n-1). The premise is that for all transfer requests R, the required transfer time TR is less than or equal to the allowable transfer time TA (TR≦TA). If this premise is not met, an error will be notified to the transfer request source RS at the time the data transfer request R is accepted in step S127 (FIG. 11) and step S141 (FIG. 12).

First, we will explain case CA11, where, after the first through Xth data transfers have been performed, the nth data transfer is performed within the allowable transfer time TAn and the margin time TMX for the Xth data transfer is less than or equal to the margin time TMn. In this case, because the Xth data transfer has a higher priority, the nth data transfer will be performed (X+1).

To determine whether the case is CA11, the following condition (11) and condition (12) must be true (steps S135, S136, S140). Here, SUM(X) is the sum of the required transfer times TR from the first to the Xth transfers. Condition (12) compares the slack times TMn and TMX that would occur if the transfer request Rn and the transfer request originally scheduled for the Xth transfer were executed in the Xth transfer.
Condition (11): TRn+SUM(X)≦TAn-TPn
Condition (12): TMX≦TMn, i.e., TAX−(TPX+TRX+SUM(X−1))≦TAn−(TPn+TRn+SUM(X−1))

Next, we will explain case CA12, where, after the first through Xth data transfers have been performed, the nth data transfer is performed within the allowable transfer time TAn and the margin time TMX for the Xth data transfer is greater than the margin time TMn.

In this case, even if the Xth data transfer is performed followed by the nth data transfer Rn, it will still fit within the allowable transfer time TAn. However, as in case CA2, when a new transfer request occurs, i.e., a transfer request for the (n+1)th or later transfer, the order of the Xth data transfer and data transfer Rn is swapped (step S137A) to increase the likelihood that each data transfer request can be transferred within the allowable time TA. As a result, transfer request Rn is executed Xth, and the data transfer originally scheduled to be executed Xth is executed (X+1).

Note that this is the same as swapping the execution order of transfer request R1 and transfer request R2 in case CA2 above. In case CA2, transfer request R1 was originally executed first, but because the slack time TM2 of transfer request R2 is shorter than the slack time TM1 of transfer request R1, transfer request R2 is executed first and transfer request R1 is executed second.

Furthermore, although transfer request Rn is to be executed Xth, there is a possibility that the margin time TMX of the (X-1)th data transfer executed immediately before transfer request Rn is greater than the margin time TMn of transfer request Rn. Therefore, the value of X is decreased by 1 for the repeated processing, and the determination is made again from case CA11 (steps S138, S139). To be determined as case CA12, the above condition (11) must be true and condition (12) must be false (steps S135, S136, S137A).

Next, we will explain case CA13, where if transfer request Rn is executed after the first through Xth data transfers have been executed, the data transfer will not be completed in time, but if transfer request Rn is transferred before the original Xth data transfer, the original allowable transfer time TA for the Xth data transfer will be satisfied.

In this case, the allowable time TA is met even if the transfer request that was originally Xth is executed after transfer request Rn, so transfer request Rn is executed Xth so that it is executed first, and the data transfer that was originally Xth is executed (X+1)th.

In order to determine that the case is CA13, the above condition (11) must be false and the following condition (13) must be true (steps S135, S137, S137A).
Condition (11): TRn+SUM(X)≦TAn-TPn
Condition (13): TRX+TRn+SUM(X-1)≦TAX-TPX

Note that when determining case CA13, the order X of conditions (11) and (13) is the original order of the Xth transfer request before it was swapped with transfer request Rn.

Furthermore, if condition (11) is false, it means that the allowable time TAn for transfer request Rn cannot be met unless transfer request Rn is swapped with the original Xth transfer request.

Furthermore, the fact that condition (13) is true means that even if transfer request Rn is executed before data transfer request RX, which was originally the Xth (i.e., even if transfer request Rn is executed Xth and transfer request RX is executed (X+1)th), the allowable transfer time TA of transfer request RX will be met.

Furthermore, after case CA13, to determine whether the allowable transfer time TAn can be met and whether it is necessary to further advance the order of transfer request Rn depending on the relative magnitude of the slack time TMn of transfer request Rn and the slack time TM of the transfer immediately preceding transfer request Rn [the (X-1)th transfer], the value of X is decreased by 1, as in case CA12, and the determination from case CA11 is repeated again.

However, in cases CA12 and CA13, if subtracting 1 from X results in X being 0, there are no more transfer requests to be executed before transfer request Rn, so transfer request Rn is set to first and the loop is exited (steps S139 and S140).

Furthermore, even if the calculation of the slack time in cases CA1 and CA2 is not performed, TRn≦TAn and no operational problems will occur, so the user can choose whether to perform step S136. If step S136 is not performed, the loop will exit when the minimum necessary transfer order for transfer request Rn to satisfy the transfer allowable time TAn is determined in step S135.

As an additional note, because step S134 determines whether TRn≦TAn, even if transfer request Rn becomes the earliest in order (transfer request Rn is first), the event of not meeting the transfer allowable time TAn will not occur.

Next, we will explain case CA14, where the allowable transfer time TAn cannot be met after the first through Xth data transfers have been executed, and the allowable transfer time TAX of the original Xth transfer request RX cannot be met if transfer request Rn is executed before the original Xth transfer request RX.

In this case, the Xth data transfer is executed first. An error notification is sent to the transfer request source that sent the transfer request Rn. If the above condition (11) is false and the above condition (13) is false, it is determined that the case is CA14 (steps S135, S137, S141).

In this case, an error notification for transfer request Rn is sent to the transfer control circuit 15. The user can choose whether to implement transfer request Rn in which an error occurred. If transfer request Rn is to be implemented, transfer request Rn is implemented as the (X+1)th request (step S141).

Note that if a transfer request Rn that resulted in an error is implemented, there is a high possibility that newly generated transfer requests R(n+1) and onwards will result in an error until the execution of transfer request Rn is completed. Therefore, depending on the purpose of the system, it may be effective to not implement the transfer request that resulted in an error.

Referring again to FIG. 12, in step S134, the calculation unit 14 compares the required transfer time TRn and the allowed transfer time TAn for the newly generated transfer request Rn, and determines whether TRn≦TAn.

If TRn≦TAn (YES in step S134), in step S135 the calculation unit 14 determines whether condition (11) is true. If condition (11) is true (YES in step S135), in step S136 the calculation unit 14 determines whether condition (12) is true.

If condition (12) is true (YES in step S136), the above case CA11 applies, so in step S140, the calculation unit 14 sends to the transfer control circuit 15 a transfer order indicating that the latest data transfer request Rn will be executed as the (X+1)th.

If condition (12) is false (NO in step S136), the above case CA12 applies, so the calculation unit 14 swaps the transfer order of the Xth data transfer and data transfer Rn in step S137A, decreases the value of X by 1 in step S138, and determines whether X = 0 in step S139. If X = 0 (YES in step S139), the calculation unit 14 executes step S140. If X = 0 is not (NO in step S139), the calculation unit 14 returns to step S135.

If condition (11) is false (NO in step S135), in step S137 the calculation unit 14 determines whether condition (13) is true. If condition (13) is true (YES in step S137), the above case CA13 applies, and the calculation unit 14 proceeds to step S137A.

If condition (13) is false (NO in step S137), the above case CA14 applies, so in step S141 the calculation unit 14 issues an error notification En for the nth transfer request Rn, responds to the transfer control circuit 15 with a transfer order indicating that transfer request Rn will be executed in the (X+1)th order, and returns to step S121 (Figure 11).

As described above, in this modified example, even when an arbitrary number n of transfer requests occur, high priority data can be transferred before low priority data.

Embodiment 2.
In the first embodiment, if the transfer allowable time TAn is not met when the transfer request Rn is executed after the first to Xth data transfers have been executed, and if the transfer request Rn is executed before the original Xth transfer request RX, the transfer allowable time TAX of the original Xth transfer request RX is not met (case CA14 above), then the transfer request Rn is always executed after the transfer request RX (step S100 in FIG. 10, step S141 in FIG. 12).

However, depending on the product or system, if a newly generated data transfer request Rn is important, it may be necessary to prioritize execution of the important transfer request Rn, even if this means making the previous transfer request RX wait. This second embodiment aims to solve this problem.

Figure 13 is a block diagram showing the configuration of a data transfer system according to the second embodiment, and is a diagram to be compared with Figure 1. Figure 13 differs from Figure 1 in that peripheral circuits 4 and 5 are replaced with peripheral circuits 21 and 22, respectively, and DMA unit 1 is replaced with DMA unit 25.

Each of the peripheral circuits 21 and 22 transmits a data transfer request R to the DMA unit 25 as a transfer request source RS. This data transfer request R includes not only first information relating to the source address, destination address, required transfer time TR (i.e., transfer data capacity), and second information indicating the allowable transfer time TA, but also third information indicating the importance IM of the transfer request R. The importance IM may be defined in any way, but for example, the importance IM is represented by a number from 1, 2, or 3, with the more important the transfer request R, the larger the number.

DMA unit 25 differs from DMA unit 1 in that it includes an importance holding unit 26, and the required transfer time calculation unit 14 and transfer control circuit 15 have been replaced with a required transfer time calculation unit 27 and a transfer control circuit 28, respectively. Note that the required transfer time calculation unit 27 may also be referred to simply as the "calculation unit 27" below.

The importance holding unit 26 holds the importance IM transferred from the transfer request source TS and outputs the importance IM to the calculation unit 27. The calculation unit 27 performs the same operations as the calculation unit 14, and also acquires the importance IM from the importance holding unit 26 when acquiring the transfer allowable time TA from the holding unit 11 (step S123 in Figure 11, step S129 in Figure 12).

Furthermore, if the calculation unit 27 determines that the above case CA14 applies because the above condition (11) is false and the above condition (13) is false (NO in step S137 of FIG. 12), it compares the importance IMX of the Xth transfer request RX in the transfer order with the importance IMn of the newly generated transfer request Rn.

If the importance IMn of transfer request Rn is higher than the importance IMX of transfer request RX, the calculation unit 27 swaps the transfer order of transfer request Rn and transfer request RX and notifies the transfer request source RSX of transfer request RX of an error EX.

On the other hand, if the importance IMn of transfer request Rn is equal to or less than the importance IMX of transfer request RX, the calculation unit 27 does not change the transfer order of transfer request Rn and transfer request RX, and notifies the transfer request source RSn of transfer request Rn of an error En.

The transfer control circuit 28 performs the same operations as the transfer control circuit 15, and also transfers the importance IM to the importance holding unit 26 when transferring the transfer allowable time TA to the holding unit 11 (step S4 in Figure 6, step S15 in Figure 7).

Figure 14 is a flowchart showing the main operations of the calculation unit 27, and is a diagram to be compared with Figure 12. Figure 14 differs from Figure 12 in that steps S151 and S152 have been added.

If the result of step S137 is NO, the calculation unit 27 determines in step S151 whether the following condition (14) is true:
Condition (14): IMX<IMn

If condition (14) is true (YES in step S151), the importance IMn of transfer request Rn is higher than the importance IMX of transfer request RX, so the calculation unit 27 sends an error notification EX to the requestor RSX of transfer request RX in step S152, and then swaps the transfer order of transfer request RX and transfer request Rn in step S137A. As a result, the more important transfer request Rn is executed before transfer request RX.

In step S152, an error notification EX is sent to the requestor RSX of the transfer request RX because condition (13) is false (NO in step S137), and if the transfer order of the transfer request RX and the transfer request Rn is swapped, the allowable transfer time TAX of the transfer request RX, which was originally the Xth, would no longer be met.

If condition (14) is false (NO in step S151), the importance IMn of transfer request Rn is less than or equal to the importance IMX of transfer request RX, so in step S141, the calculation unit 27 sends an error notification En to the requestor RSn of transfer request Rn and responds with a transfer order so that transfer request Rn is executed after transfer request RX. The other configurations and operations are the same as in embodiment 1, so their description will not be repeated.

As described above, in this second embodiment, in case CA14 (NO in step S137 in FIG. 14), the importance IMX of transfer request RX is compared with the importance IMn of transfer request Rn, and if IMX < IMn, transfer request Rn is executed before transfer request RX. Therefore, although transfer request RX will have to wait, transfer request Rn, which is more important than transfer request RX, can be executed before transfer request RX.

In the second embodiment, the transfer control circuit 28 transfers the importance IM included in the transfer request R to the importance holding unit 26, but this is not limited to this, and the transfer request source (peripheral circuits 21, 22) may also register the importance IM of the transfer request R in the importance holding unit 26.

Embodiment 3.
In the second embodiment, in the case of case CA14, the calculation unit 27 (FIG. 13) of the DMA unit 25 determines whether the condition (14) is true or false based on the importance IMX, IMn of the transfer requests RX, Rn, and if the condition (14) is true, the order in which the transfer requests RX, Rn are executed (transfer order) is changed (steps S151, S152, S137A in FIG. 14).

However, depending on the product or system, it may be difficult to uniformly define the importance IM for all transfer requests R. Furthermore, the situation may change after a transfer request R is issued, causing the importance IM of that transfer request R to change. If the transfer order is changed in such a case, an unintended situation may occur in the product or system. This third embodiment aims to solve this problem.

Figure 15 is a block diagram showing the configuration of a data transfer system according to the third embodiment, and is a diagram to be compared with Figure 1. Figure 15 differs from Figure 1 in that peripheral circuits 4 and 5 are replaced by peripheral circuits 31 and 32, respectively, and DMA unit 1 is replaced by DMA unit 33.

Peripheral circuits 31 and 32 each perform the same operations as peripheral circuits 4 and 5, and when DMA unit 33 inquires whether the transfer order can be changed, they also send a response to that inquiry to DMA unit 33.

DMA unit 33 differs from DMA unit 1 in that required transfer time calculation unit 14 has been replaced with required transfer time calculation unit 34. Note that required transfer time calculation unit 34 may also be referred to simply as "calculation unit 34" below. Calculation unit 34 performs the same operations as calculation unit 14, and in case CA14, queries the requester RSX of transfer request RX (for example, peripheral circuit 31) as to whether the order in which transfer requests RX and Rn are executed can be reversed.

If the request source RSX replies that it is possible to switch the transfer requests RX and Rn, the calculation unit 34 switches the order of the transfer requests Rn and RX and notifies the transfer request source RSX of the transfer request RX of an error EX.

On the other hand, if the calculation unit 34 receives a response from the request source RSX indicating that it is not possible to switch the transfer requests RX and Rn, it does not switch the order of the transfer requests Rn and RX, and notifies the transfer request source RSn (for example, the peripheral circuit 32) of the transfer request Rn of an error En.

Figure 16 is a flowchart showing the main operations of the calculation unit 34, and is a diagram to be compared with Figure 12. Figure 16 differs from Figure 12 in that steps S161 to S164 have been added.

If the answer is NO in step S137, the calculation unit 34 inquires in step S161 of the requestor RSX (e.g., peripheral circuit 31) of the transfer request RX as to whether the transfer requests RX and Rn can be swapped. The transfer requestor RSX reviews the inquiry from the calculation unit 34 and sends a response to the calculation unit 34 as to whether the transfer requests RX and Rn can be swapped.

In step S162, the calculation unit 34 receives a response from the transfer request source RSX, and in step S163, based on the received response, determines whether or not the transfer requests RX and Rn can be swapped.

If it is possible to switch the transfer requests RX and Rn (YES in step S163), the calculation unit 34 sends an error notification EX to the requestor RSX of the transfer request RX in step S164, and then switches the transfer order of the transfer request RX and the transfer request Rn in step S137A. This allows the important transfer request Rn to be executed before the transfer request RX.

In step S164, an error notification EX is sent to the requestor RSX of the transfer request RX because condition (13) is false (NO in step S137), and if the transfer order of the transfer request RX and the transfer request Rn is swapped, the allowable transfer time TAX of the transfer request RX, which was originally the Xth, would no longer be met.

If it is not possible to switch the transfer requests RX and Rn (NO in step S163), the calculation unit 34 sends an error notification En to the requestor RSn of the transfer request Rn in step S141, and also responds with a transfer order so that the transfer request Rn is executed after the transfer request RX. The other configurations and operations are the same as in embodiment 1, so their description will not be repeated.

As described above, in this third embodiment, in case CA14 (NO in step S137 of FIG. 16), the requestor RSX of the transfer request RX is queried as to whether or not the transfer requests RX and Rn can be swapped, and if the response is that they can be swapped, the transfer request Rn is executed before the transfer request RX. Therefore, in addition to obtaining the same effect as in the first embodiment, even if it is difficult to uniformly define the importance IM for all transfer requests R, or even if the importance IM of a transfer request R changes after it is issued, the important transfer request Rn can be executed first without causing a situation that goes against the intention of the system.

When inquiring of the requester RSX of the transfer request RX as to whether or not the transfer requests RX and Rn can be swapped, the requester RSX may be informed of information such as the extent to which the transfer allowable time TAX will be exceeded if the transfer requests RX and Rn are swapped, as information for determining whether or not the transfer requests RX and Rn can be swapped.

Furthermore, in this third embodiment, only the request source RSX of the transfer request RX is inquired about whether or not the transfer request can be swapped, but this is not limited to this. It is also possible to inquire about whether or not the transfer request can be swapped of all transfer request sources RS0 to RSX other than the transfer request source RSn, and swap the transfer request that becomes swappable with the transfer request Rn.

Furthermore, if it is possible to switch the transfer requests RX and Rn, the new transfer allowance time TAX1 can also be included in the response, and the transfer allowance time TAX stored in the storage unit 11 can be rewritten with the new transfer allowance time TAX1. In this case, no errors will occur after the transfer order is switched.

It is also possible to combine the second and third embodiments as appropriate. For example, it is possible to determine whether or not the transfer requests RX and Rn can be swapped based on the importance IMX and IMn, and if IMX < IMn, swap the transfer order (second embodiment), and if IMX = IMn, inquire of the requestor RSX whether or not the transfer requests RX and Rn can be swapped (third embodiment).

The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The technical scope of the present disclosure is defined by the claims, not the above-described embodiments, and is intended to include all modifications within the meaning and scope of the claims.

1, 25, 33 DMA unit, 2 System bus, 3 RAM, 4, 5, 21, 22, 31, 32 Peripheral circuits, 6 MPU, 11 Transfer allowable time holding unit, 12 Data buffer, 13 BUS/IF, 14, 27, 34 Transfer required time calculation unit, 15 Transfer control circuit, 16 Transfer time counter, 17 Destination address pointer, 18 Source address pointer, 26 Importance holding unit.

Claims (6)

A data transfer device that transfers data in accordance with a plurality of transfer requests,
Each transfer request includes first information relating to a required transfer time required to execute the transfer request, and second information indicating an allowed transfer time, which is a maximum time allowed for completing a data transfer for the transfer request;
The data transfer device
a calculation unit that sets an order of execution of the plurality of transfer requests based on the first and second information of each of the transfer requests;
a transfer control circuit that executes the plurality of transfer requests in an order set by the calculation unit;
The calculation unit
calculating the required transfer time for each of the transfer requests based on the first information;
setting an order in which the plurality of transfer requests are to be executed so that the required transfer time of each of the transfer requests falls within the transfer allowable time of the transfer request;
When the order cannot be set so that the required transfer time of each of the transfer requests falls within the transfer allowable time of the transfer request, the calculation unit:
inquiring of a requester of another transfer request scheduled before the start of the transfer request whether or not it is possible to change the order of the transfer request and the other transfer request;
If it is answered that the order can be changed, the order is set so that each of the transfer requests is executed before the other transfer requests;
If the response is that the order cannot be changed, the data transfer device sets the order so that each of the transfer requests is executed after the other transfer requests. A data transfer device that transfers data in accordance with a plurality of transfer requests,
Each transfer request includes first information relating to a required transfer time required to execute the transfer request, and second information indicating an allowed transfer time, which is a maximum time allowed for completing a data transfer for the transfer request;
The data transfer device
a calculation unit that sets an order of execution of the plurality of transfer requests based on the first and second information of each of the transfer requests;
a transfer control circuit that executes the plurality of transfer requests in an order set by the calculation unit;
The calculation unit
calculating the required transfer time for each of the transfer requests based on the first information;
setting an order in which the plurality of transfer requests are to be executed so that the required transfer time of each of the transfer requests falls within the transfer allowable time of the transfer request;
a timer unit for measuring the elapsed time from the time when each of the transfer requests is notified;
Each time the transfer request is notified, the calculation unit:
Calculating the remaining time of the permissible transfer time for each of the transfer requests based on the timekeeping result of the timekeeping unit;
recalculating the required transfer time for executing each of the transfer requests based on the remaining amount of data in each of the transfer requests;
a data transfer device that resets the order in which the plurality of transfer requests are executed so that the recalculated required transfer time falls within the remaining time of the allowed transfer time. A data transfer device that transfers data in accordance with a plurality of transfer requests,
Each transfer request includes first information relating to a required transfer time required to execute the transfer request, and second information indicating an allowed transfer time, which is a maximum time allowed for completing a data transfer for the transfer request;
The data transfer device
a calculation unit that sets an order of execution of the plurality of transfer requests based on the first and second information of each of the transfer requests;
a transfer control circuit that executes the plurality of transfer requests in an order set by the calculation unit;
The calculation unit
calculating the required transfer time for each of the transfer requests based on the first information;
setting an order in which the plurality of transfer requests are to be executed so that the required transfer time of each of the transfer requests falls within the transfer allowable time of the transfer request;
Each time the transfer request is notified, the calculation unit:
calculate a first margin time, which is the difference between the permissible transfer time and the required transfer time of the transfer request;
For another transfer request scheduled to be executed before the transfer request, a second margin time is calculated, which is the difference between the transfer allowable time and the transfer required time of the other transfer request;
If the first margin time is greater than the second margin time, the transfer request is executed after the other transfer requests;
When the first margin time is smaller than the second margin time, the data transfer device sets the order of execution of the transfer request to precede the other transfer requests. 4. The data transfer device according to claim 1, wherein the first information includes a data volume to be transferred in response to the transfer request. 5. The data transfer device according to claim 1, wherein the allowable transfer time for each of the transfer requests is set to a shorter time as the priority of the transfer request increases. The data transfer device according to any one of claims 1 to 5 ;
a transfer request source that transmits the plurality of transfer requests.