JP7824086B2 - Output Circuit - Google Patents

Description

This disclosure relates to an output circuit.

AC coupling circuits are used in a variety of fields (see, for example, Patent Document 1).
The AC coupling circuit removes a direct current (DC) component from an input voltage signal and extracts an alternating current (AC) component.

For example, there is a known output circuit that outputs a voltage signal level-shifted by AC coupling using a bipolar transistor emitter follower or a MOS (Metal-Oxide-Semiconductor) transistor source follower. This output circuit outputs a digital signal using, for example, a small-amplitude voltage output method.

FIG. 3 is a diagram showing an example of a schematic configuration of an output circuit 101 according to the background art.
The output circuit 101 includes a waveform generating section 111 , a capacitor 112 , a capacitor 113 , a bias power supply 114 , a resistor 115 , a transistor 116 , a power supply 117 , an output terminal 118 , and a resistor 119 .
The connections of these circuit elements are similar to those of the corresponding parts of the output circuit 1 shown in FIG. 1, and detailed description thereof will be omitted here.

Japanese Patent Application Publication No. 5-14166

However, the output circuit 101 shown in Figure 3 has the problem of generating so-called sags in the output waveform. Sags represent, for example, momentary voltage drops.

This will be explained in detail.
FIG. 4A is a diagram showing an example of an input waveform 2011 of the output circuit 101 according to the background art.
FIG. 4B is a diagram showing an example of an output waveform 2012 of the output circuit 101 according to the background art.
In the graphs shown in FIGS. 4A and 4B, the horizontal axis represents time, and the vertical axis represents level (voltage level).

Here, the input waveform 2011 is exemplified as the same waveform as the input waveform 1011 shown in FIG. 2(A).
Also shown in Figure 4B is an offset voltage 2021. In the examples of Figures 3 and 4, the offset voltage 2021 is the same as the offset voltage 1021 shown in Figure 2A.

In the output circuit 101 shown in FIG. 3, when the digital signal to be processed is high frequency, the waveform is not distorted.
However, in the output circuit 101, when the digital signal to be processed is equal to or less than the time constant of the AC coupling, a sag occurs in the flat portions of the high level (H) and low level (L) of the waveform (for example, a square wave), as shown in Fig. 4(B). For this reason, the output circuit 101 could not be used at low frequencies.
Such a sag occurs when the charge stored in the capacitor 112 is released.

This disclosure was made in consideration of these circumstances, and aims to provide an output circuit that can suppress the occurrence of sags in the output waveform.

One aspect of the present invention relates to a circuit unit including: a bias power supply; a first resistor; a first capacitor; a second capacitor constituting an AC coupling circuit for an input waveform; a transistor which is either a first transistor constituted by a bipolar transistor having a base connected to the second capacitor and an output terminal connected to an emitter, or a second transistor constituted by a MOS transistor having a gate connected to the second capacitor and an output terminal connected to a source; and a circuit unit which is provided in parallel with the second capacitor and is constituted by a series connection of a third capacitor which is a parallel capacitor and a second resistor which is a parallel resistor, wherein one end of the bias power supply is connected to ground, the other end of the bias power supply is connected to one end of the first resistor, one end of the first capacitor is connected to ground, and the other end of the first resistor and the other end of the first capacitor are connected between the base of the first transistor and the second capacitor when the transistor is the first transistor, or between the gate of the second transistor and the second capacitor when the transistor is the second transistor, and the capacitance of the first capacitor is represented by C1 _and the capacitance of the second capacitor is represented by C2. When the capacitance of the third capacitor is represented by C2, _the resistance value of the first resistor is represented by R1 _{, and} the resistance value of the second resistor is represented by R2, the output circuit is set so that {C2 _/ ( _C1 + _C2 ) _} ={R1 _/ (R1 ₊ R2 ₎ } and C3 _>> (C1 ₊ C2 ₎ .

This disclosure makes it possible to prevent sags from occurring in the output waveform in the output circuit.

FIG. 2 is a diagram illustrating an example of a schematic configuration of an output circuit according to an embodiment. 1A is a diagram showing an example of an input waveform of an output circuit according to an embodiment, and FIG. 1B is a diagram showing an example of an output waveform of an output circuit according to an embodiment. FIG. 1 is a diagram illustrating an example of a schematic configuration of an output circuit according to the background art. 1A is a diagram showing an example of an input waveform of an output circuit according to the background art, and FIG. 1B is a diagram showing an example of an output waveform of an output circuit according to the background art.

Embodiments of the present disclosure will be described below with reference to the drawings.

[Output circuit]
FIG. 1 is a diagram showing an example of a schematic configuration of an output circuit 1 according to an embodiment.
The output circuit 1 comprises a waveform generating section 11, a first capacitor 13, a second capacitor 12, a bias power supply 14, a first resistor 15, a transistor 16, a power supply 17, an output terminal 18, a third resistor 19, and a circuit section 21.
The circuit section 21 includes a third capacitor 31 and a second resistor 32 .

1 has a configuration in which a circuit unit 21 is added to the output circuit 101 shown in Fig. 3. Note that the parameters of each circuit element (for example, capacitance or resistance value) may be different between the output circuit 1 shown in Fig. 1 and the output circuit 101 shown in Fig. 3.
In the example of FIG. 1, the second capacitor 12 is used to form an AC coupling circuit.

1, a waveform generating section 11 generates a waveform of an input signal (input waveform). As the waveform, for example, a square wave (which may also be called a rectangular wave) is used.
For example, the waveform generating section 11 may generate an input waveform under control of a circuit external to the output circuit 1 .
In the example of FIG. 1, a bipolar transistor is used as the transistor 16 .

The connection relationships of the circuit elements in the output circuit 1 will be described.
One end of the waveform generating section 11 is connected to the ground.
The other end of the waveform generating section 11 is connected to one end of the second capacitor 12 and one end of the third capacitor 31 .
The other end of the third capacitor 31 is connected to one end of the second resistor 32 .
One end of the first capacitor 13 is connected to the ground.

One end of the bias power supply 14 (the negative side in the example of FIG. 1) is connected to the ground.
The other end (positive side in the example of FIG. 1) of the bias power supply 14 and one end of the first resistor 15 are connected.
The other end of the second capacitor 12, the other end of the first capacitor 13, the other end of the first resistor 15, the other end of the second resistor 32, and the base of the transistor 16 are connected together.

The power supply 17 and the collector of the transistor 16 are connected.
One end of the third resistor 19 is connected to the ground.
The emitter of the transistor 16 is connected to the other end of the third resistor 19. An output terminal 18 is provided between the emitter of the transistor 16 and the other end of the third resistor 19.

The capacitance of the first capacitor 13 is represented by _C1 .
The capacitance of the second capacitor 12 is represented as _C2 .
The capacitance of the third capacitor 31 is represented by _C3 .
The resistance value of the first resistor 15 is represented as _R1 .
The resistance value of the second resistor 32 is represented as _R2 .
The voltage of the input (IN) waveform (potential difference between high level (H) and low level (L)) is represented by Vi.
The offset voltage of the output (OUT) waveform is represented as V _offset .
The voltage (bias voltage) of the bias power supply 14 is represented by V _bias .
The base-emitter voltage of transistor 16 is designated _VBE .

FIG. 2A is a diagram showing an example of an input waveform 1011 of the output circuit 1 according to the embodiment.
In the example of FIG. 1, the input waveform 1011 is a waveform generated by the waveform generating section 11 .
FIG. 2B is a diagram showing an example of an output waveform 1012 of the output circuit 1 according to the embodiment.
In the example of FIG. 1, output waveform 1012 is the waveform output from output terminal 18 .
In the graphs shown in FIGS. 2A and 2B, the horizontal axis represents time, and the vertical axis represents level (voltage level).
Also shown in FIG. 2B is an offset voltage 1021 .

Here, the offset voltage V _offset is expressed by the following equation (1).

[Equation 1]
V _offset = V _bias - V _BE ... (1)

With offset voltage 1021 as the reference (center voltage), the potential difference (amplitude) between the high level (H) and low level (L) of output waveform 1012 is expressed by equation (2).

[Equation 2]
Potential difference = {C ₂ /(C ₁ +C ₂ )}・Vi...(2)

Here, the output waveform 1012 is based on the result of dividing the amplitude (voltage Vi) of the input waveform 1011 by the capacitances _C1 and _C2 .
In this embodiment, with regard to the ratio relationship shown in equation (3), the relationship between the capacitance _C1 and the capacitance _C2 and the relationship between the resistance value _R1 and the resistance value _R2 are matched.
Furthermore, the capacitance C3 is set to a large value so that it can supply charge to the capacitances C1 and C2.
It should be noted that equation (3) is an ideal equation, and in reality it may deviate slightly due to adjustments.

[Equation 3]
{C ₂ /(C ₁ +C ₂ )} = {R ₁ /(R ₁ +R ₂ )}
C ₃ >> C ₁ +C ₂
...(3)

With such settings, the output circuit 1 can compensate for sags in which the voltage of the output waveform 1012 changes obliquely relative to a constant value (high level (H) value or low level (L) value).
In the output circuit 1, for example, the charge stored in the third capacitor 31 of the circuit section 21 is injected into a waveform portion where a sag would occur if only the second capacitor 12 were present, thereby making it possible to suppress the occurrence of a sag.

Here, in the example of Figure 1, a bipolar transistor is used as the transistor 16 in the output circuit 1, and a voltage signal level-shifted by AC coupling is output by the emitter follower of the bipolar transistor, but this is not limited to this.
For example, a MOS (Metal-Oxide-Semiconductor) transistor may be used as the transistor 16 instead of a bipolar transistor. In this case, a voltage signal level-shifted by AC coupling is output by the source follower of the MOS transistor in the output circuit 1. In this case, the gate, drain, and source of the MOS transistor are arranged in place of the base, collector, and emitter of the bipolar transistor, respectively.

In the example of FIG. 1, the output circuit 1 outputs a digital signal, for example, in a small amplitude voltage output format.
As a specific example, the waveform generating section 11 may be configured using a CMOS (Complementary MOS) circuit with a large output. Even in such a case, the output circuit 1 can reduce the output by dividing the voltage between the capacitors _C2 and _C3 .
In the example of FIG. 1, in the output circuit 1, a current source may be used instead of the first resistor 15 in the circuit that generates the bias voltage (bias current).

As described above, the output circuit 1 according to this embodiment includes the circuit section 21 in which the third capacitor 31 (capacitance _C3 ) and the second resistor 32 (resistance _R2 ) are connected in series in parallel with the AC coupling capacitance (capacitance _C2 in this embodiment). By appropriately selecting the capacitance _C3 and resistance _R2 of the circuit section 21, it is possible to compensate for the sag so as to flatten the output waveform 1012.

Therefore, in the output circuit 1 according to this embodiment, the sag is compensated for, and thus the output frequency can be lowered to a low frequency range, for example.
In this way, the output circuit 1 according to this embodiment can suppress the occurrence of sag in the output waveform 1012.
In the output circuit 1 according to this embodiment, for example, it is possible to improve the sag of the waveform using a simple circuit.

For example, in conventional technology, in an output circuit of an integrated circuit that outputs an output level-shifted by AC coupling using a bipolar emitter follower or the like, when the output frequency is lowered, a sag occurs in which the flat portion of the output waveform becomes slanted due to the influence of the time constant of the AC coupling.
In contrast to this, in the output circuit 1 according to this embodiment, for example, by keeping the time constant the same value and adding a circuit consisting of a capacitance (C) and a resistance (R), the sag in the flat portion can be easily corrected to a horizontal level.

As one configuration example, the output circuit 1 includes a capacitor (in this embodiment, second capacitor 12) that forms an AC coupling circuit for the input waveform, a transistor (in this embodiment, transistor 16) that is either a first transistor (in the example of Figure 1) composed of a bipolar transistor whose base is connected to the capacitor and whose output terminal is connected to the emitter, or a second transistor (an example different from Figure 1) composed of a MOS transistor whose gate is connected to the capacitor and whose output terminal is connected to the source, and a circuit section (in this embodiment, circuit section 21) that is arranged in parallel with the capacitor and composed of a series connection of a parallel capacitor (in this embodiment, third capacitor 31) and a parallel resistor (in this embodiment, second resistor 32).

Here, the output circuit 1 according to this embodiment may be applied to, for example, an ECL (Emitter-Coupled Logic) circuit.

The above describes in detail an embodiment of this disclosure with reference to the drawings, but the specific configuration is not limited to this embodiment and includes designs that do not deviate from the gist of this disclosure.

1, 101...output circuit, 11, 111...waveform generating section, 12...second capacitor, 13...first capacitor, 31...third capacitor, 112, 113...capacitor, 14, 114...bias power supply, 15...first resistor, 19...third resistor, 32...second resistor, 115, 119...resistor, 16, 116...transistor, 17, 117...power supply, 18, 118...output terminal, 21...circuit section, 1011, 2011...input waveform, 1012, 2012...output waveform, 1021, 2021...offset voltage

Claims (1)

a bias power supply;
A first resistor;
A first capacitor;
a second capacitor that constitutes an AC coupling circuit for the input waveform;
a first transistor which is a bipolar transistor having a base connected to the second capacitor and an output terminal connected to an emitter, or a second transistor which is a MOS transistor having a gate connected to the second capacitor and an output terminal connected to a source;
a circuit section provided in parallel with the second capacitor and configured by a series connection of a third capacitor serving as a parallel capacitor and a second resistor serving as a parallel resistor;
Equipped with
One end of the bias power supply is connected to ground,
the other end of the bias power supply is connected to one end of the first resistor;
One end of the first capacitor is connected to ground,
the other end of the first resistor and the other end of the first capacitor are connected between the base of the first transistor and the second capacitor when the transistor is the first transistor, or between the gate of the second transistor and the second capacitor when the transistor is the second transistor;
When the capacitance of the first capacitor is represented by C1 _, the capacitance of the second capacitor is represented by C2 _, the capacitance of the third capacitor is represented by C3 _, the resistance value of the first resistor is represented by R1 _, and the resistance value of the second resistor is represented by _R2 ,
It is set so that {C2 _/ (C1 ₊ C2 ₎ }={R1 _/ (R1 ₊ R2 ₎ } and C3 _>> (C1 ₊ C2 ₎ ;
Output circuit.