JP7826853B2 - MEMORY SYSTEM AND DATA CORRECTING METHOD - Patent application - Google Patents

Description

The present invention relates to a memory system and a data correction method in which errors in data stored in memory are corrected by an external control unit.

Conventionally, memory systems have been known that include dynamic random access memory (DRAM) and a control unit such as a memory controller that manages the data, and that can correct bit errors (errors) when they occur in data stored in the DRAM. In this type of memory system, when the control unit writes data to the DRAM, it calculates an error correction code (ECC) corresponding to the data and stores the data and the calculated ECC in the DRAM. In addition, when the control unit reads data stored in the DRAM, it reads the data and the ECC corresponding to the data and compares them using the ECC, correcting or detecting any errors that may have occurred. For example, when an 8-bit ECC is added to 64-bit data, the control unit corrects 1-bit errors and detects 2-bit errors. The control unit overwrites the read data with the corrected data, thereby correcting the erroneous data stored in the DRAM.

In the memory system described in Patent Document 1, the control unit reads all data stored in the DRAM within a certain period of time, and if errors are detected and corrected using ECC, it performs a scrubbing process in which the corrected data is written back to the DRAM.

U.S. Patent No. 8,024,638

One type of DRAM known is one that generates and stores ECC codes internally and is also capable of autonomously performing error correction (hereafter referred to as "ECC-enabled DRAM"). ECC-enabled DRAM, for example, has a data storage area and an ECC storage area. When a read request is received from an external control unit, it reads the data and ECC from each area and, if an error is found in the data, returns the corrected data to the control unit. Because ECC-enabled DRAM can return correct data to an external control unit even if an accidental error occurs, it is used in applications that require error-resistant characteristics, such as server memory.

Here, we consider a memory system that has a control unit and ECC-compatible DRAM. Although ECC-compatible DRAM can return error-corrected data to an external control unit, it does not generally overwrite the data stored internally with corrected data, meaning that erroneous data remains in the data storage area.

However, in this memory system, the data read from the ECC-compatible DRAM is data that has been internally corrected, so the external control unit cannot detect whether an error has occurred in the data stored in the ECC-compatible DRAM. Furthermore, even if this memory system stores an ECC separately outside the ECC-compatible DRAM and performs the above-mentioned scrubbing process, the data that the external control unit reads from the ECC-compatible DRAM is corrected data, so data errors cannot be detected.

In view of the above, the present invention aims to enable error correction in a memory system using ECC-compatible DRAM, even if an error occurs in data stored in the ECC-compatible DRAM.

In order to achieve the above object, the memory system according to claim 1 comprises a memory unit (3) having a data storage area (31) for storing data, an ECC generation unit (32) for generating an error correction code corresponding to the data, an ECC storage area (33) for storing the error correction code generated by the ECC generation unit, and an error correction unit (34) for correcting an error in the data using the error correction code, and a control unit (2) for reading and writing data stored in the data storage area of the memory unit, wherein the control unit is configured to receive a scrubbing process from a scrubbing process circuit (4) for executing a scrubbing process on the memory unit , and to receive an access request from the scrubbing process circuit and an error correction process from another unit different from the control unit. and an arbitration circuit (5) that arbitrates between access requests from the area to the memory unit, and in the scrubbing process, data stored in the memory unit is read and the read data is written back to the memory unit as is, and if there is a write request from another area to a predetermined address range in the data storage area of the memory unit between the read request from the scrubbing process circuit and the next write request, and the predetermined address range includes at least a part of the address range corresponding to the read request from the scrubbing process circuit to the memory unit, the arbitration circuit performs a process of suspending the write request from the other area until the write process based on the write request from the scrubbing process circuit is completed.

This memory system comprises a memory unit capable of internally and autonomously correcting errors, and a control unit that processes reading and writing data stored in the data storage area of the memory unit. The data read by the control unit is written back to the memory unit as is. Even if an error occurs in the data read by the control unit from the memory unit, the data has been corrected by the error correction unit within the memory unit, and is therefore expected to be error-free and correct. The data with an error stored in the memory unit is then written back as is using the corrected data read by the control unit, i.e., the correct data, returning it to the state it was in before the error occurred. Therefore, by using a memory unit that internally and autonomously corrects errors, such as ECC-compatible DRAM, this memory system is capable of correcting the data to be correct even if the control unit cannot detect an error in the data stored in the memory unit.

A data correction method according to claim 4 is a data correction method for correcting errors in data in a memory system comprising: a storage unit (3) having a data storage area (31) for storing data, an ECC generation unit (32) for generating an error correction code corresponding to the data, an ECC storage area (33) for storing the error correction code generated by the ECC generation unit , and an error correction unit (34) for correcting an error using the error correction code when an error occurs in the data; a scrubbing processing circuit (4) for performing scrubbing processing of the storage unit; and a control unit (2) having an arbitration circuit (5) for arbitrating between an access request from the scrubbing processing circuit to the storage unit and an access request from another area different from the control unit, and for reading and writing data stored in the data storage area of the storage unit, wherein the control unit periodically scrubs the data storage area of the storage unit. the control unit reads a portion of the data in the data storage area in one read request and holds the portion of the data until the next write request; the control unit writes the portion of the data read by the immediately preceding read request directly to the same address in the data storage area where the portion of the data is stored in one write request; and if, between the read request from the scrubbing processing circuit and the next write request, there is a write request from another area to a predetermined address range in the data storage area of the memory unit, and the predetermined address range includes at least a part of the address range corresponding to the read request from the scrubbing processing circuit to the memory unit, the arbitration circuit performs processing to suspend the write request from the other area until the write processing in accordance with the write request from the scrubbing processing circuit is completed .

This error correction method corrects data in a memory system that includes a storage unit capable of internally and autonomously correcting errors, and a control unit that processes reading and writing data stored in a data storage area of the storage unit. In one read request, the control unit reads and stores a portion of the data in the data storage area, and in the next write request, writes the portion of the data stored in the previous read request directly to the same address in the storage unit. Because the storage unit is configured to perform error correction autonomously, the data read by the control unit in one read request is expected to be correct data without errors, and by writing this "correct data" directly, the data storage area stores data with the error corrected. This method makes it possible to correct erroneous data in the storage unit, even in memory systems that use storage units that internally and autonomously correct errors, such as ECC-compatible DRAM.

Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described below.

1 is a block diagram illustrating a memory system according to an embodiment. FIG. 2 is a block diagram illustrating an example of the configuration of a storage unit used in the memory system. FIG. 2 is a block diagram illustrating a configuration example of a DRAM controller. FIG. 2 is a block diagram showing an example of the configuration of a scrubbing processing circuit. 10 is a flowchart illustrating an example of a scrubbing process according to the embodiment. 10 is a flowchart illustrating an example of processing in an arbitration circuit.

Embodiments of the present invention will be described below with reference to the accompanying drawings. Note that in the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

(Embodiment)
A memory system 1 according to an embodiment will be described with reference to the drawings.

[Basic configuration]
1, the memory system 1 includes a control unit 2 and a storage unit 3, and is suitable for use in applications requiring robustness against errors, such as data processing for business servers, driving assistance in vehicles, or periphery monitoring in autonomous driving, etc. The memory system 1 is not limited to the above applications, and can also be used in various other applications.

As shown in FIG. 1, the control unit 2 includes multiple DRAM masters 21, a DRAM controller 22, and a bus 23, and the DRAM controller 22 is capable of exchanging various signals and data with the DRAM masters 21 and the memory unit 3. The control unit 2 is, for example, an SoC, an integrated circuit that integrates various functional circuits such as a processor, CPU, and GPU on a single semiconductor chip. SoC, CPU, and GPU are abbreviations for "System on a Chip," "Central Processing Unit," and "Graphics Processing Unit," respectively.

The DRAM master 21 is a processing block that requires memory, such as a processor, CPU, or GPU. The DRAM master 21 is connected to the DRAM controller 22 via the bus 23. The number and type of DRAM masters 21 can be changed as appropriate depending on the application of the memory system 1.

The DRAM controller 22 is connected to the external storage unit 3 and performs read and write operations on various data stored in the storage unit 3. For ease of explanation, the process of the DRAM controller 22 reading data from the storage unit 3 will be referred to as "read," and the process of writing data to the storage unit 3 will be referred to as "write." The DRAM controller 22 performs read and write operations on various data required for arithmetic processing in the DRAM master 21 from the storage unit 3, for example. Furthermore, as a scrubbing process independent of the aforementioned read and write operations, the DRAM controller 22 reads all data stored in the storage unit 3 at regular intervals and writes the read data directly to the same address in the storage unit 3. Details of the DRAM controller 22 will be described later.

The fixed period for one scrubbing process by the control unit 2 is arbitrary and is set appropriately depending on the data capacity of the storage unit 3, the purpose of the memory system 1, etc.

The memory unit 3 is an ECC-compatible DRAM, and is, for example, a recording medium that records various data used in arithmetic processing in the DRAM master 21. As shown in FIG. 3, the memory unit 3 includes a data storage area 31, an ECC generation unit 32, an ECC storage area 33, and an error correction unit 34. The ECC generation unit 32 generates an ECC corresponding to the data to be stored in the data storage area 31, and stores the generated ECC in the ECC storage area 33. For example, when the DRAM controller 22 issues a read request for data stored in the data storage area 31, the memory unit 3 reads the ECC corresponding to the data from the ECC storage area 33. If the error correction unit 34 detects an error using the ECC in the data requested to be read by the DRAM controller 22, the memory unit 3 corrects the data and returns the corrected data to the DRAM controller 22. In other words, the memory unit 3 is configured to correct a single-bit error that can be corrected in the data requested to be read and output the corrected data, but is not able to autonomously overwrite the data stored in the data storage area 31 with the error-corrected data. Furthermore, if no error has occurred in the data requested to be read, the memory unit 3 outputs the data as is.

The above is the basic configuration of the memory system 1 according to the embodiment. In the memory system 1, the control unit 2 reads all data stored in the data storage area 31 of the memory unit 3 (ECC-compatible DRAM) within a certain period of time, and then writes the read data directly to the original area. In other words, even if an error occurs in the data stored in the data storage area 31 of the memory unit 3, the memory system 1 is configured so that the corrected data output from the memory unit 3 is written directly to the original area. As a result, the memory system 1 prevents erroneous data from being stored in the data storage area 31 for a long period of time, and ultimately prevents uncorrectable data errors of two or more bits from occurring, making it highly error-resistant.

[DRAM Controller]
Next, the DRAM controller 22 will be described in detail.

As shown in FIG. 3, the DRAM controller 22 includes a scrubbing processing circuit 4, an arbitration circuit 5, and a protocol generation circuit 6.

The scrubbing processing circuit 4 issues read and write requests for all data stored in the memory unit 3 within a fixed period of time, and writes the data read from the memory unit 3 directly to the same area. As shown in FIG. 4, the scrubbing processing circuit 4 includes an address generation unit 41, an access request unit 42, and a data storage unit 43.

The address generation unit 41 sequentially generates address values in the data storage area 31 of the memory unit 3. For example, during scrubbing processing, the address generation unit 41 sequentially generates address values in ascending order at intervals equal to the amount of data in one read.

For ease of explanation, the amount of data read in one scrubbing process will be referred to as the "read data amount" below.

Specifically, for example, if the data capacity of the storage unit 3 is 8 GB (gigabytes) and the amount of read data is 512 B (bytes), the address generation unit 41 generates address values in the order of 0, 512, 1024, 1536, ..., 8589934080. In this case, when the address value reaches the value of the data capacity of the storage unit 3, the address generation unit 41 generates the first address value of "0", for example, and repeats the sequential generation of address values in the same manner as above. The address value generated by the address generation unit 41 is output to the access request unit 42, for example, and is used by the access request unit 42 in read and write requests.

The amount of read data is a preset fixed value. Furthermore, the data capacity of the storage unit 3 and the amount of data read/written per scrubbing process are not limited to the above examples, and can be changed as appropriate depending on the application of the memory system 1.

The access request unit 42 outputs to the arbitration circuit 5 an access request to the area of the data storage area 31 of the memory unit 3 that corresponds to the address value generated by the address generation unit 41. The access requests from the access request unit 42 are read and write requests for data stored in the data storage area 31. The access request unit 42 outputs access requests to the memory unit 3 to the arbitration circuit 5 at predetermined intervals so that the DRAM controller 22 can read and write all data stored in the data storage area 31 of the memory unit 3 within a certain period of time.

Hereinafter, unless otherwise specified, the terms "access request," "read request," and "write request" refer to an access request, read request, and write request to the memory unit 3.

For example, consider the case where the data capacity of the storage unit 3 is 8 GB, the amount of read data is 512 B, and it is desired to read and write all data stored in the storage unit 3 in one hour. In this case, the interval between access requests by the access request unit 42 is set to (60 x 60 x 1000 x 1000) / (16 x 1024 x 1024) = 214.6 μsec. Note that the interval between access requests by the access request unit 42 can be changed as appropriate depending on the data capacity of the storage unit 3, the amount of read data, and the fixed period required for one scrubbing process.

The data holding unit 43 is a read data buffer that temporarily holds data read from the memory unit 3 by the DRAM controller 22 based on a read request from the access request unit 42. The data capacity of the data holding unit 43 is, for example, a capacity corresponding to the amount of read data, i.e., the capacity for one data access in scrubbing processing. When a write request is made from the access request unit 42, the data holding unit 43 outputs the held data as write data. The data holding unit 43 then holds new data read from the memory unit 3 by the DRAM controller 22 in response to a read request from the access request unit 42 for the next address value until the next write request. The write data output from the data holding unit 43 is written by the DRAM controller 22 to the same area of the data storage area 31 of the memory unit 3 where the read data was stored.

The arbitration circuit 5 performs arbitration when an access request from the bus 23 conflicts with an access request from the scrubbing processing circuit 4. When access requests to the storage unit 3 from the bus 23 and the scrubbing processing circuit 4 conflict, the arbitration circuit 5 outputs one access request to the protocol generation circuit 6 and suspends the other access request until the first access request is completed. A conflict in access requests means that the address ranges in the data storage area 31 of the storage unit 3 for two or more access requests at least partially overlap. For example, the arbitration circuit 5 prioritizes the access request from the bus 23 and suspends the access request from the scrubbing processing circuit 4. However, if the address ranges for these access requests do not overlap, the arbitration circuit 5 outputs both access requests to the protocol generation circuit 6. The arbitration circuit 5 issues an access request to the protocol generation circuit 6, returns read data from the storage unit 3 to the access request source, and transmits write data received from the access request source to the storage unit 3.

For example, when there is a conflict between write requests from the bus 23 and the scrubbing processing circuit 4, and the write request from the bus 23 is between a read request and a write request from the scrubbing processing circuit 4, the arbitration circuit 5 preferably suspends the write request from the bus 23. This is because if data is written from the bus 23 to the same address in the memory unit 3 after a scrubbing processing read, the contents of the data will be rewritten, and if a scrubbing processing write is then performed, the contents of the data will differ from what was intended. The processing operation of the arbitration circuit 5 will be described later.

The protocol generation circuit 6 receives access requests to the storage unit 3 output from the arbitration circuit 5, converts the access requests into commands to be issued to the storage unit 3, and issues the commands. The protocol generation circuit 6 is a circuit that generates protocols for communication with the storage unit 3, which is ECC-compatible DRAM, and may also be referred to as a DRAM protocol generation circuit.

The above is the basic configuration of the DRAM controller 22. The DRAM controller 22 performs scrubbing processing by the scrubbing processing circuit 4 and read/write processing based on access requests from the DRAM master 21, etc.

[Scrubbing process]
Next, a description will be given of the scrubbing process of the storage unit 3 by the control unit 2. For ease of explanation, the data stored in the data storage area 31 of the storage unit 3 will be referred to as "stored data" below.

When a predetermined start condition is met, such as when the power to the memory system 1 is turned on, the control unit 2 causes the scrubbing processing circuit 4 to start the processing shown in FIG. 5. In step S110, the address generation unit 41 in the scrubbing processing circuit 4 generates an address value for the data storage area 31 of the memory unit 3 and outputs the generated address value to the access request unit 42.

Next, in step S120, the access request unit 42 outputs a read request for the address value generated in step S110 to the arbitration circuit 5. The arbitration circuit 5 then outputs the read request output from the access request unit 42 to the protocol generation circuit 6.

Next, in step S130, the protocol generation circuit 6 receives the read request from the arbitration circuit 5, converts it into a read request command to the memory unit 3, and issues it.

Then, in step S140, the DRAM controller 22 reads data from a predetermined address range in the data storage area 31 of the memory unit 3, starting from the address value generated in step S110. The address range can be changed as appropriate depending on the preset amount of data to be read.

Next, in step S150, the scrubbing processing circuit 4 receives the data read in step S140 and stores it in the data storage unit 43.

Next, in step S160, the scrubbing processing circuit 4 performs processing similar to steps S110 to S130 to request a write to the same address range in the storage unit 3 as the data read in step S140. Then, in step S150, the DRAM controller 22 outputs the data held by the data holding unit 43 as write data and performs processing to write the write data back to the area in the storage unit 3 where the read data was stored. As a result, if no error has occurred, the data stored in the storage unit 3 is overwritten by the DRAM controller 22 with the original data. On the other hand, if an error has occurred, the data stored in the storage unit 3 is overwritten by the DRAM controller 22 with "correct data" after the error correction unit 34 has corrected the error. In either case, the storage unit 3 maintains error-free stored data, which cannot be detected externally, through the read/write processing by the control unit 2, i.e., the scrubbing processing.

Then, in step S170, the control unit 2 determines whether the address value generated in step S110 has reached the value corresponding to the data capacity of the storage unit 3, i.e., the upper limit, and if the determination is affirmative, the process proceeds to step S180. On the other hand, if the determination is negative in step S170, the control unit 2 proceeds to step S190.

In step S180, the address generation unit 41 generates the first address value (e.g., 0). The control unit 2 then returns the process to step S120.

On the other hand, in step S190, the address generation unit 41 generates the next address value by adding the amount of read data to the address value generated in step S110. For example, if the address value generated in step S110 is "0" and the amount of read data is "512B," in step S190 the address generation unit 41 generates an address value of "512." The control unit 2 then returns the process to step S120.

The control unit 2 performs the above process on all stored data in the memory unit 3 within a set, predetermined period of time. As a result, all stored data is read from and written back to the memory unit 3 at regular intervals, and even if an error occurs in the stored data for some reason, the corrected data is written back. Therefore, even when using a memory unit 3 that cannot be directly detected by the external control unit 2, such as ECC-compatible DRAM, the memory system 1 can prevent data containing uncorrectable errors of two or more bits from being retained.

[Arbitration circuit]
Next, the arbitration process in the arbitration circuit 5 will be described.

The arbitration circuit 5 executes the process shown in Figure 6, for example, in parallel with the scrubbing process performed by the scrubbing process circuit 4.

In step S210, the arbitration circuit 5 determines whether or not there is a write request from the bus 23, and if the determination is affirmative, the process proceeds to step S220. On the other hand, if the determination is negative in step S210, the arbitration circuit 5 returns the process to step S210.

In step S220, the arbitration circuit 5 determines whether scrubbing processing is occurring between step S120 (read request) and step S160 (data write), and if the determination is affirmative, the process proceeds to step S230. On the other hand, if the determination is negative in step S220, the arbitration circuit 5 proceeds to step S290.

In step S290, the arbitration circuit 5 executes the write request from the bus 23. The arbitration circuit 5 then returns the process to step S210.

In step S230, the arbitration circuit 5 determines whether the address range of the write request from the bus 23 overlaps with the address range of the write request in the scrubbing process, and if the determination is positive, the process proceeds to step S240. On the other hand, if the determination is negative, the arbitration circuit 5 proceeds to step S270.

In step S240, the arbitration circuit 5 prioritizes the write request in the scrubbing process and puts the write request from the bus 23 on hold. Next, in step S250, the arbitration circuit 5 waits until the write request in step S160 in the scrubbing process is issued, and once that write request is issued, executes the write request in the scrubbing process. Then, in step S260 after the write process in the scrubbing process is completed, the arbitration circuit 5 executes the write request from the bus 23 that was on hold, and returns the process to step S210.

On the other hand, in step S270, the arbitration circuit 5 executes the write request from the bus 23 without suspending it, and proceeds to step S280. Then, in step S280, the arbitration circuit 5 executes the write request in the scrubbing process, and returns to step S210.

By performing the above processing, the arbitration circuit 5 puts on hold any write requests made from the bus 23 between step S140 (data read) and step S160 (data write) in the scrubbing process that overlap with the address range of step S160. This prevents writes from the bus 23 within the overlapping address range between the read and write of stored data in the scrubbing process, preventing stored data from being replaced with unintended data due to the scrubbing process.

The memory system 1 according to the embodiment uses an ECC-compatible DRAM as the storage unit 3, and the control unit 2 reads the data stored in the storage unit 3 within a fixed period of time and writes the read data to the same address. The data stored in the storage unit 3 is not overwritten autonomously, but is output to the control unit 2 as is if no error has occurred. If a correctable single-bit error has occurred, the data is corrected using the internal ECC and output as corrected data. Since there is a high probability that the data read by the control unit 2 from the storage unit 3 is correct and free of errors, the read data can be written back to the same address range in its original form to reduce the probability of an uncorrectable error of two or more bits occurring.

Thus, this memory system 1 uses ECC-compatible DRAM, and is configured to retain the stored data as error-corrected data through scrubbing processing, even if the external control unit 2 cannot directly detect errors in the data stored in the ECC-compatible DRAM. As a result, even though the memory system 1 is configured using an SoC and ECC-compatible DRAM, it is capable of substantial error correction and is highly resistant to errors.

(Other embodiments)
Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one, or less than one, are also within the scope and spirit of the present disclosure.

The control unit 2 and the method described herein may be implemented by a special-purpose computer configured by configuring a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the control unit 2 and the method described herein may be implemented by a special-purpose computer configured by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control unit 2 and the method described herein may be implemented by one or more special-purpose computers configured by combining a processor and memory programmed to perform one or more functions with a processor configured with one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by a computer on a computer-readable non-transitory tangible recording medium.

It goes without saying that in each of the above embodiments, the elements constituting the embodiment are not necessarily essential, except when expressly stated as essential or when they are clearly considered essential in principle. Furthermore, in each of the above embodiments, when the numbers, values, amounts, ranges, etc. of the components of the embodiment are mentioned, they are not limited to that specific number, except when expressly stated as essential or when they are clearly limited to a specific number in principle. Furthermore, in each of the above embodiments, when the shape, positional relationship, etc. of the components, etc. are mentioned, they are not limited to that shape, positional relationship, etc., except when expressly stated as essential or when they are clearly limited to a specific shape, positional relationship, etc. in principle.

2: control unit, 3: memory unit, 31: data storage area, 32: ECC generation unit, 33: ECC storage area, 34: error correction unit, 4: scrubbing processing circuit, 41: address generation unit, 42: address request unit, 43: data holding unit, 5: arbitration circuit

Claims (4)

1. A memory system comprising:
a memory unit (3) having a data storage area (31) for storing data, an ECC generation unit (32) for generating an error correction code corresponding to the data, an ECC storage area (33) for storing the error correction code generated by the ECC generation unit, and an error correction unit (34) for correcting an error in the data using the error correction code;
a control unit (2) that performs processing for reading and writing the data stored in the data storage area of the storage unit,
The control unit has a scrubbing processing circuit (4) that executes a scrubbing process on the storage unit , and an arbitration circuit (5) that arbitrates between an access request to the storage unit from the scrubbing processing circuit and an access request to the storage unit from another area different from the control unit, and in the scrubbing process, reads the data stored in the storage unit and executes a process of writing the read data back to the storage unit as is ,
A memory system in which, if a write request from the other area to a specified address range of the data storage area of the memory unit is made between a read request from the scrubbing processing circuit and the next write request, and the specified address range includes at least a portion of the address range corresponding to the read request from the scrubbing processing circuit to the memory unit, the arbitration circuit performs processing to suspend the write request from the other area until the write processing due to the write request from the scrubbing processing circuit is completed . The memory system of claim 1, wherein the scrubbing processing circuit has an address generation unit (41) that sequentially generates address values for the data storage area in the memory unit, an access request unit (42) that issues read and write requests to the area corresponding to the address values, and a data holding unit (43) that holds a portion of the data read from the data storage area in response to a single read request, and issues the read and write requests for all data stored in the data storage area at predetermined intervals, and writes the portion of the data read from the memory unit to the area in the data storage area corresponding to the same address value where the portion of the data is stored. The memory system of claim 2, wherein the data retention unit retains the portion of data read by the control unit from the storage unit in response to a single read request from the access request unit at least until the next write request, and outputs the retained portion of data as write data at the time of the write request. a memory unit (3) having a data storage area (31) for storing data, an ECC generation unit (32) for generating an error correction code corresponding to the data, an ECC storage area (33) for storing the error correction code generated by the ECC generation unit, and an error correction unit (34) for correcting an error using the error correction code when an error occurs in the data ;
A data correction method for correcting errors in data in a memory system including a scrubbing circuit (4) that performs scrubbing of the storage unit, an arbitration circuit (5) that arbitrates between an access request from the scrubbing circuit to the storage unit and an access request from another area different from the control unit to the storage unit, and a control unit (2) that performs processing for reading and writing the data stored in the data storage area of the storage unit, comprising:
the control unit issues a read request and a write request for all data stored in the data storage area of the storage unit at predetermined intervals;
In one read request, the control unit reads part of the data in the data storage area and holds the part of the data until the next write request;
In one write request, the part of the data read in the immediately preceding read request is written directly to the same address in the data storage area where the part of the data is stored ;
a data correction method including: if, between a read request from the scrubbing processing circuit and a next write request, there is a write request from the other area to a predetermined address range of the data storage area of the memory unit, and the predetermined address range includes at least a portion of the address range corresponding to the read request from the scrubbing processing circuit to the memory unit, the arbitration circuit performs a process of suspending the write request from the other area until the write process based on the write request from the scrubbing processing circuit is completed .