JP7827293B2 - Gate drive circuit - Google Patents

Description

The present invention relates to a gate drive circuit used in power conversion circuits such as inverters, rectifiers, and DC/DC converters.

Power devices using wide bandgap semiconductors such as SiC MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) and GaN HEMTs (High Electron Mobility Transistors) are capable of high-speed switching, i.e., a large voltage change rate (dv/dt). By utilizing this feature, power conversion circuits can reduce switching losses and increase the carrier frequency, thereby reducing the volume of ripple removal filters. However, as the voltage change rate (dv/dt) increases, common-mode noise on the transmission path that transmits control signals also increases, which can cause gate drive circuits to malfunction.

A typical countermeasure to this problem is to use optical isolators in the signal isolation section to minimize the stray capacitance of the transmission path that transmits the control signal, thereby suppressing common-mode noise. However, optical isolators cause large jitter in signal transmission, making it difficult to achieve the switching operation of several hundred kHz to several MHz expected of wide bandgap devices. In response to this, jitter can be reduced by using magnetically coupled or capacitively coupled signal isolators. However, because the stray capacitance of the transmission path that transmits the control signal increases compared to when optical isolators are used, this increases the common-mode noise superimposed on the transmission path during high-speed switching, resulting in the problem of noise generation in the gate drive signal.

Figure 1 shows an example of a conventional gate drive circuit that generates a gate drive signal. In this example, a signal processor that generates and outputs the gate drive signal is isolated from the gate driver, gate resistor, MOSFET, and other components by a signal isolator. This signal processor includes a synchronization signal generator that generates a synchronization signal (e.g., a peak signal indicating the timing of a counter's maximum value and a bottom signal indicating the timing of its minimum value) from a clock CLK, a reference generator that generates a reference value in response to the synchronization signal, a buffer for holding the reference value, a carrier generator that generates a carrier signal, such as a triangular wave, in response to the clock CLK, and a comparator that compares the reference value output by the buffer with the carrier signal output by the carrier generator. The signal processor can be implemented using a microprocessor, a programmable logic device such as an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device), or a logic circuit such as a CMOS (Complementary Metal Oxide Semiconductor) or a TTL (Transistor-Transistor Logic), or a combination of these.

The operation of the gate drive circuit shown in Figure 1 will be explained using Figure 2. The reference value is assumed to be a value between 0 and 1, and the carrier signal, which is a triangular wave, also has a value between 0 and 1. The reference value output by the buffer is updated at the times when the carrier signal reaches its maximum and minimum. Specifically, the reference generator begins calculating the reference value at time t1, when the carrier signal reaches its minimum, and completes the calculation at time t2. The calculated reference value is temporarily stored in the buffer, and at time t3, when the carrier signal reaches its maximum, the buffer outputs the stored reference value to the comparator. At time t3, the reference generator begins calculating the next reference value, and completes the calculation at time t4. The calculated reference value is temporarily stored in the buffer, and at time t5, when the carrier signal reaches its minimum, the buffer outputs the stored reference value to the comparator. This process continues in the same manner. The reference value compared to the carrier signal by the comparator is a discrete value, and is delayed by half a cycle of the carrier signal. The comparator compares the magnitude of the carrier signal with a reference value; if the carrier signal is greater, the gate drive signal remains an off signal (L); if the reference value is greater, the gate drive signal remains an on signal (H). The signal processor in such conventional gate drive circuits always transmits the gate drive signal via a signal isolator.

Figure 3 shows an example configuration when such a conventional gate drive circuit is applied to a step-down chopper. In the example of Figure 3, the step-down inductance is assumed to be sufficiently large, and the load is represented as a constant current source I. In the example of Figure 3, the reference potential on the primary side of the gate drive circuit is GND1. Meanwhile, on the secondary side, the source terminal voltage of the MOSFET is set to reference potential GND2. Generally, a stray capacitance C of several pF to several hundred pF exists between different, isolated reference potentials (here, between GND1 and GND2).

The operation of such a gate drive circuit will be explained using Figure 4. This shows the gate signal being switched from OFF (L) to ON (H) at time t6. After a turn-on delay, the MOSFET's drain-source voltage v1 drops at time t7. At this time, according to Kirchhoff's voltage law, the diode voltage v2 begins to rise. Meanwhile, considering that the voltage applied to the stray capacitance C of the signal isolator is equal to the diode voltage v2, as the diode voltage v2 rises from time t7 to time t8, a common-mode current of C (dv2/dt) flows from GND2 to GND1.

Magnetic coupling and capacitive coupling signal isolators can malfunction due to the flow of such common mode currents. For example, if an off signal (L) is erroneously output due to a malfunction caused by a common mode current, even though an on signal (H) is being input to the signal isolator, the MOSFET will erroneously turn off. Malfunctions in signal isolators become particularly pronounced when high-speed switching is performed using wide bandgap devices, as the common mode current is proportional to the voltage change rate (dv/dt).

U.S. Patent No. 6,111,454

J. Wang, S. Mocevic, R. Burgos and D. Boroyevich, “High-Scalability Enhanced Gate Drivers for SiC MOSFET Modules With Transient Immunity Beyond 100 V/ns,” in IEEE Transactions on Power Electronics, vol. 35, no. 10, pp. 10180-10199, Oct. 2020.

Therefore, one object of the present invention is to provide a gate drive circuit that can suppress malfunctions even when performing high-speed switching.

A gate drive circuit according to one aspect of the present invention includes a first circuit, a second circuit, and a signal isolator for isolating and transmitting a signal from the first circuit to the second circuit, the first circuit including a reference generator for generating a reference value, a first buffer for holding the reference value, and a synchronization signal generator for generating a synchronization signal for synchronizing the first circuit and the second circuit, and the second circuit including a second buffer for holding the reference value transmitted from the first buffer in the first circuit via the signal isolator, a carrier generator for generating a carrier signal synchronized with the synchronization signal transmitted from the first circuit via the signal isolator, and a comparator for comparing the reference signal output by the second buffer with the carrier signal output by the carrier generator to output a gate drive signal.

According to one aspect, a gate drive circuit can be provided that can suppress malfunctions even when performing high-speed switching.

FIG. 1 is a diagram showing an example of a circuit according to the prior art. FIG. 2 is a diagram for explaining the operation of a circuit of the prior art. FIG. 3 shows an example of an application of a prior art circuit. FIG. 4 shows waveforms of voltage, current and gate drive signals in an application of the prior art circuit. FIG. 5 is a diagram showing a gate drive circuit according to the first embodiment. FIG. 6 is a diagram for explaining the operation of the gate drive circuit according to the first embodiment. FIG. 7 is a diagram for explaining the operation of the gate drive circuit according to the first embodiment. FIG. 8 is a diagram for explaining the operation of the gate drive circuit according to the first embodiment. FIG. 9 is a diagram showing a gate drive circuit according to the second embodiment. FIG. 10 is a diagram for explaining the operation of the gate drive circuit according to the second embodiment. FIG. 11 is a diagram for explaining the operation of the gate drive circuit according to the second embodiment. FIG. 12 is a diagram showing a gate drive circuit according to the second embodiment. FIG. 13 is a diagram showing an example of a circuit for generating a plurality of gate drive signals. FIG. 14 is a diagram showing an example of an experimental circuit. FIG. 15 is a diagram showing various voltage, current and signal waveforms when a gate drive signal generated by a circuit of the prior art is used. FIG. 16 is a diagram showing various voltage, current and signal waveforms when the gate drive signal generated by the gate drive circuit according to the first embodiment is used.

[First Embodiment]
An example of the configuration of a gate drive circuit according to this embodiment is shown in Fig. 5. As shown in Fig. 5, in this embodiment, a circuit 1 that generates a reference value (also called a command value) and a circuit 2 that generates a gate drive signal based on the reference value are connected and insulated by signal isolators 1 and 2, and the gate of a MOSFET or the like is driven by the gate drive signal via a gate driver and a gate resistor.

Circuit 1 is provided with a signal processor 1, which includes a synchronization signal generator 1, a reference generator, and a buffer 1. Synchronization signal generator 1 counts up, for example, from 0 to 1 in response to clock signal clk1 on the circuit 1 side. When the count value reaches 1, it outputs synchronization signal Peak1. Conversely, when the count value reaches 1, it counts down to 0 and outputs synchronization signal bottom1 when the count value reaches 0. Synchronization signals peak1 and bottom1 are output to the reference generator and buffer 1, and are also output to circuit 2 via signal isolator 2. The reference generator begins calculating a reference value for each of synchronization signals peak1 and bottom1, and outputs the calculated reference value to buffer 1. Buffer 1 measures timing using clock signal clk1 and synchronization signals Peak1 and Bottom1, holds the reference value output from the reference generator, and outputs it to circuit 2 via signal isolator 1.

Signal isolators 1 and 2 are, for example, magnetically coupled or capacitively coupled signal isolators based on their responsiveness. Furthermore, signal processors 1 and 2 are implemented, as in the past, by microprocessors, programmable logic devices such as FPGAs or CPLDs, or logic circuits such as CMOS or TTL, or a combination of these.

Circuit 2 is provided with a signal processor 2, which includes a buffer 2, a synchronization signal generator 2, a carrier generator, and a comparator. Synchronization signal generator 2 counts up, for example, from 0 to 1 in response to clock signal clk2 from circuit 2, and outputs synchronization signal Peak2 when the count value reaches 1. Conversely, when the count value reaches 1, it counts down to 0 and outputs synchronization signal Bottom2 when the count value reaches 0. However, because clock signals clk1 and clk2 are not synchronized, synchronization signal generator 2 adjusts the timing at which the count value reaches 1 or 0 in response to at least one of synchronization signals Peak1 and Bottom1 transmitted via signal isolator 2. Buffer 2 holds the reference value transmitted via signal isolator 1 and switches the reference value to be output to the next reference value in response to at least one of synchronization signals Peak2 and Bottom2 from synchronization signal generator 2. The carrier generator outputs a count value, for example, counting up from 0 to 1 in response to clock signal clk2. When the count value reaches 1, it counts back down to 0, outputting a triangular wave carrier signal. Note that because clock signals clk1 and clk2 are not synchronized, the carrier generator also adjusts the timing at which the count value reaches 1 and 0 in response to synchronization signals peak1 and bottom1 transmitted via signal isolator 2. The comparator compares the carrier signal with a reference value; if the carrier signal is greater than the reference value, the gate drive signal is set to an off signal (L); if the reference value is equal to or greater than the carrier signal, the gate drive signal is set to an on signal (H).

Figure 6 shows a time chart of the processing of signal processors 1 and 2 shown in Figure 5. In Figure 6, as shown in the second row, the period during which the counter value of synchronization signal generator 1 first counts up is designated n, the period during which it next counts down is designated n+1, and the period thereafter increases by one. As shown in the first row of Figure 6, when period n begins at time t9, the reference generator begins calculating the reference value. After completing calculation of the reference value at time t10, the reference value is output to buffer 1, as indicated by the arrow in Figure 6. Buffer 1 transmits the reference value to circuit 2 via signal isolator 1, as indicated by the arrows in the third and fourth rows of Figure 6. Here, buffer 1 transmits the reference value from time t10 to time t11. During period n+1, the reference value is calculated by the reference generator from time t12 to time t13, and the reference value is output to buffer 1 at time t13. From time t13 to time t15, buffer 1 outputs the reference value to circuit 2 via signal isolator 1.

As shown in the fifth row of Figure 6, if Circuit 1 and Circuit 2 are synchronized, Buffer 2 receives and holds the reference value transmitted via Signal Isolator 1 during Period n. Buffer 2 outputs the reference value it received and held during Period n-1 during Period n (times t9 to t12). Therefore, when Period n+1 begins at time t12, Buffer 2 outputs the reference value it received and held during Period n. Therefore, as shown in the sixth row of Figure 6, the reference value changes with each period. On the other hand, as shown in the seventh row of Figure 6, if Circuit 1 and Circuit 2 are synchronized, the carrier generator outputs a carrier signal that increases from time t9 and decreases from time t12. As shown in the eighth row of Figure 6, the comparator compares the reference value with the carrier signal. If the carrier signal is greater than the reference value, the comparator turns off the gate drive signal. If the carrier signal is equal to or less than the reference value, the comparator turns on the gate drive signal. It operates in the same way during other periods.

In this way, transmitting the reference value via a signal isolator completes communication in a shorter time than conventional technology, which always transmits gate drive signals via a signal isolator, making it less susceptible to malfunctions in the signal isolator. For example, if the reference value is transmitted from Buffer 1 to Buffer 2 using 32-bit, 100 MHz serial communication, the time required to transmit the reference value (t11 - t10) is 0.32 μs (= 32/100 MHz). Therefore, during one cycle of the carrier signal, a significant signal passes through Signal Isolator 1 for only 2 x 0.32 = 0.64 μs.

Even if the period during which a significant signal is transmitted is shortened in this way, depending on the reference value, the gate drive signal may change during communication from Buffer 1 to Buffer 2. In the example of Figure 6, there is no change in the gate drive signal from time t10 to time t11 in period n, but a change occurs in the gate drive signal at time t14 between time t13 and time t15 in period n+1. In such a case, there is a possibility that Signal Isolator 1 may malfunction, so the output timing of the reference value is adjusted in Buffer 1.

Specifically, as shown in Figure 7, Buffer 1 delays the timing of outputting the reference value. In Figure 7, period n+1 begins at time t16, but even if Buffer 1 receives the reference value from the reference generator at time t17, it delays outputting the reference value until time t17 to t19. As a result, even if the gate drive signal changes at time t18 between times t17 and t19, Buffer 1 can start outputting the reference value from time t19, allowing the reference value to be transmitted via Signal Isolator 1 without being affected by changes in the gate drive signal.

In any period i to i+1 (iεn, n±1, n±2 . . . ), the buffer 1 delays the output of the reference value only when the following formula is satisfied:
T _C <t _sw,i ≦T _C +T _t (1)
Note that _TC is the time required to calculate the reference value and is obtained from a simulation of a microprocessor or programmable logic. _Tt is the time required to transmit the reference value and is calculated as described above. In FIG. 7, _TC and _Tt are shown for period n. _tsw is also shown as the period from the start of period n. Thus, condition (1) is not satisfied in period n.

On the other hand, t _sw,i is the switching time in period i, and the point at which calculation of the reference value starts is expressed as t = 0. The switching time is calculated from the intersection of the carrier signal and the reference value (or the intersection of the counter value of the synchronization signal generator 2 and the reference value) as follows:
t _sw,i = (1-D _i-1 )/2f _sw (2)
Here, f _sw is the carrier frequency, and D _i-1 is the reference value for period i-1. That is, the reference value to be compared with the carrier signal is the reference value calculated one period before, and is therefore D _i-1 .

Therefore, buffer 1 determines whether equation (1) is satisfied, and if it is determined that it is not satisfied, it outputs the reference value immediately upon receiving it from the reference generator. On the other hand, if it determines that equation (1) is satisfied, it outputs the reference value after t _sw,i expressed by equation (2) has elapsed from the start of period i. Note that the transfer of the reference value is completed before the calculation of the next reference value is started, i.e., before the start of the next period.

Next, using Figure 8, we will explain the synchronization between circuit 1 and circuit 2. Synchronization signal generator 1 counts up and down as shown in the first row of Figure 8, generating synchronization signals peak1 and bottom1 as shown in the second and third rows of Figure 8, which are transmitted to circuit 2 via signal isolator 2 as shown in the fourth row of Figure 8. Synchronization signal generator 2 and carrier generator count up and down like the carrier signal shown in the fifth row of Figure 8, but change their count value to a maximum value (e.g., 1) upon receiving synchronization signal peak1 and to a minimum value (e.g., 0) upon receiving synchronization signal bottom1. That is, synchronization signal generator 2 outputs synchronization signal peak2 upon receiving synchronization signal peak1 and outputs synchronization signal bottom2 upon receiving synchronization signal bottom1. Furthermore, the carrier generator changes the count value that becomes the carrier signal to a maximum value upon receiving synchronization signal peak1 and to a minimum value upon receiving synchronization signal bottom1. In the example of Figure 8, at time t21, the count value is adjusted to a minimum value of 0 in response to synchronization signal bottom1, at time t22, the count value is adjusted to a maximum value of 1 in response to synchronization signal peak1, at time t23, the count value is adjusted to a minimum value of 0 in response to synchronization signal bottom1, and at time t24, the count value is adjusted to a maximum value of 1 in response to synchronization signal peak1.

In this way, synchronization is possible even in a configuration in which signal processors 1 and 2 are isolated by signal isolators 1 and 2. Strictly speaking, the period on circuit 1 and the period on circuit 2 are not simultaneous, but the above configuration allows a correspondence between period n on circuit 1 and period n on circuit 2, and for the sake of explanation, they are shown in the diagram as being simultaneous.

In the above example, the synchronization signals peak1 and bottom1 are transmitted from circuit 1 to circuit 2, but it is also possible to transmit only one of them. In this case, circuit 2 adjusts the count value based on the reception timing of one of the signals.

Furthermore, since some of the functions of the synchronization signal generator 2 and carrier generator overlap, they may be integrated.

[Embodiment 2]
In the first embodiment, the influence of the gate drive signal on the signal isolator 2 was not taken into consideration. However, there may be an influence if the timing of the synchronization signals peak1 and bottom1 transmitted from the circuit 1 via the signal isolator 2 overlaps with the timing of the signal change in the gate drive signal. Specifically, if the reference value is small (close to 0 in the above example), the timing at which the synchronization signal bottom1 is output may overlap with the timing of the signal change in the gate drive signal. If the reference value is large (close to 1 in the above example), the timing at which the synchronization signal peak1 is output may overlap. Therefore, in this embodiment, such a problem is addressed by adopting the configuration described below.

The configuration of the gate drive circuit of this embodiment is shown in Figure 9. Circuit 1 is the same as in the first embodiment, but there is a change in signal processor 2 of circuit 2. Specifically, buffer 2 immediately outputs the reference value to synchronization signal generator 2 and carrier generator within the same period in which it received the reference value. Based on the received reference value, synchronization signal generator 2 and carrier generator determine whether either synchronization signal peak1 or bottom1 will be affected by changes in the gate drive signal in the next period. If affected, they do not make adjustments based on the affected synchronization signal peak1 or bottom1, but make adjustments based on the other synchronization signal peak1 or bottom1. For example, if the count value is between 0 and 1, and the reference value received in a certain period is less than 0.1, synchronization signal bottom1 may be affected. Therefore, in the next period, adjustments based on synchronization signal bottom1 are not made, but adjustments are made in response to the reception of synchronization signal peak1. Additionally, if the reference value received during a certain period exceeds 0.9, there is a possibility that it may affect the synchronization signal peak1, so adjustments will not be made based on the synchronization signal peak1 during the next period, but will be made in response to the reception of the synchronization signal bottom1. In all other cases, regardless of whether the synchronization signal peak1 or bottom1 arrives during the next period, adjustments will be made based on that synchronization signal.

Figure 10 shows an example of using only synchronization signal peak1. In the example of Figure 10, the reference value received in period n-1 is, for example, less than 0.1, so the gate drive signal is on only for a short period when the carrier signal value is also small. Times t25 to t26, when synchronization signal bottom1 is transmitted via signal isolator 2, fall within the time period when the gate drive signal is on. Therefore, if the reference value received in period n-1 is less than 0.1, the count value is not adjusted based on synchronization signal bottom1 in the next period n. On the other hand, since the reference value received in period n does not exceed 0.9, the count value is adjusted based on synchronization signal peak1 at time t27 in period n+1. Similarly, since the reference value received in period n+1 is, for example, less than 0.1, times t28 to t29, when synchronization signal bottom1 is transmitted via signal isolator 2, fall within the time period when the gate drive signal is on. Therefore, if the reference value received in period n+1 is less than 0.1, the count value will not be adjusted based on synchronization signal bottom1 in the next period n+2. However, since the reference value in period n+2 does not exceed 0.9, the count value will be adjusted based on synchronization signal peak1 at time t30 in period n+3.

Figure 11 shows an example of using only synchronization signal bottom1. In the example of Figure 11, the reference value received in period n-1 exceeds 0.9, for example, so the count value is adjusted based on synchronization signal bottom1 at time t31 in period n. Meanwhile, the reference value received in period n exceeds 0.9, and the gate drive signal is turned off for a short period when the carrier signal value also increases. Times t32 to t33, when synchronization signal peak1 is transmitted via signal isolator 2, fall within the time period when the gate drive signal is off. Therefore, if the reference value received in period n exceeds 0.9, the count value is not adjusted based on synchronization signal peak1 in the next period n+1. Similarly, since the reference value received in period n+1 exceeds 0.9, the count value is adjusted based on synchronization signal bottom1 at time t34 in period n+2. Furthermore, the reference value received in period n+2 exceeds 0.9, for example, so times t35 to t36, when synchronization signal peak1 is transmitted via signal isolator 2, fall within the time period when the gate drive signal is off. Therefore, if the reference value received in period n+2 exceeds 0.9, the count value will not be adjusted based on the synchronization signal peak1 in the next period n+3.

Note that adjusting the count value of synchronization signal generator 2 may result in the count value reaching the maximum or minimum value consecutively. Therefore, if the same type of synchronization signal is input multiple times, buffer 2 operates to ignore the second and subsequent synchronization signals. For example, if synchronization signal peak1 is received after the count value of synchronization signal generator 2 has exceeded its maximum value, synchronization signal generator 2 will again set the count value to its maximum value. In this case, synchronization signal generator 2 will output synchronization signal peak2 twice in a row, but buffer 2 will ignore the second synchronization signal peak2.

[Modification of the Second Embodiment]
In the second embodiment, the buffer 2 outputs a reference value to the synchronization signal generator 2 and the carrier generator, and each determines whether or not to receive the synchronization signals peak1 and bottom1 based on the reference value, but the buffer 2 may determine whether or not to receive the synchronization signals peak1 and bottom1 based on the reference value, and output a synchronization signal selection signal EN to the synchronization signal generator 2 and the carrier generator. For example, an example of a gate drive circuit configured in this way is shown in Figure 12.

In the example of Figure 13, a synchronization signal selection signal EN is output from buffer 2 to synchronization signal generator 2 and carrier generator. When buffer 2 receives the reference value via signal isolator 2, it immediately determines whether the reference value is less than 0.1 or greater than 0.9. If the reference value is less than 0.1, it outputs a selection signal EN that selects only synchronization signal peak1. If the reference value exceeds 0.9, it outputs a selection signal EN that selects only synchronization signal bottom1. Otherwise, it outputs a selection signal EN that selects both synchronization signals peak1 and bottom1.

When the synchronization signal generator 2 and carrier generator receive a selection signal EN that selects only synchronization signal peak1, they adjust their own count values using only synchronization signal peak1; when they receive a selection signal EN that selects only synchronization signal bottom1, they adjust their own count values using synchronization signal bottom1 only; and when they receive a selection signal EN that selects synchronization signals peak1 and bottom1, they adjust their own count values using synchronization signals peak1 and bottom1.

[When generating multiple gate drive signals]
Fig. 13 shows an example of the configuration of a gate drive circuit that generates two gate drive signals for two MOSFETs or the like. In Fig. 13, signal processor 2 that generates gate drive signal 1 is the signal processor 2 in the embodiment described above, and signal processor 3 that generates gate drive signal 2 has the same configuration as signal processor 2 in the embodiment described above. Meanwhile, signal processor 1 has an additional buffer 3 for signal processor 3 in addition to buffer 1 for signal processor 2, and the reference generator generates reference value 1 that is accumulated in buffer 2 and transmitted to signal processor 2 via signal isolator 1, and reference value 2 that is accumulated in buffer 3 and transmitted to signal processor 3 via signal isolator 3. Note that synchronization signal generator 1 outputs synchronization signals peak1 and bottom1 (peak and bottom in Fig. 13) in the same way as in the embodiment described above.

In this way, the signal processor 1 is provided with buffers equal to the number of gate drive signals to be generated, and the reference generator generates reference values equal to the number of gate drive signals to be generated. Furthermore, it is sufficient to provide a secondary signal processor 2 equal to the number of gate drive signals to be generated.

[About the effects]
An experiment was conducted using a step-down chopper as shown in Figure 14. Specifically, the gate drive signal 1 for the upper arm was always an off signal (L), and the gate drive signal 2 for the lower arm was generated using either the conventional circuit shown in Figure 1 or the circuit according to this embodiment (e.g., Figure 5) and had a double-pulse waveform. The voltage vsig represents the voltage of the gate drive signal, the voltage vg represents the output voltage of the gate driver, and the voltage vds represents the drain-source voltage. The DC power supply was set to 500 V. As a result, the drain-source voltage vds was 0 V when on and 500 V when off. Furthermore, when the gate drive signal was an on (H) signal, vsig = 5 V, and when it was an off (L) signal, vsig = 0 V. The output voltage of the gate driver was vg = 19 V when on and vg = -5 V when off. Rg represents the gate resistance, Rg = 3.3 Ω.

Figure 15 shows experimental results when gate drive signal 2 was generated using the conventional circuit shown in Figure 1 and output to the circuit shown in Figure 15. More specifically, the results show 200 overlapping measurements of vds, vsig, and vg for a double-pulse waveform. The turn-off trigger was provided by changing the gate drive signal vsig from 5 V to 0 V. As a result, the drain-source voltage vds increased, and then ringing occurred in the gate drive signal vsig. Focusing on the gate driver output voltage vg, after the turn-off trigger, the gate driver output voltage should have remained at vg = -5 V, but it temporarily increased. This is thought to be due to common-mode noise causing the signal isolator to malfunction, resulting in ringing in the gate drive signal, which in turn generated an erroneous on signal and turned on the gate driver erroneously. As a result, the drain-source voltage temporarily decreased, and the MOSFET also turned on erroneously.

Meanwhile, Figure 16 shows experimental results when gate drive signal 2 was generated using the circuit of this embodiment shown in Figure 5 and output to the circuit shown in Figure 14. More specifically, the results show 200 overlapping measurements of vds, vsig, and vg for a double pulse waveform. A turn-off trigger was given by changing the gate drive signal vsig from 5V to 0V. This significantly reduced the ringing that occurred in the gate drive signal vsig after turn-off. As a result, the gate driver output voltage also remained in the off state. In other words, the gate driver did not erroneously turn on. As a result, the drain-source voltage did not erroneously turn on. In other words, common-mode noise can now be handled.

Although the embodiments of the present invention have been described above, the present invention is not limited to these. For example, it is possible to delete any technical feature of each embodiment, or to combine any technical feature of any embodiment.

The above-described embodiments can be summarized as follows:

A gate drive circuit according to a first aspect of this embodiment includes a first circuit, a second circuit, and a signal isolator for isolating and transmitting a signal from the first circuit to the second circuit. The first circuit includes a reference generator for generating a reference value, a first buffer for holding the reference value, and a synchronization signal generator for generating a synchronization signal for synchronizing the first circuit and the second circuit. The second circuit includes a second buffer for holding the reference value transmitted from the first buffer in the first circuit via the signal isolator, a carrier generator for generating a carrier signal synchronized with the synchronization signal transmitted from the first circuit via the signal isolator, and a comparator for comparing the reference signal output by the second buffer with the carrier signal output by the carrier generator to output a gate drive signal.

In this way, the signal that passes through the signal isolator becomes a reference value and synchronization signal, and the reference value can be transmitted in a shorter time than when transmitting a gate drive signal, which makes it possible to suppress the adverse effects that the gate drive signal generated on the second circuit side has on the signal that passes through the signal isolator (i.e., the reference value).

The first buffer described above may hold the reference value generated by the reference generator for a certain period and transmit it to the second circuit via a signal isolator, and the second buffer may hold the reference value transmitted from the first buffer in the first circuit via the signal isolator for a period corresponding to the certain period, and output the reference value transmitted and held during the certain period in the period following the period corresponding to the certain period. This double-buffer configuration allows the reference value to be transmitted at the appropriate timing.

Furthermore, the first buffer described above may be configured to output a reference value after receiving the reference value from the reference generator during the certain period, avoiding the time when the gate drive signal changes. This makes it possible to suppress the adverse effects of the gate drive signal on signals passing through the signal isolator. Note that since the time when the gate drive signal changes can be predicted from the reference value in the previous period, if the time when the reference value is output overlaps with the time when the gate drive signal changes, it may be configured to be delayed until after the time when the gate drive signal changes.

Furthermore, the synchronization signal mentioned above may be at least one of a first signal representing the timing of the maximum value of the carrier signal and a second signal representing the timing of the minimum value of the carrier signal. Such a synchronization signal takes less time to pass through the signal isolator and is less susceptible to the influence of the gate drive signal.

In addition, when the synchronization signal described above includes a first signal and a second signal, the carrier generator described above may adjust the carrier signal based on the received signals by switching between receiving only the first signal, only the second signal, or both the first and second signals in the period following the reference value received by the second buffer during a certain period. This allows synchronization between the first circuit and the second circuit to be achieved in a manner that avoids adverse effects from the gate drive signal.

Furthermore, when the synchronization signal described above includes a first signal and a second signal, the second buffer described above may determine, based on a reference value received during a certain period, whether reception of only the first signal, only the second signal, or both the first and second signals is appropriate during the period following the certain period, and output a selection signal representing the appropriate signal to the carrier generator. In this case, the carrier generator described above may switch between reception of only the first signal, only the second signal, or both the first and second signals based on the selection signal from the second buffer, and adjust the carrier signal based on the received signal. Even with this configuration, synchronization between the first circuit and the second circuit can be achieved while avoiding adverse effects from the gate drive signal.

Furthermore, the above-mentioned carrier generator may be configured to adjust the value of the carrier signal to its maximum value when a first signal is received, and to adjust the value of the carrier signal to its minimum value when a second signal is received.

Furthermore, the second circuit described above may further include a second synchronization signal generator that generates a second synchronization signal synchronized with the synchronization signal transmitted from the first circuit via the signal isolator. In this case, the second buffer is configured to output a reference value to the comparator in response to the second synchronization signal from the second synchronization signal generator.

A gate drive circuit according to a second aspect of this embodiment includes a first circuit, a second circuit, and a signal isolator for isolating and transmitting a signal from the first circuit to the second circuit. The first circuit includes a reference generator for generating a reference value and a first buffer for holding the reference value, and the second circuit includes a second buffer for holding the reference value transmitted from the first buffer in the first circuit via the signal isolator, a carrier generator for generating a carrier signal, and a comparator for comparing the reference signal output by the second buffer with the carrier signal output by the carrier generator and outputting a gate drive signal.

In this way, the reference value transmitted via the signal isolator can be transmitted in a shorter time than when transmitting the gate drive signal, thereby suppressing the adverse effects that the gate drive signal generated on the second circuit side may have on the signal passing through the signal isolator (i.e., the reference value).

Note that various methods are possible for synchronizing the first circuit and the second circuit, and are not limited to the embodiment described above.

Claims (8)

a first circuit;
a second circuit; and
a signal isolator for isolating and transmitting a signal from the first circuit to the second circuit;
and
The first circuit comprises:
a reference generator for generating a reference value;
a first buffer for holding the reference value;
a synchronization signal generator that generates a synchronization signal for synchronizing the first circuit and the second circuit;
and
The second circuit includes:
a second buffer for holding the reference value transmitted from the first buffer in the first circuit through the signal isolator;
a carrier generator that generates a carrier signal synchronized with the synchronization signal transmitted from the first circuit through the signal isolator;
a comparator that compares the reference signal output by the second buffer with the carrier signal output by the carrier generator and outputs a gate drive signal;
A gate drive circuit having: the first buffer holds the reference value generated by the reference generator for a certain period of time and transmits the reference value to the second circuit via the signal isolator;
2. The gate drive circuit according to claim 1, wherein the second buffer holds the reference value transmitted from the first buffer in the first circuit via the signal isolator during a period corresponding to the certain period, and outputs the reference value transmitted during the certain period and held during a period next to the period corresponding to the certain period. 3. The gate drive circuit according to claim 2, wherein the first buffer outputs the reference value in such a manner as to avoid a time when the gate drive signal changes after receiving the reference value from the reference generator during the certain period. 2. The gate drive circuit according to claim 1, wherein the synchronization signal is at least one of a first signal representing the timing of the maximum value of the carrier signal and a second signal representing the timing of the minimum value of the carrier signal. When the synchronization signal includes the first signal and the second signal,
The carrier generator includes:
5. The gate drive circuit according to claim 4, wherein the second buffer adjusts the carrier signal based on the received signal by switching between receiving only the first signal, receiving only the second signal, and receiving both the first and second signals in a period following the certain period based on the reference value received in the certain period. When the synchronization signal includes the first signal and the second signal,
The second buffer comprises:
determining whether reception of only the first signal, reception of only the second signal, or reception of both the first and second signals is appropriate in a period following the certain period based on the reference value received in the certain period, and outputting a selection signal representing the appropriate signal to the carrier generator;
The carrier generator includes:
5. The gate drive circuit according to claim 4, wherein the gate drive circuit switches between receiving only the first signal, receiving only the second signal, and receiving both the first and second signals based on the selection signal from the second buffer, and adjusts the carrier signal based on the received signal. The carrier generator includes:
adjusting the value of the carrier signal to a maximum value when the first signal is received;
The gate drive circuit according to claim 4 , wherein when the second signal is received, the value of the carrier signal is adjusted to a minimum value. The second circuit includes:
a second synchronization signal generator that generates a second synchronization signal synchronized with the synchronization signal transmitted from the first circuit through the signal isolator;
3. The gate drive circuit according to claim 2, wherein the second buffer outputs the reference value to the comparator in response to a second synchronization signal from the second synchronization signal generator.