JP7831395B2 - Semiconductor circuit manufacturing method - Google Patents

Description

This disclosure relates to a method for manufacturing semiconductor circuits using silicon carbide (hereinafter also referred to as "SiC") semiconductor devices.

Conventionally, there are SiC semiconductor devices in which MOSFETs (abbreviation for Metal Oxide Semiconductor Field Effect Transistor) are formed as switching elements for semiconductor circuits. This SiC semiconductor device is formed, for example, using an n ⁺ type SiC substrate. An ^n- type buffer layer with a lower impurity concentration than the SiC substrate is formed on the SiC substrate, and an ^n- type drift layer with a lower impurity concentration than the buffer layer is formed on the buffer layer. A p- type base layer is placed on the drift layer, and an n ⁺ type source region is formed on the surface of the base layer. Multiple trenches are formed so as to penetrate the source region and the base layer and reach the drift layer, and a gate insulating film and a gate electrode are formed sequentially in each trench.

In this way, a trench gate structure MOSFET is constructed. In a SiC semiconductor device in which such a MOSFET is formed, a built-in diode is constructed by a pn junction between the base layer and the drift layer.

In this type of SiC semiconductor device, basal plane dislocations (hereinafter referred to as "BPDs") exist in the SiC substrate, and these BPDs are the cause of electrical characteristic fluctuations. Specifically, the driving of the built-in diode causes defects to expand into the epitaxial layer starting from the BPDs, reducing the current flow during energization. This results in fluctuations in the electrical characteristics of the SiC semiconductor device.

To suppress these electrical characteristic fluctuations, Patent Document 1 describes a circuit configuration in which a SiC semiconductor device is provided, adjusting the on-voltage of a freewheeling diode connected in parallel with the MOSFET to prevent large currents from flowing through the MOSFET's built-in diode.

Japanese Patent Publication No. 2021-069221

However, the technology described in Patent Document 1 attempts to reduce stress on the built-in diode by modifying the circuit configuration, i.e., by reducing the amount of current and temperature applied. This makes it difficult to suppress fluctuations in electrical characteristics when stress is applied.

This disclosure aims to provide a method for manufacturing a semiconductor circuit using a SiC semiconductor device that can suppress fluctuations in electrical characteristics when stress is applied to the built-in diode.

One aspect of this disclosure is,
A method for manufacturing a semiconductor circuit incorporating a plurality of SiC semiconductor devices (10) having switching elements that include built-in diodes (BDs) formed using a SiC substrate (11),
The selection of SiC semiconductor devices to be incorporated into a semiconductor circuit is based on a parameter that represents the acceleration of the fluctuations in electrical characteristics caused by the current flowing to the built-in diode,
This includes manufacturing semiconductor circuits by incorporating selected SiC semiconductor devices.

In this way, SiC semiconductor devices are selected for incorporation into semiconductor circuits based on parameters representing fluctuation acceleration. This makes it possible to suppress fluctuations in the electrical characteristics of the SiC semiconductor device when stress is applied to its built-in diodes, compared to randomly selecting SiC semiconductor devices.

The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later.

This is a cross-sectional view of a MOSFET formed on a SiC semiconductor device used in a semiconductor circuit according to the first embodiment. This is an explanatory diagram of the current path in a SiC semiconductor device. This is an explanatory diagram of defect growth caused by BPD near the built-in diode. This figure shows the relationship between BPD density and the change in on-resistance ΔVon. This figure illustrates the relationship between stress on the built-in diode and the acceleration of fluctuations. This chart shows a list of numerical values corresponding to the fluctuation acceleration characteristics of SiC semiconductor devices. Figure 6A is a chart of a list sorted according to the magnitude of the numerical values corresponding to the variable acceleration. This is a circuit diagram showing an example of a semiconductor circuit in which MOSFETs are connected in parallel. This is a circuit diagram showing an example of a semiconductor circuit in which MOSFETs are connected in series. This is a diagram showing the in-plane distribution of BPD density for each wafer. This is a histogram of the BPD density for each chip in a SiC semiconductor device. This graph plots the relationship between BPD densities when two SiC semiconductor devices are randomly selected. Figure 11 shows a diagram illustrating the degree of imbalance in electrical characteristic fluctuations and the magnitude of these fluctuations. This figure shows a preferred relationship for the BPD density of two SiC semiconductor devices when MOSFETs are connected in parallel. This figure shows a preferred relationship for the BPD density of two SiC semiconductor devices when MOSFETs are connected in series.

The embodiments of this disclosure will be described below with reference to the drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

(First Embodiment)
The first embodiment will be described with reference to the drawings. In this embodiment, a representative example will be described in which a semiconductor circuit is configured using a SiC semiconductor device 10 on which an inverting type MOSFET with a trench gate structure is formed as a switching element, as shown in Figure 1. The SiC semiconductor device 10 is configured such that the region on which the MOSFET shown in Figure 1 is formed is a cell region, and an outer peripheral region (not shown) is provided on which an outer peripheral breakdown structure such as a guard ring is formed to surround the cell region. The SiC semiconductor device 10, which is provided with these cell region and outer peripheral region, is made into a semiconductor chip and incorporated into a semiconductor circuit.

For the sake of explanation, as shown in Figure 1, one direction in the planar direction of the SiC substrate 11 (described later) will be referred to as the "X-axis direction," the direction perpendicular to the X-axis direction in that planar direction will be referred to as the "Y-axis direction," and the direction perpendicular to that planar direction, i.e., the XY plane, will be referred to as the "Z-axis direction."

[Configuration of SiC semiconductor 10]
The SiC semiconductor device 10 is formed using, for example, an n ⁺ type SiC substrate 11. As the SiC substrate 11, for example, a substrate is used that has an off-angle of 0 to 8° with respect to the (0001) Si plane, has an n-type impurity concentration of 1.0 × ^10¹⁹ /cm³ ^such as nitrogen and phosphorus, and has a thickness of about 300 μm. In this embodiment, the SiC substrate 11 constitutes the drain region.

An n ^- type buffer layer 12 made of SiC is formed on the surface of the SiC substrate 11. The buffer layer 12 is formed as needed and can be omitted. The buffer layer 12 is constructed by epitaxial growth on the surface of the SiC substrate 11. The buffer layer 12 has a lower impurity concentration than the SiC substrate 11; for example, the n-type impurity concentration is between that of the SiC substrate 11 and the low-concentration layer 13 described later, and its thickness is about 1 μm.

On the surface of the buffer layer 12, an n ^- type low-concentration layer 13 made of SiC is formed, for example, ^with an n-type impurity concentration of 5.0 to 10.0 × ^10¹⁵ /cm³ and a thickness of about 10 to 15 μm. The low-concentration layer 13 may have a constant impurity concentration in the Z-axis direction, but it is preferable that the concentration distribution is sloped so that the SiC substrate 11 side of the low-concentration layer 13 has a higher concentration than the side away from the SiC substrate 11. This low-concentration layer 13 is also composed of an epitaxial layer grown by epitaxial growth.

On the low-concentration layer 13 in the cell region, a current-dispersing layer 14 and a deep layer 15 are formed.

The current-dispersing layer 14 is composed of, for example, an n-type impurity layer with a thickness of 0.5 to 2 μm. The n-type impurity concentration of the current-dispersing layer 14 is, for example, 1.0 × ^10¹⁶ to 5.0 × ^10¹⁷ / ^cm³ . The current-dispersing layer 14 is connected to the low-concentration layer 13. Therefore, the low-concentration layer 13 and the current-dispersing layer 14 constitute a drift layer.

The deep layer 15 is formed in the cell region, and for example, the p-type impurity concentration is set to 2.0 × ^10¹⁷ to 2.0 × ^10¹⁸ / ^cm³ , and its thickness is equal to that of the current dispersion layer 14.

The current distribution layer 14 and the deep layer 15 are arranged in a layout where multiple layers are alternately arranged in the Y-axis direction, with the Y-axis direction being the longitudinal direction. The formation pitch of the current distribution layer 14 and the deep layer 15 is matched to, for example, the formation pitch of the trench gate structure described later, and the deep layer 15 is formed to sandwich the trench 19, which will be described later.

A p-type base layer 16 is formed on the current dispersion layer 14 and the deep layer 15. An n ⁺ -type source region 17 and a p ⁺ -type contact region 18 are formed on the surface of the base layer 16 in the cell region. The source region 17 is formed in contact with the side surface of the trench 19, which will be described later, and the contact region 18 is formed on the opposite side of the trench 19, with the source region 17 in between. The source region 17 corresponds to the impurity region.

The base layer 16 has, for example, a p-type impurity concentration of 3.0 × ^10¹⁷ / ^cm³ or less. The source region 17 has an n-type impurity concentration in the surface layer, i.e., a surface concentration of 1.0 × ^10²¹ / ^cm³ . The contact region 18 constitutes a high-concentration region in the surface layer of the base layer 16, and has a p-type impurity concentration in the surface layer, i.e., a surface concentration of 1.0 × ^10²¹ / ^cm³ .

As described above, the semiconductor portion of the SiC semiconductor device 10 has a structure in which the SiC substrate 11, buffer layer 12, low-concentration layer 13, current-dispersing layer 14, deep layer 15, base layer 16, source region 17, contact region 18, etc. are stacked. Hereinafter, the side of the semiconductor portion of the SiC semiconductor device 10 facing the source region 17 and contact region 18 will be referred to as "side 10a" of the SiC semiconductor device 10, and the side facing the SiC substrate 11 will be referred to as "other side 10b" of the SiC semiconductor device 10.

In the SiC semiconductor device 10, multiple trenches 19 with a width of 1.4 to 2.0 μm are formed in the cell region, for example, penetrating from one surface 10a through the base layer 16 to reach the current dispersion layer 14, with the bottom surface located within the current dispersion layer 14.

The trenches 19 are formed in a stripe pattern, for example, with multiple trenches extending along the Y-axis and arranged at equal intervals along the X-axis. The trenches 19 are formed so as to be sandwiched between the deep layers 15 when viewed from the normal direction of the SiC substrate 11. Furthermore, the trenches 19 are formed such that, for example, the distance between the centers of adjacent trenches 19, i.e., the trench pitch, is 3.0 μm or less.

The trench 19 is embedded, for example, by a gate insulating film 20 formed on its inner wall surface and a gate electrode 21 made of doped Poly-Si formed on the surface of the gate insulating film 20. This constitutes a trench gate structure. While not particularly limited, the gate insulating film 20 is formed, for example, by thermal oxidation or CVD on the inner wall surface of the trench 19. CVD stands for chemical vapor deposition. The gate insulating film 20 has a thickness of approximately 100 nm on both the side and bottom surfaces of the trench 19.

The gate insulating film 20 is also formed on surfaces other than the inner wall surface of the trench 19. Specifically, the gate insulating film 20 is formed to cover, for example, a portion of the surface of the source region 17 on one surface 10a of the SiC semiconductor device 10. In other words, the gate insulating film 20 has contact holes 20a formed in a portion different from the portion where the gate electrode 21 is located, exposing the contact region 18 and the rest of the source region 17.

The gate insulating film 20 is also formed on the surface of the base layer 16 in the outer peripheral region (not shown). Similarly, the gate electrode 21 extends to the surface of the gate insulating film 20 in the outer peripheral region (not shown), in the same manner as the gate insulating film 20. The trench gate structure of this embodiment is configured as described above.

An interlayer insulating film 22 is formed on one surface 10a of the SiC semiconductor device 10, covering the gate electrode 21, gate insulating film 20, etc. The interlayer insulating film 22 is composed of, for example, BPSG. BPSG is an abbreviation for Borophosphosilicate Glass.

The interlayer insulating film 22 has contact holes 22a that communicate with the contact holes 20a, exposing the source region 17 and the contact region 18. The pattern of the contact holes 22a is arbitrary, but for example, it can be a line along the longitudinal direction of the trench 19.

A source electrode 23 is formed on the interlayer insulating film 22, electrically connected to the source region 17 and the contact region 18 through contact holes 20a and 22a. The source electrode 23 is also connected to a contact region 18 formed on the surface of the base layer 16 (not shown) in the outer peripheral region.

A drain electrode 24 is formed on the other side 10b of the SiC semiconductor device 10, which is electrically connected to the SiC substrate 11. In this way, an n-channel, inverted trench-gate MOSFET is constructed. Furthermore, a built-in diode BD is formed within the MOSFET by a pn junction between a low-concentration layer 13 and a base layer 16, etc.

The above is a basic configuration example of the SiC semiconductor device 10. As will be described later, the SiC semiconductor device 10 can be used as a semiconductor circuit, for example, in an inverter circuit for driving a three-phase motor using MOSFETs as switching elements, or in a circuit for driving a DC load. Of course, its applications are not limited to these, and it can be applied to other uses as well.

[Defective growth caused by BPD]
As described above, the SiC semiconductor device 10 has a structure in which a trench gate MOSFET and a built-in diode BD composed of a pn junction are provided in the cell region. BPDs are present in the SiC substrate 11, buffer layer 12, and drift layer, and defects caused by these BPDs can occur in the SiC semiconductor device 10.

The equivalent circuit of the SiC semiconductor device 10 is shown in Figure 2 as a circuit configuration having a MOSFET and an internal diode BD, and when the MOSFET is turned on, an on current I _ON is generated from the drain electrode 24 to the source electrode 23. In Figure 2, "S", "D", and "G" correspond to the source electrode 23, drain electrode 24, and gate electrode 21, respectively. Specifically, when a predetermined voltage such as 20V is applied to the gate electrode 21, a channel is formed on the surface of the base layer 16 that is in contact with the trench 19, and an on current I _ON flows between the source electrode 23 and the drain electrode 24.

Subsequently, when the SiC semiconductor device 10 is turned off, a reverse bias is applied, causing it to conduct in reverse. As a result, the built-in diode BD functions as a freewheeling diode, and a freewheeling current I _OFF flows through the built-in diode BD. At this time, as shown in the left diagram of Figure 3, holes diffused from the p-type layer side to the n-type layer side of the pn junction constituting the built-in diode BD recombine with electrons in the n-type layer. Because the recombination energy of these holes and electrons is large, the BPD expands, as shown in the right diagram of Figure 3, resulting in a stacking fault D. This stacking fault D expands as the stress on the built-in diode BD increases. Hereafter, such a stacking fault D will be simply referred to as "defect D". This defect D interferes with the on-current I _ON and the freewheeling current I _OFF . Furthermore, because the defect D expands in response to the stress on the built-in diode BD, the electrical characteristics after operation deteriorate compared to the electrical characteristics immediately after manufacturing, i.e., before the defect D occurs.

[Effects of electrical characteristic fluctuations caused by BPD]
It has been confirmed that the change in electrical characteristics caused by current flow to the built-in diode BD originates from the BPD contained in the SiC substrate 11. Furthermore, the amount of change in electrical characteristics caused by current flow to the built-in diode BD (hereinafter referred to as the current flow change) changes depending on the BPD density contained in the element.

The in-plane distribution of BPD density in the SiC substrate 11 differs from wafer to wafer. Therefore, when SiC semiconductor device chips 10 are randomly selected for incorporation into a semiconductor circuit, the current fluctuation amount of each SiC semiconductor device 10 will vary. In other words, there will be variations in the degree of increase in current fluctuation amount for the same stress (hereinafter referred to as fluctuation acceleration). This means that even with the same semiconductor circuit, the current fluctuation amount of the selected SiC semiconductor device 10 will vary, leading to large variations in the reliability of the semiconductor circuit and potentially causing reliability design problems. Based on this, the inventors have found that in order to ensure the reliability of semiconductor circuits using SiC semiconductor devices 10, it is necessary to select the SiC semiconductor device 10 to be incorporated into the semiconductor circuit according to its fluctuation acceleration.

[Method for manufacturing semiconductor circuits]
The following describes the manufacturing method of semiconductor circuits, along with the manufacturing method of the SiC semiconductor device 10 incorporated into the semiconductor circuit. However, since the formation of trench gate structure MOSFETs and the like can be done by known SiC semiconductor manufacturing processes, these details are omitted in this specification.

First, in order to select the SiC semiconductor device 10 to be incorporated into the semiconductor circuit according to its fluctuation acceleration characteristic, the fluctuation acceleration characteristic of the SiC semiconductor device 10 is quantified.

The variable acceleration characteristic varies depending on the configuration and usage conditions of the SiC semiconductor device 10, and can be quantified based on parameters representing these characteristics. Specifically, since the variable acceleration characteristic is primarily determined by the BPD density and the hole density when current is applied to the built-in diode BD, these are used as parameters related to the variable acceleration characteristic to quantify it.

In particular, a strong correlation between BPD density and electrical characteristic fluctuations has been confirmed. When the change in the on-resistance Von of MOSFETs (ΔVon) after energizing MOSFETs in SiC semiconductor devices 10 with different BPD densities under predetermined conditions was examined, the results shown in Figure 4 were obtained.

BPD density is the basis for the formation of defects D through expansion. BPD density can be derived by cutting multiple wafers constituting the SiC substrate 11 from a SiC ingot, forming etch pits on the cut wafers by KOH (potassium hydroxide) etching, and counting the etch pits. Alternatively, BPD density can be derived by image recognition and quantification using X-ray topology or PL (photoluminescence) imaging on the wafer-shaped SiC substrate 11. In the case of KOH etching, since it is a destructive test that directly etches the wafer-shaped SiC substrate 11, it is performed on wafers cut at both ends of the growth direction of the crystal-grown SiC ingot. For wafers cut inside the growth direction beyond the inspected ends, the BPD density is estimated by interpolation based on the inspection results of the wafers at both ends. In the case of X-ray topology or PL imaging, since it is a non-destructive test, it is possible to inspect all wafer-shaped SiC substrates 11 cut from the SiC ingot, allowing for accurate quantification of BPD density.

High hole density can contribute to the expansion of defects D. Specifically, when the hole density exceeds a predetermined threshold, the expansion of defects D begins, and after exceeding the threshold, the rate of variation changes according to the magnitude of the hole density. The main factors influencing hole density include process factors such as the impurity concentration and film thickness of the buffer layer 12, the impurity concentration of the SiC substrate 11, and the impurity concentration of the current dispersion layer 14. The introduction of hole trap defects by ion implantation also determines the magnitude of the hole density. Furthermore, the hole density depends on whether the SiC ingot from which the wafer constituting the SiC substrate 11 is extracted is grown using sublimation recrystallization or gas growth, and also on the SiC ingot or wafer manufacturer. Manufacturers also exhibit a consistent trend in BPD density.

The hole density can be derived using TCAD simulation. Alternatively, although the hole density itself cannot be directly measured, a correlation between the hole density obtained from sim and Qrr is known, and since Qrr is measurable, the hole density can be quantified by measuring Qrr. Regarding the hole density, if a sample manufactured using the same manufacturing process as the SiC semiconductor device 10 is prepared and measured beforehand, the measured values of that sample can be used even before MOSFETs and other components are fabricated onto the wafer-shaped SiC substrate 11.

Next, the variable acceleration of each SiC semiconductor device 10 is quantified using at least one of the parameters representing the variable acceleration, such as BPD density or hole density, and these quantifications are listed. For example, the variable acceleration can be quantified by substituting these values into a function equation that uses BPD density or hole density as parameters. For instance, the variable acceleration in response to stress on the built-in diode BD, i.e., current flow and temperature, has the relationship shown in Figure 5. The smaller the BPD density, the higher the impurity concentration and film thickness of the buffer layer 12, and the higher the impurity concentration of the current dispersion layer 14 and SiC substrate 11, the smaller the variable acceleration in response to stress, as shown by arrow A1 in the figure. Conversely, the larger the BPD density, the lower the impurity concentration and film thickness of the buffer layer 12, and the lower the impurity concentration of the current dispersion layer 14 and SiC substrate 11, the larger the variable acceleration in response to stress, as shown by arrow A2 in the figure. Based on these relationships, the variable acceleration can be quantified by setting a function equation that uses BPD density or hole density as parameters.

Then, after quantifying the data, a list is created that associates the chip number of each SiC semiconductor device 10 with a numerical value indicating the fluctuation acceleration, as shown in Figure 6A, for example. The chip number indicates the location of the chip on the wafer constituting the SiC substrate 11.

Subsequently, as shown in Figure 6B, the list is sorted based on the numerical value indicating the variable acceleration, and then the SiC semiconductor devices 10 are grouped according to the magnitude of the variable acceleration value. For example, they can be divided into four groups in order of magnitude. The first group has a value of 1000 or less and minimal variable acceleration; the second group has a value of 3000 or less and small variable acceleration; the third group has a value of 5000 or less and medium variable acceleration; and the fourth group has a value exceeding 5000 and large variable acceleration. Of course, sorting is not mandatory at this stage; it would suffice to simply assign a group number corresponding to the chip number of each SiC semiconductor device 10.

Here, we have set multiple threshold values (1000, 3000, 5000) for grouping, but these values can be set arbitrarily. Alternatively, based on the total number of SiC semiconductor devices 10, the groups could be divided as follows: the first group (smallest to largest value), the second group (smallest to largest value), the third group (smallest to largest value), and so on. The proportions within each group can be constant or varied. Furthermore, the number of groups can be other than four, such as three.

The materials are then grouped in this manner. Next, a semiconductor manufacturing process is carried out on the SiC substrate 11 in wafer form to create the various components that make up MOSFETs, etc. These components are then diced to produce individual SiC semiconductor devices 10 chips. Finally, based on the grouped list, the SiC semiconductor devices 10 to be used when manufacturing semiconductor circuits are selected.

Specifically, the SiC semiconductor device 10 is selected according to the connection configuration of the MOSFETs in the semiconductor circuit.

For example, in order to achieve the high-current applications that have been progressing in recent years, MOSFETs 31a and 32a provided in multiple SiC semiconductor devices 10 may be connected in parallel to form a drive circuit for a load 33, as shown in the semiconductor circuit in Figure 7. Note that the built-in diodes 31b and 32b are connected in parallel to each of the MOSFETs 31a and 32a.

In such cases, to prevent the semiconductor circuit from being composed solely of SiC semiconductor devices 10 with high fluctuation acceleration, at least one group with a lower fluctuation acceleration value than the other groups is selected. That is, SiC semiconductor devices 10 are selected in combination of those with low fluctuation acceleration, or a combination of those with low and high fluctuation acceleration, so that only SiC semiconductor devices 10 with high fluctuation acceleration are not selected. If the devices are grouped into four groups as described above, the goal is to prevent a situation where all SiC semiconductor devices 10 are selected solely from the fourth group, which has the highest fluctuation acceleration value.

Furthermore, in the semiconductor circuit constituting the inverter 50 used for driving the three-phase motor 40 shown in Figure 8, switching elements are connected in series in each phase. Specifically, MOSFETs 51a to 56a provided in multiple SiC semiconductor devices 10 are used as switching elements for the upper arms 51, 53, and 55 and lower arms 52, 54, and 56 of each of the UVW phases, and MOSFETs 51a to 56a are connected in series in each phase. Note that built-in diodes 51b to 56b are connected in parallel to each of the MOSFETs 51a to 56a.

When connecting multiple SiC semiconductor devices 10 in series in this manner, the selection process ensures that SiC semiconductor devices 10 with similar fluctuation acceleration characteristics are selected. For example, within each group, the selection range is limited to devices within the same group or adjacent groups, preventing the selection of SiC semiconductor devices 10 from distant groups. If the devices are grouped into four groups as described above, all SiC semiconductor devices 10 are selected either from the fourth group or from adjacent groups, such as the first and second groups. Furthermore, selection from distant groups, such as the first and fourth groups, is prevented.

Here, we will explain the distribution of BPD density in the SiC semiconductor device 10, and the effects of randomly selecting two SiC semiconductor devices 10 and incorporating them into a semiconductor circuit without considering BPD density.

Six-inch wafers constituting the SiC substrate 11 were created by slicing a crystal-grown SiC ingot. Nine wafers were extracted from these wafers, and the in-plane distribution of BPD density was examined. A map showing this in-plane distribution was created. Figure 9 shows the results. In this figure, BPD density is shown by varying shades of gray, with darker hatching indicating higher BPD density. As shown in this figure, even wafers cut from the same ingot have different in-plane distributions of BPD density. Generally, the BPD density is low at the center of the wafer, but at the outer edge of the wafer, the BPD density varies, with some wafers showing high densities and others not so high.

Furthermore, dicing the nine extracted wafers into 9mm square chips yielded 2016 chips. The BPD density of each chip was examined and a histogram was created, resulting in Figure 10. As shown in this figure, chips with a BPD density close to zero had a high frequency, while those with a higher BPD density had a lower frequency. This indicates that while chips with low BPD densities made up the majority, chips with high BPD densities were also included.

Therefore, if two SiC semiconductor devices 10 are selected randomly without considering the variable acceleration properties, the selected SiC semiconductor device 10 will exhibit no regularity in its variable acceleration properties. Specifically, if the BPD density of the SiC substrate 11 in each of the two SiC semiconductor devices 10 is examined, and the horizontal axis is plotted with the BPD density of one of them (BPD1) and the vertical axis with the BPD density of the other (BPD2), a random plot will be obtained, as shown in Figure 11.

As shown in Figure 11, if two SiC semiconductor devices 10 are randomly selected, the semiconductor circuit into which they are incorporated may have the following effects.

For example, consider a connection configuration where two SiC semiconductor devices 10 are connected in parallel, as shown in Figure 7. In this connection configuration, assume that both SiC semiconductor devices 10 have high BPD density. In this case, if an electrical characteristic fluctuation occurs in one SiC semiconductor device 10, current concentration occurs in the other SiC semiconductor device 10. This, in turn, causes electrical characteristic fluctuations in the other SiC semiconductor device 10, leading to current concentration in the first SiC semiconductor device 10. This cycle repeats, potentially resulting in device failure.

In contrast, if both SiC semiconductor devices 10 have low BPD densities, then neither SiC semiconductor device 10 is likely to experience electrical characteristic fluctuations, thus reducing the likelihood of the above problem occurring. Furthermore, even if one of the two SiC semiconductor devices 10 experiences electrical characteristic fluctuations due to a high BPD density, the other will not experience such fluctuations due to its low BPD density. Therefore, in this case as well, the two SiC semiconductor devices 10 will not repeatedly experience electrical characteristic fluctuations.

In summary, the BPD density plots of the two SiC semiconductor devices 10 shown in Figure 11 can be roughly divided into four sections as shown in Figure 12. When both SiC semiconductor devices 10 have low BPD densities, as in section R1 in the lower left of Figure 12, the electrical characteristic fluctuations of the semiconductor circuit are small, and the degree of imbalance in the way the electrical characteristics fluctuate between the two SiC semiconductor devices 10 is also small. When one of the two SiC semiconductor devices 10 has a low BPD density and the other has a high BPD density, as in section R2 in the upper left and section R3 in the lower right of Figure 12, although the degree of imbalance in electrical characteristic fluctuations is somewhat large, the electrical characteristic fluctuations of the semiconductor circuit are small because the fluctuations are not repeated. When both SiC semiconductor devices 10 have high BPD densities, as in section R4 in the upper right of Figure 12, the degree of imbalance in electrical characteristic fluctuations is large, and the fluctuations are repeated, resulting in large electrical characteristic fluctuations of the semiconductor circuit.

Therefore, in the case of a connection configuration in which two SiC semiconductor devices 10 are connected in parallel, as shown in Figure 13, electrical characteristic fluctuations can be suppressed by selecting SiC semiconductor devices 10 with a combination of low BPD densities for both devices, or a combination where one of the BPD densities is low. Thus, as described above, when connecting multiple SiC semiconductor devices 10 in parallel, the SiC semiconductor devices 10 should be selected from the listed groups based on their low fluctuation acceleration characteristics, or by combining a low-fluctuation-accelerating SiC semiconductor device with a high-fluctuation-accelerating SiC semiconductor device. This suppresses electrical characteristic fluctuations of the SiC semiconductor devices 10 that constitute the semiconductor circuit.

On the other hand, in the case of a connection configuration in which two SiC semiconductor devices 10 are connected in series, the same current will flow, so it is preferable that the BPD densities of the two SiC semiconductor devices 10 be similar, regardless of their relative sizes. For example, in the semiconductor circuit constituting the inverter shown in Figure 8, it is better to ensure that the electrical characteristics of the upper and lower arms do not differ.

Therefore, in the case of a connection configuration in which two SiC semiconductor devices 10 are connected in series, as shown in Figure 14, the SiC semiconductor devices 10 are selected in a combination where the BPD densities of both devices are approximate, regardless of their relative sizes. This suppresses the deviation in electrical characteristics between the two SiC semiconductor devices 10. Thus, when connecting multiple SiC semiconductor devices 10 in series, selecting the SiC semiconductor devices 10 from groups with similar fluctuation acceleration characteristics from a listed group suppresses the deviation in electrical characteristic fluctuations among the multiple SiC semiconductor devices 10 constituting the semiconductor circuit.

In this way, once a SiC semiconductor device 10 corresponding to the connection configuration of the semiconductor circuit to be manufactured is selected, the chip of the SiC semiconductor device 10 with the selected chip number is picked up and incorporated to form the semiconductor circuit. For example, in the case of a module equipped with a semiconductor circuit constituting an inverter as shown in Figure 8, the upper and lower arms, which are connected in series as a combination of U, V, and W phases, will be made up of semiconductor circuits in which SiC semiconductor devices 10 from the same group are incorporated.

As explained above, in this embodiment, the SiC semiconductor device 10 to be incorporated into the semiconductor circuit is selected based on a parameter representing the accelerating fluctuation. This makes it possible to suppress fluctuations in the electrical characteristics of the SiC semiconductor device 10 when stress is applied to the built-in diode BD, compared to the case where the SiC semiconductor device 10 is selected randomly.

Furthermore, the semiconductor circuit manufacturing method of this embodiment can also achieve the following effects.

(1) In the case of a connection configuration in which multiple SiC semiconductor devices 10 are connected in parallel, at least one SiC semiconductor device 10 with a low BPD density is selected. This suppresses fluctuations in electrical characteristics.

(2) In the case of a connection configuration in which multiple SiC semiconductor devices 10 are connected in series, the SiC semiconductor devices 10 are selected in a combination where the BPD density of each SiC semiconductor device 10 is approximate, regardless of the size of each device. This suppresses deviations in the electrical characteristics between the multiple SiC semiconductor devices 10.

(Other embodiments)
This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence range. In addition, various combinations and forms, as well as other combinations and forms including one, more, or less of those elements, fall within the scope and concept of this disclosure.

The above embodiment shows an example of the configuration of the SiC semiconductor device 10, but different configurations are possible. For example, the SiC semiconductor device 10 may be provided with an n-type JFET section and a p-type electric field suppression layer on top of the low-concentration layer 13. The JFET section and the electric field suppression layer may have a structure in which linear portions extend along the X-axis and are arranged alternately and repeatedly in the Y-axis direction. The presence or absence of the buffer layer 12 can be selected as appropriate. Furthermore, when selecting multiple SiC semiconductor devices 10 to be incorporated into a semiconductor circuit, both SiC semiconductor devices 10 with the buffer layer 12 and SiC semiconductor devices 10 without the buffer layer 12 may be selected.

Furthermore, although the above embodiment described an example of a SiC semiconductor device 10 equipped with a MOSFET as a switching element, other switching elements such as IGBTs may also be used.

It goes without saying that, in each of the above embodiments, the elements constituting the embodiment are not necessarily essential unless explicitly stated as essential or considered fundamentally essential. Furthermore, in each of the above embodiments, when numerical values such as the number, numerical values, quantities, or ranges of the constituent elements of the embodiment are mentioned, the embodiment is not limited to those specific numbers unless explicitly stated as essential or considered fundamentally limited to those specific numbers. Also, when the shape, positional relationships, etc., of the constituent elements are mentioned in each of the above embodiments, the embodiment is not limited to those shapes, positional relationships, etc., unless explicitly stated or considered fundamentally limited to those specific shapes, positional relationships, etc.

10…SiC semiconductor device, 10a…One side, 10b…Other side, 11…SiC substrate, 12…Buffer layer, 13…Low-concentration layer, 14…Current dispersion layer, 15…Deep layer, 16…Base layer, 17…Source region, 18…Contact region, 19…Trench, 20…Gate insulating film, 21…Gate electrode, 22…Interlayer insulating film, 23…Source electrode, 23a, 23b…Contact hole, 24…Drain electrode, 25a…Contact hole, 31a, 32a, 51a-56a…MOSFET, 31b, 32b, 51b-56b, BD…Built-in diode, 33…Load, 40…Three-phase motor, 50…Inverter, 51, 53, 55…Upper arm, 52, 54, 56…Lower arm

Claims (3)

A method for manufacturing a semiconductor circuit incorporating a plurality of silicon carbide semiconductor devices (10) having switching elements that include built-in diodes (BDs) formed using a silicon carbide substrate (11),
The silicon carbide semiconductor device to be incorporated into the semiconductor circuit is selected based on a parameter that represents the acceleration of the fluctuations in electrical characteristics caused by energizing the built-in diode,
This includes manufacturing the semiconductor circuit by incorporating the selected silicon carbide semiconductor device,
By selecting the aforementioned silicon carbide semiconductor device,
Based on the parameter representing the aforementioned fluctuation acceleration, the fluctuation acceleration is quantified,
The silicon carbide semiconductor devices are grouped based on the magnitude of the aforementioned fluctuation acceleration value,
A method for manufacturing a semiconductor circuit, in which, when the semiconductor circuit is configured to connect a plurality of silicon carbide semiconductor devices in parallel, at least one silicon carbide semiconductor device is selected from the grouped silicon carbide semiconductor devices to be in a group in which the value of the fluctuation acceleration is smaller than that of the other groups . A method for manufacturing a semiconductor circuit incorporating a plurality of silicon carbide semiconductor devices (10) having switching elements that include built-in diodes (BDs) formed using a silicon carbide substrate (11),
The silicon carbide semiconductor device to be incorporated into the semiconductor circuit is selected based on a parameter that represents the acceleration of the fluctuations in electrical characteristics caused by energizing the built-in diode,
This includes manufacturing the semiconductor circuit by incorporating the selected silicon carbide semiconductor device,
By selecting the aforementioned silicon carbide semiconductor device,
Based on the parameter representing the aforementioned fluctuation acceleration, the fluctuation acceleration is quantified,
The silicon carbide semiconductor devices are grouped based on the magnitude of the aforementioned fluctuation acceleration value,
A method for manufacturing a semiconductor circuit, wherein, when the semiconductor circuit is configured to connect a plurality of silicon carbide semiconductor devices in series, the silicon carbide semiconductor devices are selected from within the same group of grouped silicon carbide semiconductor devices or from groups whose numerical values of the fluctuation acceleration differ by one. The method for manufacturing a semiconductor circuit according to claim 1 or 2 , wherein the parameter representing the fluctuation acceleration includes at least one of the basal plane dislocation density and the hole density when current is applied to the built-in diode.