JP7833594B2 - A system and method for improving composite inter- and intra-prediction. - Google Patents

Description

This application claims priority based on Provisional Application No. 62/790,421, filed on 9 January 2019, the entire contents of which are incorporated herein by reference.

This application relates to video coding and compression. More specifically, this application relates to a method and apparatus for composite interface and intra-prediction (CIIP) method for video coding.

Various video coding techniques can be used to compress video data. Video coding is performed according to one or more video coding standards. For example, video coding standards include General Purpose Video Coding (VVC), Joint Exploration Test Model (JEM), High Efficiency Video Coding (H.265/HEVC), Advanced Video Coding (H.264/AVC), and Video Expert Group (MPEG).
This includes coding, etc. Video coding generally refers to prediction methods that utilize redundancy present in video images or sequences (e.g., inter-prediction, intra-prediction, etc.).
The key goal of video coding technology is to compress video data into a format that uses a lower bitrate while avoiding or minimizing a decrease in video quality.

Examples of this disclosure provide methods for improving the efficiency of merge-related mode syntactic signaling.

A video coding method that compromises: obtaining a reference image in a list of reference images associated with a current prediction block; generating an inter-prediction based on a first motion vector from the current image to a first reference image; obtaining an intra-prediction mode associated with the current prediction block; generating an intra-prediction for the current prediction block based on the intra-prediction; generating a final prediction for the current prediction block by averaging the inter-prediction and the intra-prediction; and determining whether the current prediction block is treated as inter-mode or intra-mode for a most likely mode (MPM) based intra-mode prediction.

A fourth aspect of the present disclosure provides a non-temporary computer-readable storage medium for storing instructions. When executed by one or more processors, the process includes: obtaining a reference image in a list of reference images associated with the current prediction block; generating an inter-prediction based on a first motion vector from the current image to a first reference image; obtaining an intra-prediction mode associated with the current prediction block; and generating an intra-prediction for the current prediction block based on the intra-prediction.
The final prediction for the current prediction block is generated by averaging the inter-prediction and the intra-prediction, and the current prediction block is determined to be in the most likely mode (MP).
M) The computing device is instructed to perform actions including determining whether an intra-mode prediction based on the system should be treated as inter-mode or intra-mode.

Please understand that both the general description above and the detailed description below are merely examples and do not limit this disclosure.

The accompanying drawings incorporated herein and forming part thereof illustrate examples consistent with the present disclosure and, together with the descriptions, help to illustrate the principles of the present disclosure.
This is a block diagram of an encoder according to an example of the disclosure. This is a block diagram of a decoder, as an example of the disclosure. This flowchart shows a method for generating composite inter-intra predictions (CIIPs) according to an example of the present disclosure. This flowchart shows a method for generating a CIIP according to an example of the present disclosure. This figure shows a block partition in a multi-type tree structure, as an example of the disclosure. This figure shows a block partition in a multi-type tree structure, as an example of the disclosure. This figure shows a block partition in a multi-type tree structure, as an example of the disclosure. This figure shows a block partition in a multi-type tree structure, as an example of the disclosure. This figure shows a block partition in a multi-type tree structure, as an example of the disclosure. This figure shows a composite inter-intra prediction (CIIP) as an example of this disclosure. This figure shows a composite inter-intra prediction (CIIP) as an example of this disclosure. This figure shows a composite inter-intra prediction (CIIP) as an example of this disclosure. This is a flowchart of the MPM candidate list generation process, as an example of the disclosure. This is a flowchart of the MPM candidate list generation process, as an example of the disclosure. This figure shows a workflow of an existing CIIP design in VVC, as an example of what is disclosed here. This figure shows the workflow of the proposed CIIP method by removing BDOF, as an example of the disclosure. This figure shows a single-prediction-based CIIP workflow, as an example of this disclosure, in which a list of predictions is selected based on the POC distance. This is a flowchart illustrating a method for enabling the CIIP block for generating an MPM candidate list, as an example of this disclosure. This is a flowchart illustrating a method for disabling the CIIP block for generating an MPM candidate list, as shown in this disclosure. This figure shows a computing environment coupled with a user interface, as an example of the disclosure.

Examples of the present disclosure are referenced in detail here, and these examples are shown in the accompanying drawings. Unless otherwise noted, the following description refers to the accompanying drawings where the same numbers in different drawings represent the same or similar elements. The embodiments described below in the examples of the present disclosure do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with the embodiments related to the present disclosure described in the accompanying claims.

The terms used in this disclosure are for the sole purpose of describing specific embodiments.
This disclosure is not intended to limit the scope of this disclosure. As used in this disclosure and the attached claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless explicitly indicated in the context. The terms “and/or” as used herein are intended to mean and include any or all possible combinations of one or more of the listed items relating to this disclosure.

Here, we may use terms such as “first,” “second,” and “third” to describe various types of information, but it should be understood that the information should not be limited by these terms. These terms are used solely to distinguish one category of information from another. For example, without departing from the scope of this disclosure, first information may be called second information, and similarly, second information may be called first information. Where used herein, the term “if” means, depending on the context, “when,” “on the occasion of,” or “when.”
This can be understood as meaning "at the discretion of the judge."

The first version of the HEVC standard was completed in October 2013, and it offers approximately 50% bitrate savings or equivalent perceived quality compared to the previous generation video coding standard, H.264/MPEG AVC. While the HEVC standard offers significant coding improvements over its predecessor, there is evidence that superior coding efficiency can be achieved by adding coding tools to HEVC. Based on this, VCEG and MPEG
Both ITU-TVECG and ISO/IE have begun research into new coding technologies for future video coding standards. In October 2015, ITU-TVECG and ISO/IE initiated important research into advanced technologies that will enable significant improvements in coding efficiency.
A Joint Video Exploration Team (JVET) was formed by C MPEG. A reference software called the Joint Exploration Model (JEM) was created by integrating several additional coding tools on top of the HEVC Test Model (HM) to enable JVE.
It was maintained by T.

In October 2017, a Call for Proposals (CfP) for video compression with capabilities exceeding HEVC was issued by ITU-T and ISO/IEC. In April 2018, at the 10th JVET meeting, 23 CfP responses were received and evaluated, with some exceeding HEVC by approximately 40%.
The compression efficiency gain was demonstrated. Based on these evaluation results, JVET decided to Versatil
A new project was launched to develop a next-generation video coding standard called e Video Coding (VVC). In the same month, a reference software codebase called the VVC Test Model (VTM) was established to demonstrate a reference implementation of the VVC standard.

Like HEVC, VVC is built on a block-based hybrid video coding framework. Figure 1 (described below) shows a block diagram of a typical block-based hybrid video coding system. The input video signal is processed block by block (called coding units (CUs)). In VTM-1.0, C
U can be up to 128x128 pixels. However, unlike HEVC, which partitions blocks based solely on quad trees, VVC divides a single coding tree unit (CTU) into CUs to accommodate various local characteristics based on quad/binary/ternary trees. Furthermore, the concept of multiple partition unit types in HEVC is eliminated; that is, the separation of CUs, prediction units (PUs), and transformation units (TUs) does not exist in VVC. Instead, each CU is always used as the basic unit for both prediction and transformation without additional partitions. In a multi-type tree structure, a single CTU is initially partitioned by a quad tree structure. Then, each quad tree leaf node can be further partitioned by binary and ternary tree structures.
As shown in Figures 5A, 5B, 5C, 5D, 5D, and 5E (explained below), there are five partitioning types: four-way partitioning, horizontal two-way partitioning, vertical two-way partitioning, horizontal three-way partitioning, and vertical three-way partitioning.

Figure 1 (described below) allows for the performance of spatial and/or temporal predictions.
Spatial prediction (or "intra-prediction") predicts the current video block using pixels from already coded adjacent block samples (called reference samples) within the same video image/slice. Spatial prediction reduces the spatial redundancy inherent in video signals. Temporal prediction (also called "inter-prediction" or "motion-compensated prediction") is also used.
The CU predicts the current video block using reconstructed pixels from an already coded video image. Time prediction reduces the temporal redundancy inherent in the video signal. The time prediction signal for a particular CU is typically signaled by one or more motion vectors (MVs) indicating the amount and direction of movement between the current CU and its time reference. Additionally, if multiple reference images are supported, one reference image index is also transmitted. This is used to identify which reference image in the reference image store the time prediction signal comes from. After spatial and/or time prediction, the mode determination block in the encoder selects the optimal prediction mode, for example, based on a rate-distortion optimization method. The prediction block is then subtracted from the current video block, and the prediction residual is uncorrelated using transformations and quantization.

The quantized residual coefficients are inversely quantized and inversely transformed to form reconstructed residuals, which are then added to the prediction block to form the reconstructed signal of the CU. Further in-loop filtering, such as deblocking filters, sample adaptive offset (SAO), and adaptive in-loop filters (ALF), can be applied to the reconstructed CU before being placed in the reference image store and used for coding future video blocks. To form the output video bitstream, the coding mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are all sent to the entropy coding unit, where they are further compressed and packed to form the bitstream.

Figure 2 (described below) shows a typical block diagram of a block-based video decoder. The video bitstream is first entropy-decoded in an entropy-decode unit. The coding mode and prediction information are sent to either a spatial prediction unit (if intra-coded) or a temporal prediction unit (if inter-coded) to form a prediction block. The residual transformation coefficients are sent to an inverse quantization unit and an inverse transform unit to reconstruct the residual block. The prediction block and the residual block are then added together. The reconstructed block can pass through further in-loop filtering before being stored in a reference image store. The reconstructed video in the reference image store is then sent out to drive a display device and is also used to predict future video blocks.

Figure 1 shows a typical encoder 100. Encoder 100 has a video input 110.
It includes motion compensation 112, motion estimation 114, intra/intermode determination 116, block predictor 140, adder 128, transform 130, quantization 132, prediction-related information 142, intra-prediction 118, image buffer 120, inverse quantization 134, inverse transform 136, adder 126, memory 124, in-loop filter 122, entropy coding 138, and bitstream 144.

Figure 2 shows a block diagram of a typical decoder 200. The decoder 200 consists of a bitstream 210, entropy decoder 212, inverse quantization 214, inverse transform 216, and adder 2
18. It has an intra/intermode selection 220, intra prediction 222, memory 230, in-loop filter 228, motion compensation 224, image buffer 226, prediction-related information 234, and video output 232.

Figure 3 shows an exemplary method 300 for generating composite inter-intra predictions (CIIPs) according to the present disclosure.

In step 310, the first reference image and the second reference image associated with the current prediction block are used.
Get the reference image. Here, the first reference image is before the current image in display order, and the second
The reference image is displayed after the current image in the display order.

In step 312, the first prediction L0 is obtained based on the first motion vector MV0 from the current prediction block to the reference block in the first reference image.

In step 314, a second prediction L1 is obtained based on a second motion vector MV1 from the current prediction block to a reference block in the second reference image.

Figure 4 shows an exemplary method for generating a CIIP according to this disclosure. For example, the method includes single-prediction-based interprediction and MPM-based intraprediction to generate a CIIP.

In step 410, the reference image in the list of reference images associated with the current prediction block is retrieved.

In step 412, an interpretation is generated based on a first motion vector from the current image to the first reference image.

In step 414, the intra-prediction mode associated with the current prediction block is obtained.

In step 416, an intra-prediction is generated for the current prediction block based on the intra-prediction.

In step 418, the final prediction for the current prediction block is generated by averaging the inter-prediction and the intra-prediction.

In step 420, the current prediction block is the most likely mode (MPM).
For the base intra-mode prediction, determine whether it will be treated as inter-mode or intra-mode.

Figure 5A shows a diagram illustrating a block quaternary partition in a multi-type tree structure according to an example of the present disclosure.

Figure 5B shows a diagram illustrating a block vertical binary partition in a multi-type tree structure, according to an example of the present disclosure.

Figure 5C shows a diagram illustrating a block horizontal binary partition in a multi-type tree structure according to an example of the present disclosure.

Figure 5D shows a diagram illustrating a block vertical ternary partition in a multi-type tree structure according to an example of the present disclosure.

Figure 5E shows a diagram illustrating a block horizontal ternary partition in a multi-type tree structure according to an example of the present disclosure.

Combined Inter and Intra Prediction As shown in Figures 1 and 2, inter and intra prediction methods are used in a hybrid video coding scheme. Here, each PU is allowed to choose either inter prediction or intra prediction to utilize correlation in either the time domain or the spatial domain, but not both. However, as noted in previous literature, the residual signals generated by inter-prediction blocks and intra-prediction blocks can exhibit very different characteristics from each other. Therefore, if the two types of predictions can be efficiently combined, another accurate prediction can be expected to reduce the energy of prediction residuals and improve coding efficiency. Furthermore, in natural video content, the motion of moving objects can be complex. For example, there may be regions that contain both old content (e.g., objects included in previously coded images) and new content (e.g., objects excluded in previously coded images). In such scenarios, neither inter prediction nor intra prediction can provide one accurate prediction for the current block.

To further improve prediction efficiency, the VVC standard employs Composite Inter- and Inter-Prediction (CIIP), which combines intra- and inter-prediction of a single CU coded by merge mode. Specifically, for each merge CU, one additional flag is signaled to indicate whether CIIP is enabled for the current CU. For luminance components, CIIP supports four frequently used intra-modes, including planar mode, DC mode, horizontal mode, and vertical mode. For saturation components, DM (i.e., saturation reuses the same intra-mode as the luminance component) is always applied without additional signaling. Furthermore, existing CI
In the IP design, a weighted average is applied, and inter-predicted and intra-predicted samples of a single CIIP CU are combined. Specifically, if planar mode or DC mode is selected, equal weights (i.e., 0.5) are applied. Otherwise (i.e., either horizontal mode or vertical mode is applied), the current CU is first divided horizontally (in horizontal mode) or vertically (in vertical mode) into four regions of the same size.

Furthermore, in the current VVC operating specification, the intra-mode of one CIIP CU can be used as a predictor to predict the intra-mode of its adjacent CIIP CU via the Most Probable Mode (MPM) mechanism. Specifically, each CI
Regarding an IP CU, if its adjacent block is also a CIIP CU, the intra-modes of those adjacent blocks are, first, planar mode, DC mode, horizontal mode,
It is then rounded to the nearest mode within the vertical mode and added to the current CU's MPM candidate list. However, when constructing the MPM list for each intra-CU, if one of its adjacent blocks is coded in CIIP mode, it is considered unavailable. In other words, the intra-mode of one CIIP CU is not permitted to predict the intra-mode of its adjacent intra-CUs. Figures 7A and 7B (described below) compare the MPM list generation process for intra-CUs and CIIP CUs.

Here, shift and _offset are 15-BD and 1≪(14-BD)+2・(1≪13
These are equal to the right-shift and offset values applied to combine the L0 and L1 prediction signals of the dual prediction.

Figure 6A shows a diagram illustrating a composite intermediate and intra-prediction of horizontal modes according to an example of this disclosure.

Figure 6B shows a diagram illustrating a composite intermediate and intra-prediction of vertical modes according to an example of this disclosure.

Figure 6C shows a diagram illustrating a composite intermediate and intra-prediction of planar mode and DC mode according to an example of this disclosure.

Figure 7A shows a flowchart of the MPM candidate list generation process for an intraCUS according to an example of the present disclosure.

Figure 7B shows a flowchart of the MPM candidate list generation process for CIIP CU according to an example of the present disclosure.

Improvements to CIIP While CIIP can improve the efficiency of conventional motion compensation prediction, its design can be further improved. Specifically, the following problems in existing CIIP designs in VVC are identified in this disclosure.

First, as explained in the section on "Composite Inter and Intra Prediction," CIIP is,
To combine inter and intra-prediction samples, each CIIP CU needs to generate a prediction signal using its reconstructed neighboring samples. This is done by one CII
This means that decoding a PCU depends on the complete reconstruction of its adjacent blocks. Due to this interdependence, in actual hardware implementations, CIIP must be performed during the reconstruction phase, when adjacent reconstructed samples are available for intra-prediction. Since decoding CUs during the reconstruction phase must be performed sequentially (i.e., one by one), the number of computational operations (e.g., multiplication, addition, bit shifts) included in the CIIP process cannot be too high in order to ensure sufficient throughput for real-time decoding.

As described in the "Bidirectional Optical Flow" section, BDOF is enabled to improve prediction quality when one intercoded CU is predicted from two reference blocks from both forward and backward time directions. As shown in Figure 8 (described below), in the current VVC, BDOF is also involved in generating interprediction samples in CIIP mode. Given the further complexity with BDOF, such a design would require hardware codec encoding/
Decode throughput may decrease significantly.

Next, in the current CIIP design, when one CIIP CU refers to one merge candidate that is dually predicted, it is necessary to generate motion-compensated prediction signals for both lists L0 and L1. If one or more MVs are not integer precision, an additional interpolation process must be invoked to interpolate the samples at partial sample locations.
Such processes not only increase computational complexity but also increase memory bandwidth if more reference samples need to be accessed from external memory.

Furthermore, as discussed in the section on "Composite Inter and Intra Prediction," current CI
In the IP design, intra-mode CIIP CUs and intra-mode intra-CUs are treated differently when constructing the MPM list for their adjacent blocks. Specifically, if one current CU is coded in CIIP mode, its adjacent CIIP CUs are considered intra, meaning the intra-mode of adjacent CIIP CUs can be added to the MPM candidate list. However, if the current CU is coded in intra-mode, its adjacent CIIP CUs are considered inter, meaning the intra-mode of adjacent CIIP CUs is excluded from the MPM candidate list. Such an inconsistent design may not be optimal for the final version of the VVC standard.

Figure 8 shows a diagram illustrating the workflow of an existing CIIP design in VVC, as an example of the present disclosure.

Simplification of CIIP This disclosure provides a method for simplifying existing CIIP designs to facilitate hardware codec implementation. In general, the main aspects of the technology proposed in this disclosure can be summarized as follows:

First, to improve CIIP coding/decode throughput, it is proposed to exclude BDOF from the generation of interprediction samples in CIIP mode.

Next, in order to reduce computational complexity and memory bandwidth consumption, one CIIP
When CU is double-predicted (i.e., has both L0 and L1 MV), a method is proposed to convert the block from double-predicted to single-predicted in order to generate inter-prediction samples.

Then, two methods are proposed to harmonize the intra-modes of the intra-CU and CIIP when forming MPM candidates for adjacent blocks.

CIIP without BDOF
As noted in the "Problem Statement" section, BDOF is currently C
When U is double-predicted, it is always enabled to generate inter-prediction samples for the CIIP mode. Due to the further complexity of BDOF, existing CIIP designs may suffer from significantly reduced encode/decode throughput, and real-time decoding may be particularly difficult for VVC decoders. On the other hand, CIIP
For the CU, its final prediction sample is generated by averaging the inter-prediction sample and the intra-prediction sample. In other words, the improved prediction sample from BDOF is not directly used as the prediction signal for the CIIP CU. Therefore, compared to the conventional dual-prediction CU (where BDOF is directly applied to generate the prediction sample), the corresponding improvement obtained from BDOF is less efficient in the CIIP CU. Accordingly, based on the above circumstances, it is proposed to disable BDOF when generating inter-prediction samples in CIIP mode. Figure 9 (described below) shows the corresponding workflow of the proposed CIIP process after removing BDOF.

Figure 9 shows a diagram illustrating the workflow of the proposed CIIP method by removing BDOF, as an example of the present disclosure.

CIIP based on a single forecast
As described above, when a merge candidate referenced by a single CIIP CU is double-predicted, both L0 and L1 prediction signals are generated to predict the samples in the CU. In order to reduce memory bandwidth and interpolation complexity, in one embodiment of the present disclosure, (current CU
Even if dual predictions are made, only inter-prediction samples generated using a single prediction will be used and combined with intra-prediction samples in CIIP mode. Specifically, when the current CIIP CU is a single prediction, the inter-prediction samples are:
It is directly coupled with the intra-prediction sample. Otherwise (i.e., when the current CU is double-predicted), the inter-prediction sample used by the CIIP is generated based on a single prediction from one prediction list (L0 or L1). Various methods can be applied to select the prediction list. In the first method, it is proposed that for any CIIP block predicted by two reference images, the first prediction (i.e., list L0) is always selected.

The second method proposes always selecting the second prediction (i.e., list L1) for any CIIP block predicted by two reference images. The third method applies one adaptive method when a prediction list associated with a single reference image having a small image order count (POC) distance from the current image is selected. Figure 10 (described below) illustrates a single-prediction-based CIIP workflow that selects a prediction list based on POC distance.

Finally, in the last method, it is proposed to enable the CIIP mode only when the current CU is single-predicted. Furthermore, to reduce overhead, CII
Signaling of the enable/disable flag for P depends on the prediction direction of the current CIIP CU. If the current CU is predicted to be single, the CIIP flag is signaled in the bitstream to indicate whether CIIP is enabled or disabled. Otherwise (i.e., if the current CU is predicted to be double), the CIIP flag signaling is skipped and is always inferred to be false, meaning CIIP is always disabled.

Figure 10 shows a single-prediction-based CIIP workflow, which selects a list of predictions based on POC distance, according to an example of the present disclosure.

Harmonizing Intra-CU and CIIP Intra-Modes for MPM Candidate List Construction As described above, current CIIP designs are not unified in how they use the intra-modes of the intra-CU and CIIP CU to form MPM candidate lists for their adjacent blocks. Specifically, the intra-modes of both the intra-CU and CIIP CU can predict the intra-modes of adjacent blocks coded in CIIP mode.
However, the intra mode of the intraCU alone is unpredictable. To achieve another unified design, two methods are proposed in this section that harmonize the use of intra-CU and CIIP intra-modes for MPM list configuration.

In the first method, it is proposed to treat the CIIP mode as an intermode for MPM list configuration. Specifically, one CIIP CU or one intra CU
When generating any of the MPM lists, if an adjacent block is coded in CIIP mode, the intra-mode of the adjacent block is marked as unavailable.
This method does not allow the configuration of an MPM list using the intra-mode of the CIIP block. Conversely, the second method proposes treating the CIIP mode as an intra-mode for MPM list configuration. Specifically, in this method,
In the intra-mode of the PCU, the intra-modes of both adjacent CIIP blocks and intra-blocks can be predicted. Figures 11A and 11B (described below) show the MPM candidate list generation process when the two methods described above are applied.

Other embodiments of this disclosure will be apparent to those skilled in the art from considering the specifications and practices of this disclosure disclosed herein. This application does not permit any modification, use, or alteration of this disclosure, including any deviation from this disclosure that falls within the scope of known or customary practice in the art, in accordance with its general principles.
Or intended to cover conformity. The true scope and spirit of this disclosure are shown by the following claims, and the specification and examples are intended to be considered merely examples.

This disclosure is not limited to the specific examples described above and shown in the accompanying drawings, and it should be understood that various modifications and changes may be made without departing from its scope. The scope of this disclosure is intended to be limited only by the attached claims.

Figure 11A shows a flowchart of a method for enabling the CIIP block for generating an MPM candidate list, according to an example of the present disclosure.

Figure 11B shows a flowchart of a method for disabling the CIIP block for MPM candidate list generation, according to an example of the present disclosure.

Figure 12 shows the computing environment 12 coupled with the user interface 1260.
This indicates 10. The computing environment 1210 may be part of a data processing server. The computing environment 1210 includes a processor 1220, memory 1240, and I/
Includes interface 1250.

Processor 1220 controls the overall operation of the computing environment 1210, typically including operations related to display, data acquisition, data communication, and image processing. Processor 1220 may include one or more processors that execute instructions to perform all or some of the steps of the above methods. Furthermore, processor 1220 may include processor 1
It may include one or more circuits that facilitate interaction between 220 and other components.
A processor can be a central processing unit (CPU), a microprocessor, a single-chip machine, or a GPU.

Memory 1240 is configured to store various types of data to support the operation of the computing environment 1210. Examples of such data include instructions, video data, image data, etc., used by any application or method operating in the computing environment 1210. Memory 1240 may contain any type of volatile or non-volatile memory device, or a combination thereof, such as static random access memory (SRAM) or electrically erasable programmable read-only memory (EEPROM).
This can be achieved using erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disks, or optical disks.

The I/O interface 1250 provides an interface between the processor 1220 and peripheral interface modules such as a keyboard, click wheel, and buttons. The buttons include, but are not limited to, a home button, a scan start button, and a scan stop button. The I/O interface 1250 can be coupled with an encoder and a decoder.

In one embodiment, a non-temporary computer-readable storage medium containing multiple programs, such as those contained in memory 1240, which can be executed by a processor 1220 in a computing environment 1210, is also provided for carrying out the method described above. For example, the non-temporary computer-readable storage medium may be ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

A non-temporary computer-readable storage medium stores therein multiple programs for execution by a computing device having one or more processors, and when executed by one or more processors, the multiple programs perform the methods for predicting the operation of the computing device as described above.

In one embodiment, the computing environment 1210 uses one or more application-specific integrated circuits (ASICs), digital signal processors (DS) to perform the method described above.
P), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PL
D) This can be realized by a field-programmable gate array (FPGA), a graphical processing unit (GPU), a controller, a microcontroller, a microprocessor, or other electronic components.

Claims (16)

The method of claim 1, further comprising specifying that the BDOF operation is applied on the condition that CIIP is not applied to generate the final prediction of the current coding block. The method according to claim 1, further comprising calculating a double prediction for the current coding block based on averaging the first prediction and the second prediction. Calculating the double prediction for the current coding block is:
The BDOF value is calculated based on the first horizontal gradient value, the first vertical gradient value, the second horizontal gradient value, and the second vertical gradient value.
The dual prediction of the current coding block is calculated based on the first prediction, the second prediction, and the BDOF value.
The method according to claim 1, further comprising: The method according to claim 1, wherein the bit depth of the video data is equal to 12. The method according to claim 1, wherein the bit depth of the video data is greater than 12. The video coding apparatus according to claim 7, further comprising specifying that the BDOF operation is applied on the condition that CIIP is not applied to generate the final prediction of the current coding block. The video coding apparatus according to claim 7, wherein the bit depth of the video data is equal to 12. The video coding apparatus according to claim 7, wherein the bit depth of the video data is greater than 12. The video coding apparatus according to claim 7, wherein the operation further comprises calculating a double prediction for the current coding block based on averaging the first prediction and the second prediction. Calculating the double prediction for the current coding block is:
The BDOF value is calculated based on the first horizontal gradient value, the first vertical gradient value, the second horizontal gradient value, and the second vertical gradient value.
The dual prediction of the current coding block is calculated based on the first prediction, the second prediction, and the BDOF value.
The video coding apparatus according to claim 7, further comprising: A non-temporary computer-readable storage medium for storing multiple programs executed by a computing device having one or more processors,
A non-temporary computer-readable storage medium wherein the plurality of programs, when executed by one or more processors, cause the computing device to perform the operation according to any one of claims 1 to 6. A method for storing a bitstream,
A bitstream is generated by performing the method according to any one of claims 1 to 4,
The bitstream mentioned above is stored,
A method that includes this. The method according to claim 14, wherein the bit depth of the video data is equal to 12. The method according to claim 14, wherein the bit depth of the video data is greater than 12.