JP7839362B2 - BUCK circuit and its power-on control method, controller, power-on control device - Google Patents

Description

This disclosure claims priority to the Chinese patent applications filed on July 22, 2022, application number 202210869343.6, titled "BUCK Circuit and its Power-On Control Method, Controller, and Power-On Control Device," and filed on July 22, 2022, application number 202210872067.9, titled "BUCK Circuit and its Power-On Control Method, Controller, Power-On Control Device, and Storage Medium," all of which are incorporated herein by reference.

This disclosure relates to the field of power supply technology, and more particularly to BUCK circuits and their power-on control methods, controllers, and power-on control devices.

The BUCK circuit is widely used as a step-down circuit in various applications. Figure 1 shows a commonly used BUCK circuit, but this circuit has the following drawbacks during use. Specifically, in the initial state, the input capacitor C1 is fully charged and the output capacitor C2 is uncharged. Therefore, when the BUCK circuit is powered on, directly turning on the switch transistor Q1 is equivalent to a short circuit across the output capacitor C2, causing a rapid increase in charging current. This can lead to the switch transistor Q1 breaking down or the inductor L1 saturating, potentially damaging the circuit.

This disclosure aims to solve, at least to some extent, one of the technical problems described above.

Therefore, the first object of this disclosure is to provide a power-on control method for a BUCK circuit. This method involves determining a set current according to the current withstand capability of the first switch transistor and the saturation current of the inductor in the BUCK circuit, and during power-on, determining the off-setting time of the first switch transistor according to the time it takes for the inductor current to rise to the set current, thereby controlling the first switch transistor to be turned off. This prevents the inductor current from damaging any elements in the circuit, effectively ensuring the safety of the BUCK circuit during power-on.

A second object of this disclosure is to provide a controller for a BUCK circuit.

The third object of this disclosure is to provide a computer-readable storage medium.

A fourth object of this disclosure is to provide a power-on control device for a BUCK circuit.

The fifth object of this disclosure is to provide a BUCK circuit.

To achieve the above objective, the power-on control method for a BUCK circuit provided in an embodiment of the first aspect of this disclosure includes the steps of: identifying the current withstand capability of a first switch transistor in the BUCK circuit and identifying the saturation current of an inductor in the BUCK circuit; determining a set current and a current rise time according to the smaller of the current withstand capability and the saturation current; determining the on-set time of the first switch transistor according to the current rise time; and, when the BUCK circuit is powered on, switching the state of the first switch transistor according to the inductor current and the set current, or switching the state of the first switch transistor according to the on-time of the first switch transistor and the on-set time, until the output voltage of the BUCK circuit reaches a target voltage.

The power-on control method for a BUCK circuit according to the embodiment of this disclosure determines the set current and current rise time according to the smaller of the current withstand capability of the first switch transistor in the BUCK circuit and the saturation current of the inductor, determines the on-set time of the first switch transistor according to the current rise time, and when the BUCK circuit is powered on, switches the state of the first switch transistor according to the inductor current and the set current until the output voltage of the BUCK circuit reaches the target voltage, or switches the state of the first switch transistor based on the on-time and the on-set time of the first switch transistor, thereby preventing the inductor current from damaging each element in the circuit during power-on and effectively ensuring the safety of the BUCK circuit during power-on.

According to one embodiment of the present disclosure, the step of switching the state of the first switch transistor in accordance with the inductor current and the set current includes the steps of: controlling the first switch transistor to turn on when the BUCK circuit is powered on, acquiring the inductor current, determining the on time of the first switch transistor when the inductor current reaches the set current, determining the off setting time of the first switch transistor according to the on time, controlling the first switch transistor to turn off, and controlling the first switch transistor to turn on when the off time of the first switch transistor reaches the off setting time, repeating this process sequentially until the output voltage of the BUCK circuit reaches a target voltage.

According to one embodiment of this disclosure, the step of determining the off-setting time of the first switch transistor according to the on-time includes: determining the control period of the first switch transistor; identifying the time difference between the on-time and the control period when the on-time is greater than or equal to the control period, and setting the difference between the control period and the time difference as the off-setting time; and setting the difference between the control period and the on-time as the off-setting time when the on-time is less than the control period.

According to one embodiment of the present disclosure, the step of determining the control period of the first switch transistor includes: identifying a first time when the inductor current rises to a maximum current value when the first switch transistor is first turned on; identifying a second time when the first switch transistor is controlled to turn off and the inductor current falls from the maximum current value to zero; and defining the control period as the sum of the first time and the second time.

According to one embodiment of the present disclosure, the step of determining the control period of a first switch transistor includes: identifying a first time when the first switch transistor is first turned on, during which the inductor current rises to a maximum current value; identifying a third time when the first switch transistor is controlled to turn off, during which the inductor current drops from the maximum current value to a preset current threshold greater than zero; and defining the sum of the first time and the third time as the control period.

According to one embodiment of the present disclosure, the step of switching the state of the first switch transistor according to the on-time and on-set time of the first switch transistor includes the steps of controlling the first switch transistor to turn on when the BUCK circuit is powered on, controlling the first switch transistor to turn off when the on-time of the first switch transistor reaches the on-set time, and controlling the first switch transistor to turn on when it is determined that the first switch transistor satisfies a preset off condition, and repeating this sequentially until the output voltage of the BUCK circuit reaches a target voltage.

According to one embodiment of the present disclosure, the step of determining that a first switch transistor satisfies a preset off condition includes the steps of: obtaining the current of an inductor during the off period of the first switch transistor; and determining that the first switch transistor satisfies the preset off condition when the current of the inductor drops to zero.

According to one embodiment of the present disclosure, the step of determining that a first switch transistor satisfies a preset off condition includes: obtaining the current of an inductor during the off period of the first switch transistor; and determining that the first switch transistor satisfies a preset off condition when the current of the inductor drops to a preset current threshold.

According to one embodiment of this disclosure, the step of determining that a first switch transistor satisfies a preset off condition includes obtaining the off time of the first switch transistor, and determining that the first switch transistor satisfies a preset off condition when the off time of the first switch transistor reaches a second set time, wherein the second set time is greater than the on set time.

According to one embodiment of the present disclosure, the step of determining that a first switch transistor satisfies a preset off condition includes: obtaining the maximum current of the inductor during the initial on-period of the first switch transistor; identifying a first time at which the maximum current decreases to zero; and determining that the first switch transistor satisfies a preset off condition when the off-period of the first switch transistor reaches a first time.

According to one embodiment of the present disclosure, the step of determining that a first switch transistor satisfies a preset off condition includes: obtaining the maximum current of the inductor during the initial on-period of the first switch transistor; identifying a second time at which the maximum current decreases to a preset current threshold; and determining that the first switch transistor satisfies the preset off condition when the off-time of the first switch transistor reaches the second time.

According to one embodiment of the present disclosure, when the flyback element in the BUCK circuit is a second switch transistor, the method further includes the steps of: controlling the second switch transistor to be turned off when the first switch transistor is turned on; and controlling the second switch transistor to be turned on when the first switch transistor is turned off.

According to one embodiment of the present disclosure, when the second switch transistor is on, the method further includes the step of controlling the second switch transistor to turn off prematurely if the inductor current drops to zero and the off time of the first switch transistor has not reached the off-set time.

To achieve the above objective, the BUCK circuit controller provided in the second embodiment of this disclosure comprises a memory, a processor, and a BUCK circuit power-on control program stored in the memory and operable on the processor. The processor implements the aforementioned power-on control method when executing the BUCK circuit power-on control program.

The controller for the BUCK circuit according to the embodiment of this disclosure implements the aforementioned power-on control method on the BUCK circuit, thereby reducing the inductor current of the BUCK circuit to less than the current withstand capability of the switch transistor and the saturation current of the inductor during power-on. This prevents the inductor current from damaging any elements in the circuit, effectively ensuring the safety of the BUCK circuit during power-on.

To achieve the above objective, the computer-readable storage medium provided in the third embodiment of this disclosure stores a power-on control program for the BUCK circuit, and when the power-on control program for the BUCK circuit is executed by the processor, the aforementioned power-on control method for the BUCK circuit is realized.

The computer-readable storage medium according to the embodiments of this disclosure, through the aforementioned power-on control method, can ensure that the inductor current of the BUCK circuit is kept below the current rating of the switch transistor and the saturation current of the inductor during power-on. This prevents the inductor current from damaging any elements in the circuit, effectively ensuring the safety of the BUCK circuit during power-on.

To achieve the above objective, the power-on control device for a BUCK circuit provided in an embodiment of the fourth aspect of this disclosure comprises: a determination module for determining the current withstand capability of a first switch transistor in the BUCK circuit, determining the saturation current of an inductor in the BUCK circuit, determining a set current and current rise time according to the smaller of the current withstand capability and saturation current, and determining the on-set time of the first switch transistor according to the current rise time; and a control module for switching the state of the first switch transistor according to the inductor current and the set current, or switching the state of the first switch transistor according to the on-time of the first switch transistor and the on-set time, until the output voltage of the BUCK circuit reaches a target voltage.

The power-on control device according to the embodiment of this disclosure uses a determination module to identify the current withstand capability of the first switch transistor in the BUCK circuit and the saturation current of the inductor in the BUCK circuit. The control module determines the set current and current rise time based on the smaller of the current withstand capability and saturation current, and determines the on-set time of the first switch transistor based on the current rise time. When the BUCK circuit is powered on, the control module switches the state of the first switch transistor based on the inductor current and the set current, or switches the state of the first switch transistor based on the on-time and on-set time, until the output voltage of the BUCK circuit reaches the target voltage. This effectively ensures the safety of the BUCK circuit during power-on by preventing the inductor current from damaging the components in the circuit.

To achieve the above objective, the BUCK circuit provided in the fifth embodiment of this disclosure includes an input capacitor, a first switch transistor with one end connected to one end of the input capacitor, a flyback element with one end connected to the other end of the first switch transistor and the other end connected to the other end of the input capacitor, an inductor with one end connected to the other end of the first switch transistor, an output capacitor with one end connected to the other end of the inductor and the other end connected to the other end of the flyback element, an output voltage detection module for detecting the output voltage of the BUCK circuit, a current detection module for detecting the inductor current, and the first switch transistor The system includes a controller for determining the current withstand capability of an inductor, determining the saturation current of an inductor, determining the set current and rise time according to the smaller of the current withstand capability and saturation current, and determining the on-set time of the first switch transistor according to the current rise time. The controller is further used, when the BUCK circuit is powered on, to switch the state of the first switch transistor according to the inductor current and the set current, or to switch the state of the first switch transistor according to the on-time of the first switch transistor and the on-set time, until the output voltage of the BUCK circuit reaches the target voltage.

According to the BUCK circuit of the embodiment of this disclosure, the controller determines the current withstand capability of the first switch transistor and the saturation current of the inductor. The controller determines the set current and rise time based on the smaller of the current withstand capability and saturation current, and the controller determines the on-set time of the first switch transistor based on the current rise time. When the BUCK circuit is powered on, the controller switches the state of the first switch transistor based on the inductor current and the set current until the output voltage of the BUCK circuit reaches the target voltage, or switches the state of the first switch transistor based on the on-time and on-set time of the first switch transistor. This effectively ensures the safety of the BUCK circuit during power-on by preventing the inductor current from damaging the elements in the circuit.

Additional aspects and benefits of this disclosure are partially given in the following description, some of which are evident from the following description or understood through the practice of this disclosure.

This is a circuit diagram of a BUCK circuit in related technologies. This is a circuit diagram of a BUCK circuit according to one embodiment of the present disclosure. This is a circuit diagram of a BUCK circuit according to another embodiment of the present disclosure. This is a flowchart of a power-on control method for a BUCK circuit according to one embodiment of the present disclosure. This is a flowchart of a power-on control method for a BUCK circuit according to another embodiment of the present disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some embodiments of this disclosure. This diagram shows the relationship between the switch transistor operation of a BUCK circuit and voltage and current according to some other embodiments of the present disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some other embodiments of the present disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some other embodiments of the present disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some other embodiments of the present disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some other embodiments of the present disclosure. This is a flowchart of a power-on control method for a BUCK circuit according to one embodiment of the present disclosure. This diagram shows the relationship between the operation of the switch transistor in a BUCK circuit and the voltage and current according to some embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor in a BUCK circuit and the voltage and current according to some other embodiments of this disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some other embodiments of the present disclosure. This diagram shows the relationship between the operation of the switch transistor and voltage/current in a BUCK circuit according to some other embodiments of the present disclosure. This diagram shows the relationship between the switch transistor operation and voltage/current of a BUCK circuit according to some other embodiments of the present disclosure. This diagram shows the relationship between the switch transistor operation and voltage/current of a BUCK circuit according to some other embodiments of the present disclosure. This diagram shows the relationship between the switch transistor operation and voltage/current of a BUCK circuit according to some other embodiments of the present disclosure. This diagram shows the relationship between the switch transistor operation and voltage/current of a BUCK circuit according to some other embodiments of the present disclosure. This is a schematic diagram of the structure of a BUCK circuit controller according to one embodiment of the present disclosure. This is a schematic diagram of the structure of a power-on control device for a BUCK circuit according to one embodiment of the present disclosure. This is a schematic diagram of the structure of a power-on control device for a BUCK circuit according to one embodiment of the present disclosure. This is a circuit diagram of a BUCK circuit according to one embodiment of the present disclosure.

The embodiments of this disclosure shown in the drawings will be described in detail below. In all drawings, the same or similar reference numerals indicate the same or similar elements or elements having the same or similar functions. The embodiments described with reference to the following drawings are illustrative and are for illustrative purposes only and should not be understood as limitations to this disclosure.

The power-on control method of this disclosure can be applied to a BUCK circuit as shown in Figure 2 or Figure 3. As shown in Figures 2-3, the BUCK circuit comprises an input capacitor C1, a first switch transistor Q1, a flyback element, an inductor L1, and an output capacitor C2. The flyback element may be a diode D as shown in Figure 2 or a second switch transistor Q2 as shown in Figure 3. One end of the first switch transistor Q1 is connected to one end of the input capacitor C1, one end of the flyback element is connected to the other end of the first switch transistor Q1, the other end of the flyback element is connected to the other end of the input capacitor C1, one end of the inductor L1 is connected to the other end of the first switch transistor Q1, one end of the output capacitor C2 is connected to the other end of the inductor L1, and the other end of the output capacitor C2 is connected to the other end of the flyback element. As shown in Figure 3, the step-down function of the BUCK circuit can be realized by controlling the on/off state of the first switch transistor Q1 and the second switch transistor Q2. The input voltage (i.e., the voltage across the input capacitor C1) is stepped down to obtain the output voltage (i.e., the voltage across the output capacitor C2), and the input voltage is greater than the output voltage. As shown in Figure 2, the step-down function of the BUCK circuit can be realized by controlling the on/off state of the first switch transistor Q1.

Figure 4 is a flowchart of a power-on control method for a BUCK circuit according to one embodiment of this disclosure. For the sake of simplicity, the following explanation will primarily use the case where the power-on control method is applied to a BUCK circuit as shown in Figure 2 as an example.

As shown in Figure 4, the power-on control method for the BUCK circuit may include the following steps:

In step S102, the current withstand capability of the first switch transistor in the BUCK circuit is determined, as well as the saturation current of the inductor in the BUCK circuit.

Note that current withstand capability refers to the maximum current that the first switch transistor Q1 can withstand. If the current exceeds the current withstand capability of the first switch transistor Q1, the first switch transistor Q1 will break down and be damaged. Saturation current refers to the current corresponding to the saturation of the inductor L. That is, if the current exceeds the saturation current of the inductor L1, a saturation phenomenon occurs in the inductor L1.

In S104, the set current is determined according to the smaller of the current-bearing capacity and saturation current values.

Specifically, as shown in Figure 2, when the BUCK circuit is powered on, the first switch transistor Q1 is initially turned on. Due to the influence of the input capacitor C1 and output capacitor C2, the BUCK circuit generates a large charging current, charging the output capacitor C2. Because an inductor L1 is present in the circuit, the charging current of the BUCK circuit (i.e., the inductor current) continues to rise from zero. When this rise exceeds the current rating of the first switch transistor Q1 or the saturation current of the inductor L1, the first switch transistor Q1 may break down and be damaged, or the inductor L1 may saturate. Therefore, to avoid the breakdown and damage of the first switch transistor Q1 or the saturation of the inductor L1, the set current can be determined according to the current rating and saturation current. For example, the set current is less than the smaller of the current rating and saturation current.

Furthermore, by examining the product parameters based on the model numbers of the first switch transistor Q1 and inductor L1, the current withstand capability of the first switch transistor Q1 and the saturation current of the inductor L1 can be determined in advance. Then, the smaller of these two values is obtained, and a value smaller than this smaller value is selected as the set current.

In S106, when the BUCK circuit is powered on, the first switch transistor is controlled to turn on, the inductor current is acquired, and when the inductor current reaches the set current, the on time of the first switch transistor is determined, the off setting time of the first switch transistor is determined according to the on time, the first switch transistor is controlled to turn off, and when the off time of the first switch transistor reaches the off setting time, the first switch transistor is controlled to turn on. This process is repeated sequentially until the output voltage of the BUCK circuit reaches the target voltage.

Specifically, as shown in Figure 2, when the BUCK circuit is powered on, the first switch transistor Q1 is first controlled to turn on. At this time, the input capacitor C1 charges the output capacitor C2 via the first switch transistor Q1 and inductor L1. The inductor current continues to rise from zero, and when the inductor current rises from zero to the set current, it indicates that the charging current of the BUCK circuit is approaching the smaller of the current rating of the first switch transistor Q1 or the saturation current of the inductor L1. At this time, the first switch transistor Q1 is controlled to turn off to avoid breakdown of the first switch transistor Q1 and saturation of the inductor L1 due to the continued rise in charging current. Simultaneously, the on time of the first switch transistor Q1 is obtained, and the off setting time of the first switch transistor Q1 is determined according to the on time of the first switch transistor Q1. When the first switch transistor Q1 is turned off, the inductor L1 continues to charge the output capacitor C2 via the diode D, causing the voltage across the output capacitor C2 to continue rising and the inductor current in the BUCK circuit to decrease. When the off time of the first switch transistor Q1 reaches the set off time, the first switch transistor Q1 is controlled to be turned on again.

When the first switch transistor Q1 is turned on again, the inductor current rises again. When the inductor current reaches the set current, the first switch transistor Q1 is controlled to turn off. The current on-time of the first switch transistor Q1 is determined, and the off-time of the first switch transistor Q1 is determined according to this on-time. When the off-time of the first switch transistor Q1 reaches the determined off-time, the first switch transistor Q1 is controlled to turn on again. This process is repeated until the output voltage of the BUCK circuit reaches the target voltage (which is less than the input voltage). At this point, the on/off switching of the first switch transistor Q1 does not generate a large inrush current that would affect circuit safety, and the BUCK circuit can stop executing step S106 and enter normal control logic.

In the above embodiment, the set current is determined according to the current withstand capability of the first switch transistor in the BUCK circuit and the saturation current of the inductor. During power-on, the off-setting time of the first switch transistor is determined according to the time it takes for the inductor current to rise to the set current, and the first switch transistor is controlled to be off. This prevents the inductor current from damaging each element in the circuit, effectively ensuring the safety of the BUCK circuit during power-on.

In some embodiments, the step of determining the off-setting time of the first switch transistor according to the on-time includes: determining the control period of the first switch transistor; identifying the time difference between the on-time and the control period when the on-time is greater than or equal to the control period, and setting the difference between the control period and the time difference as the off-setting time; and setting the difference between the control period and the on-time as the off-setting time when the on-time is less than the control period.

Specifically, the control period T of the first switch transistor Q1 may be a fixed value that can be preset according to the actual situation. Normally, one control period T should include two processes: turning the first switch transistor Q1 on and turning it off. However, since the on-time t of the first switch transistor Q1 is related to the set current and the charging and discharging rates of the inductor and capacitor in the BUCK circuit, the on-time t changes during power-on, and may become greater than, less than, or equal to the control period T. Therefore, the off-setting time t' of the first switch transistor Q1 is determined according to the relationship between the on-time t and the control period T, thereby realizing off-control of the first switch transistor Q1. The corresponding control logic is shown in Figure 5.

Furthermore, Figure 6a is a schematic diagram illustrating the relationship between the operation of the switch transistor and the voltage and current. As shown in Figure 6a, when the BUCK circuit is powered on, the first switch transistor Q1 is first controlled to be ON, and timing begins. Simultaneously, the current of inductor L1 is acquired. As the current of inductor L1 continues to rise from zero and reaches the set current, timing is stopped, the ON time t of the first switch transistor Q1 is acquired, and it is determined whether the ON time t is greater than or equal to the control period T. At this time, since the ON time t is smaller than the control period T, the ON time can be updated to t' = t, that is, the ON time is maintained as is, the OFF setting time of the first switch transistor Q1 is set to T-t', and simultaneously, the first switch transistor Q1 is controlled to be OFF, and timing begins. When the timing time reaches the OFF setting time T-t', the first control period of the first switch transistor Q1 ends.

Subsequently, the first switch transistor Q1 is controlled to turn on again, and timing begins, while the current of inductor L1 is acquired. When the acquired current of inductor L1 reaches the set current, timing is stopped, the on-time t of the first switch transistor Q1 is acquired, and it is determined whether the on-time t is greater than or equal to the control period T. At this point, since the on-time t is greater than or equal to the control period T, the on-time can be updated to t' = t - T, the off-setting time of the first switch transistor Q1 is calculated as T - t', and simultaneously, the first switch transistor Q1 is controlled to turn off, and timing begins. When the timing time reaches the off-setting time T - t', the second control period of the first switch transistor Q1 ends. As can be seen from Figure 6a, since the output voltage of the BUCK circuit reaches the target voltage after the second control period ends, the power-on of the BUCK circuit can be completed quickly by rationally setting the control period T.

Furthermore, setting a large control period T can lead to situations like those shown in Figures 6b and 6c. Specifically, the inductor current drops to zero before the off-time of the first switch transistor Q1 has reached the set off time. Therefore, by rationally setting the control period T, the occurrence of such situations can be reduced, thereby enabling high-speed power-on of the BUCK circuit.

In the above embodiment, by determining the off-setting time of the first switch transistor according to the relationship between the on-time and control cycle of the first switch transistor, it is possible to achieve switch transistor control with a constant control cycle but different duty cycles. Furthermore, this method ensures the safety of the BUCK circuit by preventing the charging current of the BUCK circuit from damaging each element during power-on.

In some embodiments, the step of determining the control period of the first switch transistor includes: identifying a first time when the inductor current rises to a maximum current value when the first switch transistor is first turned on, and controlling the first switch transistor to turn off; identifying a second time when the inductor current falls from the maximum current value to zero; and taking the sum of the first time and the second time as the control period.

In other words, the control period of the first switch transistor may not only be set to a fixed value, but may also be determined according to the time corresponding to the first on/off cycle of the first switch transistor. Specifically, as shown in Figure 6d, when the BUCK circuit is powered on, the first switch transistor Q1 is controlled to be on, timing begins, and the current of inductor L1 is acquired. As the current of inductor L1 continues to rise from zero, and the acquired current reaches the maximum current value (i.e., the set current value), timing is stopped, the on time of the first switch transistor Q1 is acquired, and this is the first time. Simultaneously, the first switch transistor Q1 is controlled to be off, timing begins, and as the current of inductor L1 begins to decrease from the maximum current value and drops to zero, timing is stopped, the off time of the first switch transistor Q1 is acquired, and this is the second time. Next, the sum of the first time and the second time is defined as the control period T.

Subsequently, the first switch transistor Q1 is controlled to turn on again, and timing begins. The current of inductor L1 is also acquired. When the current of inductor L1 reaches the set current, timing is stopped. The on-time t of the first switch transistor Q1 is acquired, and it is determined whether the on-time t is greater than or equal to the control period T. At this point, since the on-time t is less than the control period T, the on-time can be updated to t'=t. That is, without changing the on-time, the off-setting time of the first switch transistor Q1 is calculated as T-t', and simultaneously, the first switch transistor Q1 is controlled to turn off, and timing begins. When the timing time reaches the off-setting time T-t', the second control period of the first switch transistor Q1 ends. The same procedure is followed for subsequent control periods.

Furthermore, when the first switch transistor Q1 is turned on, the voltage across the input capacitor C2 in the second control cycle is greater than the voltage across the input capacitor C2 in the first control cycle. As can be seen from the inductor current calculation formula di/dt = (VC1 - VC2) / L (where VC1 is the voltage across the input capacitor C1 and L is the inductance value of the inductor), the rate of increase of the inductor current in the second control cycle is smaller than the rate of increase of the inductor current in the first control cycle. Therefore, the on time of the first switch transistor Q1 in the second control cycle is greater than the on time of the first switch transistor Q1 in the first control cycle. Also, when the first switch transistor Q1 is turned off, as can be seen from the inductor current calculation formula di/dt = (-VC2) / L, the rate of decrease of the inductor current in the second control cycle is greater than the rate of decrease of the inductor current in the first control cycle. Therefore, the off time of the first switch transistor Q1 in the second control cycle is smaller than the off time of the first switch transistor Q1 in the first control cycle. However, since the sum of the on-time and off-time of the first switch transistor Q1 in the second control cycle is not significantly different from the sum of the on-time and off-time of the first control cycle, the control cycle T can be set to the sum of the on-time and off-time of the first switch transistor Q1 in the first control cycle. Furthermore, this control cycle T avoids delays in power-on speed caused by setting the control cycle too large, thereby achieving further optimization of the power-on control method.

This allows for setting the control cycle according to the initial on/off time of the first switch transistor, and determining the off setting time of the first switch transistor according to the relationship between the on time and the control cycle. This enables switch transistor control with a constant control cycle but different duty cycles. Furthermore, this method ensures the safety of the BUCK circuit by preventing damage to individual components from the charging current during power-on, while simultaneously avoiding power-on speed delays caused by setting the control cycle too large. This leads to further optimization of the power-on control method.

In some other embodiments, the step of determining the control period of the first switch transistor includes: identifying a first time when the first switch transistor is first turned on, during which the inductor current rises to a maximum current value, and controlling the first switch transistor to turn off; identifying a third time when the inductor current falls from the maximum current value to a preset current threshold greater than zero; and taking the sum of the first time and the third time as the control period.

In other words, the control period T can be determined based on whether the inductor current drops to zero or a single non-zero value.

Specifically, as shown in Figure 6e, when the BUCK circuit is powered on, the first switch transistor Q1 is controlled to turn on, timing begins, and the current of inductor L1 is acquired. As the current of inductor L1 continues to rise from zero, and reaches the maximum current value (i.e., the set current value), timing stops, the ON time of the first switch transistor Q1 is acquired, and this is defined as the first time. Simultaneously, the first switch transistor Q1 is controlled to turn off, timing begins again, and as the current of inductor L1 begins to decrease from the maximum current value and falls to a preset current threshold, timing stops, the OFF time of the first switch transistor Q1 is acquired, and this is defined as the third time. Next, the sum of the first time and the third time is defined as the control period T.

Subsequently, the first switch transistor Q1 is controlled to turn on again, and timing begins. The current of inductor L1 is also acquired. When the current of inductor L1 reaches the set current, timing is stopped. The on-time t of the first switch transistor Q1 is acquired, and it is determined whether the on-time t is greater than or equal to the control period T. At this point, since the on-time t is less than the control period T, the on-time can be updated to t'=t. That is, without changing the on-time, the off-setting time of the first switch transistor Q1 is calculated as T-t', and simultaneously, the first switch transistor Q1 is controlled to turn off, and timing begins. When the timing time reaches the off-setting time T-t', the second control period of the first switch transistor Q1 ends. The same procedure is followed for subsequent control periods.

This allows for setting the control cycle according to the initial on/off time of the first switch transistor, and determining the off setting time of the first switch transistor according to the relationship between the on time and the control cycle. This enables the control of switch transistors with a constant control cycle but different duty cycles. Furthermore, this method ensures the safety of the BUCK circuit by preventing damage to individual components from the charging current during power-on. Simultaneously, it avoids delays in power-on speed due to setting the control cycle too large, or frequent on/off cycles of the first switch transistor due to setting it too small, thereby achieving further optimization of the power-on control method.

In some embodiments, as shown in Figure 3, when the flyback element in the BUCK circuit is the second switch transistor Q2, the power-on control method further includes the steps of: controlling the second switch transistor to turn off when the first switch transistor is turned on, and controlling the second switch transistor to turn on when the first switch transistor is turned off.

Specifically, as shown in Figures 3 and 7a-7e, when the BUCK circuit is powered on, the first switch transistor Q1 is first controlled to turn on, and the second switch transistor Q2 is controlled to turn off. At this time, the input capacitor C1 charges the output capacitor C2 via the first switch transistor Q1 and inductor L1. The inductor current continues to rise from zero, and when the inductor current rises from zero to the set current, it indicates that the charging current of the BUCK circuit is approaching the smaller of the current rating of the first switch transistor Q1 or the saturation current of the inductor L1. At this time, in order to avoid breakdown of the first switch transistor Q1 and saturation of the inductor L1 due to the continued rise in charging current, the first switch transistor Q1 is controlled to turn off, and the second switch transistor Q2 is controlled to turn on. Simultaneously, the on time of the first switch transistor Q1 is obtained, and the off setting time of the first switch transistor Q1 is determined according to the on time of the first switch transistor Q1. When the first switch transistor Q1 is turned off and the second switch transistor Q2 is turned on, inductor L1 continues to charge the output capacitor C2 via the second switch transistor Q2. As the voltage across the output capacitor C2 continues to rise, the inductor current of the BUCK circuit decreases. When the off time of the first switch transistor Q1 reaches the off-setting time, the first switch transistor Q1 is controlled to be turned on again, and the second switch transistor Q2 is controlled to be turned off.

When the first switch transistor Q1 is turned on again and the second switch transistor Q2 is turned off again, the inductor current rises again. When the inductor current reaches the set current, the first switch transistor Q1 is controlled to turn off, and the second switch transistor Q2 is controlled to turn on. Simultaneously, the on-time of the first switch transistor Q1 is determined, and the off-time of the first switch transistor Q1 is determined according to this on-time. When the off-time of the first switch transistor Q1 reaches the determined off-time, the first switch transistor Q1 is controlled to turn on again, and the second switch transistor Q2 is controlled to turn off. This process is repeated until the output voltage of the BUCK circuit reaches the target voltage. At this point, the on/off switching of the first switch transistor Q1 does not generate a large inrush current that would affect circuit safety, and the BUCK circuit can stop executing step S106 and enter normal control logic.

In the above embodiment, the set current is determined according to the current withstand capability of the first switch transistor in the BUCK circuit and the saturation current of the inductor. During power-on, the off-setting time of the first switch transistor is determined according to the time it takes for the inductor current to rise to the set current, and the first switch transistor is controlled to be off. This prevents the inductor current from damaging each element in the circuit, effectively ensuring the safety of the BUCK circuit during power-on.

In some embodiments, when the second switch transistor is on, the power-on control method further includes the step of controlling the second switch transistor to turn off prematurely if the inductor current drops to zero and the off time of the first switch transistor has not reached the off-set time.

Specifically, let's first consider the case where the control period T is a preset fixed value. When the control period T is set to a large value, as shown in Figures 7b-7c, the inductor L1 is completely discharged and the inductor current drops to zero before the off-time of the first switch transistor Q1 has reached the off-setting time. At this time, the second switch transistor Q2 can be controlled to be turned off early. In practical implementation, when the first switch transistor Q1 is turned off, the current of the inductor L1 is acquired, and when the current of the inductor L1 drops to zero, the second switch transistor Q2 can be controlled to be turned off. When the control period T is set to a small value, as shown in Figure 7a, when the off-time of the first switch transistor Q1 reaches the off-setting time, if the inductor current has just dropped to zero or has not yet dropped to zero, the second switch transistor Q2 is controlled to be turned off based on the constraint of the off-setting time of the first switch transistor Q1.

Furthermore, let's consider an example where the control period T corresponds to the case where the inductor current drops to zero when the first switch transistor Q1 is turned off. As shown in Figure 7d, there is no situation where the inductor current drops to zero but the off time of the first switch transistor Q1 has not reached the off-set time. In this case, the second switch transistor Q2 is controlled to turn off based on the constraint of the off-set time of the first switch transistor Q1.

Furthermore, let's consider an example where the control period T corresponds to the case where the inductor current drops to a preset current threshold when the first switch transistor Q1 is turned off. As shown in Figure 7e, there is no situation where the inductor current drops to zero but the off time of the first switch transistor Q1 has not reached the off-setting time. In this case, the second switch transistor Q2 is controlled to turn off based on the constraint of the off-setting time of the first switch transistor Q1.

Figure 8 is a flowchart of a power-on control method for a BUCK circuit according to one embodiment of the present invention. For the sake of simplicity, the following explanation will primarily describe the power-on control method applied to a BUCK circuit as shown in Figure 2.

As shown in Figure 8, the power-on control method for the BUCK circuit may include the following steps:

In S202, the current withstand capability of the first switch transistor in the BUCK circuit is determined, as well as the saturation current of the inductor in the BUCK circuit.

Note that the current rating refers to the maximum current that the first switch transistor Q1 can withstand. If the current exceeds the current rating of the first switch transistor Q1, it will break down and be damaged. The saturation current is the current corresponding to the saturation of the inductor L. That is, if the current exceeds the saturation current of the inductor L1, a saturation phenomenon occurs in the inductor L1.

In S204, the current rise time is determined according to the smaller of the withstand current and the saturation current, and the ON setting time of the first switch transistor is determined according to the current rise time.

Specifically, as shown in Figure 2, when the BUCK circuit is powered on, the first switch transistor Q1 is initially turned on. Influenced by the input capacitor C1 and output capacitor C2, the BUCK circuit generates a large charging current (i.e., the current in inductor L1), charging the output capacitor C2. Because of the inductor L1 in the circuit, the charging current of the BUCK circuit continues to rise from zero. Here, the current rise time is set to the time corresponding to the increase in the charging current from zero to the smaller of the current rating of the first switch transistor Q1 and the saturation current of the inductor L1. The ON setting time TS1 of the first switch transistor Q1 is determined according to this current rise time. When the actual ON time of the first switch transistor Q1 reaches the ON setting time TS1, the first switch transistor Q1 is controlled to turn OFF to avoid breakdown of the first switch transistor Q1 or saturation of the inductor L1 due to the continuously rising charging current.

Furthermore, by examining the product parameters based on the model numbers of the first switch transistor Q1 and inductor L1, the current withstand capability of the first switch transistor Q1 and the saturation current of the inductor L1 can be determined in advance. The smaller of these two values is obtained, and then, based on the inductor current calculation formula, the current rise time is calculated based on the voltage across the input capacitor C1 and the voltage across the output capacitor C2. By adding a certain margin based on this, the on-set time TS1 of the first switch transistor is obtained. For example, the current rise time is approximately Imin * L / (VC1 - VC2), where Imin is the smaller of the two values, L is the inductance value of the inductor, VC1 is the voltage across the input capacitor C1, and VC2 is the voltage across the output capacitor C2. In the initial state, VC2 is 0. Next, the on-set time TS1 is obtained by appropriately shortening the current rise time based on this.

In S206, when the BUCK circuit is powered on, the first switch transistor is controlled to turn on. When the on time of the first switch transistor reaches the set on time, the first switch transistor is controlled to turn off. When it is determined that the first switch transistor satisfies the preset off condition, the first switch transistor is controlled to turn on. This process is repeated sequentially until the output voltage of the BUCK circuit reaches the target voltage.

Specifically, as shown in Figure 2, when the BUCK circuit is powered on, the first switch transistor Q1 is first controlled to turn on. At this time, the input capacitor C1 charges the output capacitor C2 via the first switch transistor Q1 and inductor L1, and the charging current of the BUCK circuit continues to rise from zero. When the on time of the first switch transistor Q1 reaches the on-set time TS1, the charging current of the BUCK circuit approaches the smaller of the current rating of the first switch transistor Q1 or the saturation current of the inductor L1. At this point, the first switch transistor Q1 is controlled to turn off to avoid breakdown of the first switch transistor Q1 and saturation of the inductor L1 due to the continuously rising charging current.

When the first switch transistor Q1 is turned off, the inductor L1 continues to charge the output capacitor C2 via the diode D, causing the voltage across the output capacitor C2 to continue rising and the charging current of the BUCK circuit to decrease. When the first switch transistor Q1 satisfies the preset off condition, the first on-off cycle of the first switch transistor Q1 ends. Subsequently, the first switch transistor Q1 is controlled to be turned on, and when the on time reaches the on-setting time TS1, the first switch transistor Q1 is controlled to be turned off. When the first switch transistor Q1 satisfies the preset off condition, the second on-off cycle of the first switch transistor Q1 ends. This process is repeated until the output voltage of the BUCK circuit reaches the target voltage (which is less than the input voltage). At this point, the on-off of the first switch transistor Q1 no longer generates a large inrush current that would affect circuit safety, and the BUCK circuit can stop executing step S206 and enter normal control logic.

In the above embodiment, the on-setting time is determined according to the current withstand capability of the switch transistor and the saturation current of the inductor. When the BUCK circuit is powered on, the switch transistor is controlled to turn off when its on-time reaches the on-setting time, and to turn on again when a preset off condition is met. This process is repeated until the output voltage reaches the target voltage. This effectively ensures the safety of the BUCK circuit during power-on by preventing the inductor current from damaging any elements in the circuit.

In some embodiments, the step of determining that the first switch transistor satisfies a preset off condition includes the steps of obtaining the current of the inductor during the off period of the first switch transistor, and determining that the first switch transistor satisfies the preset off condition when the current of the inductor drops to zero.

Specifically, as shown in Figure 9a, the first switch transistor Q1 is initially turned on. When the on-time of the first switch transistor Q1 reaches the on-set time TS1, the first switch transistor Q1 is controlled to be turned off, and the current of inductor L1 is acquired. When the current of inductor L1 reaches zero, the first switch transistor Q1 is controlled to be turned on again, and the first on/off cycle ends. Subsequent on/off cycles proceed similarly.

Furthermore, in the second on/off cycle, when the first switch transistor Q1 is turned on, the charging current continues to rise from zero. However, as can be seen from the inductor current calculation formula, the addition of VC2 reduces the rate at which the inductor current rises. Therefore, even with the same on-setting time TS1, the maximum current rise of the inductor current is reduced. This ensures that the charging current does not exceed the smaller of the current rating of the first switch transistor Q1 and the saturation current of the inductor L1. Simultaneously, because the rate at which the inductor current rises decreases and the stored energy of the inductor L1 decreases, when the first switch transistor Q1 is turned off, the charging current quickly drops to zero. As can be seen from the figure, the off time of the first switch transistor Q1 in the second on/off cycle is clearly shorter than that of the first on/off cycle. The same applies to subsequent on/off cycles.

This ensures the safety of the BUCK circuit by controlling the first switch transistor to turn off according to a first time interval during the first on-period of the first switch transistor, which is the time it takes for the inductor current to decrease from its maximum current to zero. This prevents the charging current from exceeding the current rating of the first switch transistor or the saturation current of the inductor when the BUCK circuit is powered on.

In some other embodiments, the step of determining that the first switch transistor has met a preset off condition includes the steps of: obtaining the current of the inductor during the off period of the first switch transistor; and determining that the first switch transistor has met a preset off condition when the current of the inductor drops to a preset current threshold.

The pre-set current threshold is a value greater than zero, but this value must be used to ensure that the charging current of the BUCK circuit does not exceed the current rating of the first switch transistor Q1 or that the inductor L1 does not saturate during subsequent on/off cycles. Specifically, this value can be obtained in advance through theoretical calculations or tests, and is not limited thereto.

Specifically, as shown in Figure 9b, the first switch transistor Q1 is initially turned on. When the on-time of the first switch transistor Q1 reaches the on-setting time TS1, the first switch transistor Q1 is controlled to be turned off, and the current of inductor L1 is acquired. Simultaneously, the current of inductor L1 is acquired, and when the current of inductor L1 reaches a preset current threshold, the first switch transistor Q1 is controlled to be turned on, ending the first on/off cycle. The same procedure is followed for subsequent on/off cycles.

Furthermore, when the first switch transistor Q1 is turned on during the second on/off cycle, the charging current continues to rise from a preset current threshold. While the charging current does not start rising from zero, if the preset current threshold is reasonably set and the rate of increase of the inductor current during the second on/off cycle is small, then even with the same on-setting time TS1, the maximum current rise of the inductor current can be made smaller than the smaller of the current rating of the first switch transistor Q1 and the saturation current of the inductor L1. This ensures that the first switch transistor Q1 does not break down and become damaged, and that the inductor L1 does not saturate.

In some other embodiments, the step of determining that the first switch transistor satisfies a preset off condition includes obtaining the off time of the first switch transistor and determining that the first switch transistor satisfies the preset off condition when the off time of the first switch transistor reaches a second set time greater than the on set time.

In other words, the pre-set off condition can be defined as the off time of the first switch transistor Q1 reaching the second set time TS2. The second set time TS2 is a fixed value greater than the on set time TS1. For example, the second set time TS2 can be set to a value greater than the on set time TS1, thereby ensuring that the charging current for each subsequent on/off cycle does not exceed the smaller of the current rating of the first switch transistor Q1 and the saturation current of the inductor L1.

As shown in Figure 9c, when the second set time TS2 is set to a large value, the inductor L1 is completely discharged and the charging current drops to zero before the off time of the first switch transistor Q1 reaches the second set time TS2. When the next on/off cycle arrives, the first switch transistor Q1 is turned on, and the charging current continues to rise from zero. However, as can be seen from the inductor current calculation formula di/dt = (VC1 - VC2)/L, VC2 is added, and the rate of increase of the inductor current decreases. Therefore, even with the same on set time TS1, the maximum current at which the inductor current rises becomes smaller, and it is guaranteed that the charging current does not exceed the smaller of the current rating of the first switch transistor Q1 and the saturation current of the inductor L1. Simultaneously, because the rate of increase of the inductor current decreases and the stored energy of the inductor L1 decreases, when the first switch transistor Q1 is turned off, the charging current rapidly drops to zero. As can be seen from the figure, the time during which the current is zero during the second on/off cycle increases. The same applies to subsequent on/off cycles.

This ensures the safety of the BUCK circuit by setting a second setting time that is larger than the on-setting time of the first switch transistor, and controlling the first switch transistor to be turned off based on this setting time. This prevents the charging current from exceeding the current rating of the first switch transistor or the saturation current of the inductor when the BUCK circuit is powered on.

In some other embodiments, the step of determining that the first switch transistor satisfies a preset off condition includes: obtaining the maximum current of the inductor during the first on period of the first switch transistor; determining a first time at which the maximum current drops to zero; and determining that the first switch transistor satisfies a preset off condition when the off time of the first switch transistor reaches a first time.

Specifically, as shown in Figure 9d, the first switch transistor Q1 is initially turned on, and when the on-time of the first switch transistor Q1 reaches the on-set time TS1, the current of inductor L1 is acquired. This current is the maximum current of inductor L1 when the first switch transistor Q1 is initially turned on. Subsequently, the first switch transistor Q1 is controlled to be turned off, and timing begins. Simultaneously, the current of inductor L1 is acquired, and when the current of inductor L1 reaches zero, timing is stopped. The time it takes for the current of inductor L1 to decrease from the maximum current to zero is acquired and defined as the first time T1. Then, the second on-off cycle begins. Within this cycle, the first switch transistor Q1 is first controlled to be turned on, and when the on-time of the first switch transistor Q1 reaches the on-set time TS1, the first switch transistor Q1 is controlled to be turned off. When the off-time reaches the first time T1, the second on-off cycle ends. The process is similar for subsequent cycles.

In the second on/off cycle, the first switch transistor Q1 is turned on, and the charging current continues to rise from zero. However, as can be seen from the inductor current calculation formula, the addition of VC2 reduces the rate at which the inductor current rises. Therefore, even with the same on-setting time TS1, the maximum current rise of the inductor current is reduced. This ensures that the charging current does not exceed the smaller of the current rating of the first switch transistor Q1 and the saturation current of the inductor L1. Simultaneously, because the rate at which the inductor current rises decreases and the stored energy of the inductor L1 decreases, when the first switch transistor Q1 is turned off, the charging current quickly drops to zero. As can be seen from the figure, the time during which the current is zero in the second on/off cycle increases. The same applies to subsequent on/off cycles.

This ensures that, during the initial on-period of the first switch transistor, the first switch transistor is turned off according to a first time interval during which the inductor current decreases from maximum to zero. This prevents the charging current from exceeding the current rating of the first switch transistor or the saturation current of the inductor when the BUCK circuit is powered on, thereby ensuring the safety of the BUCK circuit. Furthermore, compared to the method shown in Figure 5c, the power-on time of the BUCK circuit is shortened, improving the power-on speed of the BUCK circuit.

In some other embodiments, the step of determining that the first switch transistor satisfies a preset off condition includes: obtaining the maximum current of the inductor during the first on period of the first switch transistor; determining a second time at which the maximum current decreases to a preset current threshold; and determining that the first switch transistor satisfies a preset off condition when the off time of the first switch transistor reaches the second time.

The pre-set current threshold is a value greater than zero, but this value must ensure that the charging current of the BUCK circuit does not exceed the current rating of the first switch transistor Q1 or that the inductor L1 does not saturate during subsequent on/off cycles. Specifically, this value can be obtained in advance through theoretical calculations or tests, and is not limited thereto.

Specifically, as shown in Figures 5e-9g, the first switch transistor Q1 is initially turned on, and when the on-time of the first switch transistor Q1 reaches the on-setting time TS1, the current of inductor L1 is acquired. This current is the maximum current of inductor L1 when the first switch transistor Q1 is initially turned on. Subsequently, the first switch transistor Q1 is controlled to be turned off, and timing is started, and the current of inductor L1 is acquired. When the current of inductor L1 reaches a preset current threshold, timing is stopped, and the time it takes for the current of inductor L1 to decrease from the maximum current to the preset current threshold is acquired, which is defined as the second time T2. Then, the second on-off cycle begins. Within this cycle, the first switch transistor Q1 is first controlled to be turned on, and when the on-time of the first switch transistor Q1 reaches the on-setting time TS1, the first switch transistor Q1 is controlled to be turned off, and when the off-time reaches the second time T2, the second on-off cycle ends. The process is similar for subsequent cycles.

Furthermore, when the first switch transistor Q1 is turned on during the second on/off cycle, the charging current continues to rise from a preset current threshold. While the charging current does not start rising from zero, if the preset current threshold is reasonably set and the rate of increase of the inductor current during the second on/off cycle is small, then even with the same on-setting time TS1, the maximum current rise of the inductor current can be made smaller than the smaller of the current rating of the first switch transistor Q1 and the saturation current of the inductor L1. This ensures that the first switch transistor Q1 does not break down and become damaged, and that the inductor L1 does not saturate.

Furthermore, depending on the preset current threshold setting, there are multiple possible outcomes at the end of the second on/off cycle. As shown in Figure 9e, if the charging current drops to exactly zero at the end of the second on/off cycle, as can be seen from the analysis above, if the current continues to rise from zero, it is possible to ensure that the charging current is less than the smaller of the current withstand voltage of the first switch transistor Q1 and the saturation current of the inductor L1. As shown in Figure 9f, if the charging current has already dropped to zero when the second on/off cycle ends, as can be seen from the analysis above, if the current continues to rise from zero, it is possible to ensure that the charging current is less than the smaller of the current withstand voltage of the first switch transistor Q1 and the saturation current of the inductor L1. As shown in Figure 9g, when the second on/off cycle ends, the charging current has not dropped to zero, but since the current has fallen below the preset current threshold, based on the analysis at the start of the second on/off cycle, the charging current for the third on/off cycle will be less than the smaller of the current withstand voltage of the first switch transistor Q1 and the saturation current of the inductor L1. As can be seen from the above, in all of the above cases, the charging current can be made smaller than the smaller of the current rating of the first switch transistor Q1 and the saturation current of the inductor L1 during each on/off cycle of the first switch transistor Q1.

This allows the first switch transistor to be turned off according to a second time interval during its initial on-period, when the inductor current decreases from the maximum current to a preset current threshold. This ensures that the charging current does not exceed the current rating of the first switch transistor or the saturation current of the inductor when the BUCK circuit is powered on, thereby ensuring the safety of the BUCK circuit. Furthermore, compared to the method shown in Figures 9c-9d, this method shortens the power-on time of the BUCK circuit and improves its power-on speed.

In some embodiments, as shown in Figure 3, when the flyback element in the BUCK circuit is the second switch transistor Q2, the power-on control method further includes the steps of: controlling the second switch transistor to turn off when the first switch transistor is turned on, and controlling the second switch transistor to turn on when the first switch transistor is turned off.

Specifically, as shown in Figures 3 and 10a-10g, when the BUCK circuit is powered on, the first switch transistor Q1 is controlled to turn on, and the second switch transistor Q2 is controlled to turn off. At this time, the input capacitor C1 charges the output capacitor C2 via the first switch transistor Q1 and inductor L1, and the charging current of the BUCK circuit continues to rise from zero. When the on time of the first switch transistor Q1 reaches the on-set time TS1, the charging current of the BUCK circuit approaches the smaller of the current rating of the first switch transistor Q1 or the saturation current of the inductor L1. At this time, the first switch transistor Q1 is controlled to turn off, and the second switch transistor Q2 is controlled to turn on, allowing current to flow through the second switch transistor Q2 to avoid breakdown of the first switch transistor Q1 and saturation of the inductor L1 due to the continuously rising charging current.

When the first switch transistor Q1 is turned off and the second switch transistor Q2 is turned on, the inductor L1 continues to charge the output capacitor C2 by the second switch transistor Q2, the voltage across the output capacitor C2 continues to rise, and the charging current of the BUCK circuit decreases. When the first switch transistor Q1 satisfies the preset off condition, the first on-off cycle of the first switch transistor Q1 ends. After that, the first switch transistor Q1 is controlled to be turned on and the second switch transistor Q2 is turned off. When the on time reaches the on-setting time TS1, the first switch transistor Q1 is controlled to be turned off and the second switch transistor Q2 is turned on. When the first switch transistor Q1 satisfies the preset off condition, the second on-off cycle of the first switch transistor Q1 ends. This is repeated until the output voltage of the BUCK circuit reaches the target voltage (which is less than the input voltage). At this point, the on/off switching of the first switch transistor Q1 and the second switch transistor Q2 no longer generates a large inrush current that could affect the safety of the circuit. The BUCK circuit then stops executing step S206 and can enter normal control logic.

In the above embodiment, the on-setting time is determined according to the current withstand capability of the switch transistor and the saturation current of the inductor. When the BUCK circuit is powered on, the switch transistor is controlled to turn off when its on-time reaches the on-setting time, and to turn on again when a preset off condition is met. This process is repeated until the output voltage reaches the target voltage. This effectively ensures the safety of the BUCK circuit during power-on by preventing the charging current of the BUCK circuit from damaging any elements in the circuit.

In some embodiments, when the second switch transistor is on, the power-on control method further includes the step of controlling the second switch transistor to turn off prematurely if the inductor current drops to zero and the first switch transistor does not satisfy a preset off condition.

Specifically, let's first consider the case where the preset off condition is that the off time of the first switch transistor Q1 reaches the second set time TS2. As shown in Figure 10c, when the second set time TS2 is set to a large value, the inductor L1 is completely discharged and the charging current drops to zero before the off time of the first switch transistor Q1 reaches the second set time TS2. At this time, the second switch transistor Q2 can be controlled to be turned off early. In specific implementation, when the on time of the first switch transistor Q1 reaches the on set time TS1, the current of the inductor L1 is acquired, and when the current of the inductor L1 drops to zero, the second switch transistor Q2 is controlled to be turned off.

Furthermore, let's consider an example where the preset off condition is that the off time of the first switch transistor Q1 reaches the first time T1. As shown in Figure 10d, in the first on/off cycle, when the off time of the first switch transistor Q1 reaches the first time T1 and the charging current drops to exactly zero, the second switch transistor Q2 is controlled to be turned off accordingly. In the second on/off cycle, when the off time of the first switch transistor Q1 has not yet reached the first time T1, if the inductor L1 is completely discharged and the charging current drops to zero, the second switch transistor Q2 can be controlled to be turned off early. Specifically, when the on time of the first switch transistor Q1 reaches the on-setting time TS1, the current of the inductor L1 is acquired, and when the current of the inductor L1 drops to zero, the second switch transistor Q2 can be controlled to be turned off.

Furthermore, let us consider an example where the pre-set off condition is that the off time of the first switch transistor Q1 reaches the second time T2. As shown in Figures 10e-10g, in the first on/off cycle, the off time of the first switch transistor Q1 reaches the second time T2, and the charging current has not yet decreased to zero. However, due to the constraint of the second time T2, the second switch transistor Q2 is turned off and prepared for the next on/off cycle. In the subsequent on/off cycle, the off time of the first switch transistor Q1 reaches the second time T2, but there are several possibilities: the charging current has not yet decreased to zero, the charging current has just decreased to zero, or the charging current has already decreased to zero. If the current has not yet dropped to zero, the second switch transistor Q2 is controlled to turn off based on the constraint of the second time T2, as shown in Figure 10g. If the current has just dropped to zero, the second switch transistor Q2 is controlled to turn off based on the constraint of the second time T2, as shown in Figure 10e. If the current has already dropped to zero, the second switch transistor Q2 is turned off prematurely, as shown in Figure 10f. In specific implementation, when the on time of the first switch transistor Q1 reaches the on-set time TS1, the current of inductor L1 is acquired, and when the current of inductor L1 drops to zero, the second switch transistor Q2 is controlled to turn off.

Furthermore, in the case of a BUCK circuit where the flyback element is a second switch transistor, the only difference from a circuit where the flyback element is a diode is the control of the second switch transistor; the control of the first switch transistor is the same, thus achieving the same effect as when the flyback element is a diode. See above for specifics; they will not be repeated here.

In the above embodiment, a second switch transistor is used instead of a diode. When the inductor current drops to zero and the off-time of the first switch transistor has not reached the off-set time, the second switch transistor is controlled to turn off early. This prevents impact on subsequent functions, reduces circuit losses, and thereby optimizes the power-on control method.

Based on the above, the power-on control method for the BUCK circuit according to the embodiment of this disclosure determines the set current according to the smaller of the current-tolerant current of the first switch transistor in the BUCK circuit and the saturation current of the inductor. When the BUCK circuit is powered on, the first switch transistor is controlled to turn on to acquire the inductor current. When the inductor current reaches the set current, the on time of the first switch transistor is determined, the off-setting time of the first switch transistor is determined according to the on time, and the first switch transistor is controlled to turn off. When the off time of the first switch transistor reaches the off-setting time, the first switch transistor is controlled to turn on, and this is repeated until the output voltage of the BUCK circuit reaches the target voltage. This prevents the inductor current from damaging each element in the circuit during power-on, effectively ensuring the safety of the BUCK circuit during power-on.

In accordance with the above embodiments, the embodiments of this disclosure further provide a controller for a BUCK circuit.

Figure 11 is a schematic diagram of the structure of a BUCK circuit controller according to one embodiment of the present disclosure. As shown in Figure 11, the controller 130 includes a memory 131, a processor 132, and a power-on control program for the BUCK circuit stored in the memory 131 and operable on the processor 132. When the processor 132 executes the power-on control program for the BUCK circuit, it implements the aforementioned power-on control method.

The controller for the BUCK circuit according to the embodiment of this disclosure implements the aforementioned power-on control method on the BUCK circuit, thereby reducing the inductor current of the BUCK circuit to less than the current withstand capability of the switch transistor and the saturation current of the inductor during power-on. This prevents the inductor current from damaging any elements in the circuit, effectively ensuring the safety of the BUCK circuit during power-on.

Corresponding to the above embodiment, the embodiment of this disclosure further provides a computer-readable storage medium in which a power-on control program for the BUCK circuit is stored. When the power-on control program for the BUCK circuit is executed by the processor, the aforementioned power-on control method for the BUCK circuit is realized.

The computer-readable storage medium according to the embodiments of this disclosure, through the aforementioned power-on control method, can ensure that the inductor current of the BUCK circuit is kept below the current rating of the switch transistor and the saturation current of the inductor during power-on. This prevents the inductor current from damaging any elements in the circuit, effectively ensuring the safety of the BUCK circuit during power-on.

In accordance with the above embodiment, the embodiment of this disclosure further provides a power-on control device for a BUCK circuit.

Figure 12 is a schematic diagram of the structure of a power-on control device for a BUCK circuit according to one embodiment of the present disclosure. As shown in Figure 12, the power-on control device 200 comprises a determination module 210 and a control module 220.

The determination module 210 is used to determine the current withstand capability of the first switch transistor in the BUCK circuit, the saturation current of the inductor in the BUCK circuit, and to determine the set current according to the smaller of the current withstand capability and the saturation current. The control module 220 is used to control the first switch transistor to turn on when the BUCK circuit is powered on, to acquire the inductor current, to determine the on-time of the first switch transistor when the inductor current reaches the set current, to determine the off-setting time of the first switch transistor according to the on-time, and to control the first switch transistor to turn off. When the off-time of the first switch transistor reaches the off-setting time, the first switch transistor is controlled to turn on, and this process is repeated until the output voltage of the BUCK circuit reaches the target voltage.

According to one embodiment of this disclosure, the control module 220 is specifically used to determine the control period of the first switch transistor, to identify the time difference between the on time and the control period if the on time is greater than or equal to the control period, to set the difference between the control period and the time difference as the off-setting time if the on time is less than the control period, and to set the difference between the control period and the on time as the off-setting time if the on time is less than the control period.

According to one embodiment of this disclosure, the control module 220 is specifically used to determine a first time when the first switch transistor is first turned on, the time at which the inductor current rises to its maximum current value, and to control the first switch transistor to turn off; to determine a second time when the inductor current falls from its maximum current value to zero; and to define the control period as the sum of the first time and the second time.

According to one embodiment of this disclosure, the control module 220 is specifically used to determine a first time when the first switch transistor is first turned on, the time at which the inductor current rises to its maximum current value, control the first switch transistor to turn it off, determine a third time at which the inductor current drops from the maximum current value to a preset current threshold greater than zero, and set the sum of the first time and the third time as the control period.

According to one embodiment of this disclosure, when the flyback element in the BUCK circuit is a second switch transistor, the control module 220 is further used to control the second switch transistor to be turned off when the first switch transistor is turned on, and to control the second switch transistor to be turned on when the first switch transistor is turned off.

According to one embodiment of this disclosure, when the second switch transistor is ON, the control module 220 is further used to control the second switch transistor to turn OFF early if the inductor current drops to zero and the OFF time of the first switch transistor has not reached the OFF setting time.

Furthermore, regarding the explanation of the power-on control device for the BUCK circuit in this disclosure, please refer to the related explanation of the power-on control method for the BUCK circuit in this disclosure; specific details will not be repeated here.

The power-on control device according to the embodiment of this disclosure uses a determination module to identify the current withstand capability of the first switch transistor in the BUCK circuit and the saturation current of the inductor in the BUCK circuit, and determines a set current according to the smaller of the withstand capability and saturation current. When the BUCK circuit is powered on, the control module controls the first switch transistor to turn on and acquires the inductor current. When the inductor current reaches the set current, the control module identifies the on time of the first switch transistor and determines the off-set time of the first switch transistor according to the on time. The control module controls the first switch transistor to turn off, and when the off time of the first switch transistor reaches the off-set time, it controls the first switch transistor to turn on, repeating this process until the output voltage of the BUCK circuit reaches the target voltage. This effectively ensures the safety of the BUCK circuit during power-on by preventing the inductor current from damaging the elements in the circuit.

Figure 13 is a schematic diagram of the structure of a power-on control device for a BUCK circuit according to one embodiment of the present invention. As shown in Figure 13, the power-on control device 300 comprises a first decision module 310, a second decision module 320, and a control module 330.

The first determination module 310 is used to determine the current withstand capability of the first switch transistor in the BUCK circuit and the saturation current of the inductor in the BUCK circuit. The second determination module 320 is used to determine the current rise time according to the smaller of the current withstand capability and saturation current, and to determine the on-set time of the first switch transistor according to the current rise time. The control module 330 is used to control the first switch transistor to turn on when the BUCK circuit is powered on, to turn off the first switch transistor when the on-time of the first switch transistor reaches the on-set time, and to control the first switch transistor to turn on when it is determined that the first switch transistor satisfies a preset off condition, repeating this process until the output voltage of the BUCK circuit reaches the target voltage.

According to one embodiment of the present invention, the control module 330 is specifically used to acquire the inductor current during the off period of the first switch transistor, and to determine that the first switch transistor satisfies a preset off condition when the inductor current drops to zero.

According to another embodiment of the present invention, the control module 330 is specifically used to acquire the inductor current during the off period of the first switch transistor, and to determine that the first switch transistor satisfies a preset off condition when the inductor current drops to a preset current threshold.

According to another embodiment of the present invention, the control module 330 is specifically used to acquire the off time of the first switch transistor and to determine that the first switch transistor satisfies a preset off condition when the off time of the first switch transistor reaches a second set time, wherein the second set time is greater than the on set time.

According to another embodiment of the present invention, the control module 330 is specifically used to obtain the maximum current of the inductor during the initial on-period of the first switch transistor, to identify a first time at which the maximum current drops to zero, and to determine that the first switch transistor satisfies a preset off condition when the off-period of the first switch transistor reaches a first time.

According to another embodiment of the present invention, the control module 330 is specifically used to obtain the maximum current of the inductor during the initial on-period of the first switch transistor, to identify a second time when the maximum current drops to a preset current threshold, and to determine that the first switch transistor satisfies a preset off condition when the off-period of the first switch transistor reaches the second time.

According to one embodiment of the present invention, when the flyback element in the BUCK circuit is a second switch transistor, the control module 330 is further used to control the second switch transistor to the off state when the first switch transistor is turned on, and to control the second switch transistor to the on state when the first switch transistor is turned off.

According to one embodiment of the present invention, when the second switch transistor is on, the control module 330 is further used to control the second switch transistor to turn off early if the inductor current drops to zero and the first switch transistor does not meet a preset off condition.

Regarding the explanation of the power-on control device for the BUCK circuit in this application, please refer to the related explanation of the power-on control method for the BUCK circuit in this application; specific details will not be repeated here.

In accordance with the above embodiments, the embodiments of this disclosure further provide a BUCK circuit.

Figure 14 is a circuit diagram of a BUCK circuit according to one embodiment of the present disclosure. As shown in Figure 14, the BUCK circuit 100 comprises an input capacitor C1, a first switch transistor Q1, a flyback element XL, an inductor L1, an output capacitor C2, an output voltage detection module 110, a current detection module 120, and a controller 130.

One end of the first switch transistor Q1 is connected to one end of the input capacitor C1, one end of the flyback element XL is connected to the other end of the first switch transistor Q1, the other end of the flyback element XL is connected to the other end of the input capacitor C1, one end of the inductor L1 is connected to the other end of the first switch transistor Q1, one end of the output capacitor C2 is connected to the other end of the inductor L1, and the other end of the output capacitor C2 is connected to the other end of the flyback element XL.

The output voltage detection module 110 is used to detect the output voltage of the BUCK circuit, the current detection module 120 is used to detect the inductor current, and the controller 130 is used to determine the current withstand capability of the first switch transistor Q1 and the saturation current of the inductor L1, and to determine the set current according to the smaller of the current withstand capability and saturation current. The controller 130 is further used to control the first switch transistor Q1 to turn on when the BUCK circuit 100 is powered on, to obtain the inductor current IL, to determine the on time of the first switch transistor Q1 when the inductor current IL reaches the set current, to determine the off-set time of the first switch transistor Q1 according to the on time, and to control the first switch transistor Q1 to turn off. When the off time of the first switch transistor reaches the off-set time, the controller controls the first switch transistor Q1 to turn on, and repeats this process until the output voltage of the BUCK circuit 100 reaches the target voltage.

According to one embodiment of this disclosure, the controller 130 is specifically used to determine the control period of the first switch transistor, to identify the time difference between the on time and the control period if the on time is greater than or equal to the control period, to set the difference between the control period and the time difference as the off-setting time if the on time is less than the control period, and to set the difference between the control period and the on time as the off-setting time if the on time is less than the control period.

According to one embodiment of this disclosure, the controller 130 is specifically used to determine a first time when the first switch transistor is first turned on, the time it takes for the inductor current to rise to its maximum current value, and to control the first switch transistor to turn off; to determine a second time when the inductor current falls from its maximum current value to zero; and to define the control period as the sum of the first time and the second time.

According to one embodiment of this disclosure, the controller 130 is specifically used to determine a first time when the first switch transistor is first turned on, the time at which the inductor current rises to its maximum current value, and to control the first switch transistor to turn off; to determine a third time when the inductor current decreases from the maximum current value to a preset current threshold greater than zero; and to define the control period as the sum of the first time and the third time.

According to one embodiment of this disclosure, when the flyback element in the BUCK circuit is a second switch transistor, the controller 130 is further used to control the second switch transistor to be turned off when the first switch transistor is turned on, and to control the second switch transistor to be turned on when the first switch transistor is turned off.

According to one embodiment of this disclosure, when the second switch transistor is ON, the controller 130 is further used to control the second switch transistor to turn OFF early if the inductor current drops to zero and the OFF time of the first switch transistor has not reached the OFF setting time.

As shown in Figure 14, the BUCK circuit 100 comprises an input capacitor C1, a first switch transistor Q1, a flyback element XL, an inductor L1, an output capacitor C2, an output voltage detection module 110, and a controller 120.

One end of the first switch transistor Q1 is connected to one end of the input capacitor C1, one end of the flyback element XL is connected to the other end of the first switch transistor Q1, the other end of the flyback element XL is connected to the other end of the input capacitor C1, one end of the inductor L1 is connected to the other end of the first switch transistor Q1, one end of the output capacitor C2 is connected to the other end of the inductor L1, and the other end of the output capacitor C2 is connected to the other end of the flyback element XL.

The output voltage detection module 110 is used to detect the output voltage of the BUCK circuit 100. The controller 120 is used to determine the current withstand capability of the first switch transistor Q1 in the BUCK circuit 100, the saturation current of the inductor L1 in the BUCK circuit 100, and to determine the current rise time according to the smaller of the current withstand capability and saturation current. The controller 120 is also used to determine the on-set time TS1 of the first switch transistor Q1 according to the current rise time. Furthermore, the controller 120 controls the first switch transistor Q1 to be on when the BUCK circuit 100 is powered on, to be off when the on-time of the first switch transistor Q1 reaches the on-set time TS1, and to be on when it is determined that the first switch transistor Q1 satisfies a preset off condition. This process is repeated until the output voltage of the BUCK circuit 100 reaches the target voltage.

According to one embodiment of the present invention, the controller 120 is specifically used to acquire the inductor current during the off period of the first switch transistor, and to determine that the first switch transistor satisfies a preset off condition when the inductor current drops to zero.

According to another embodiment of the present invention, the controller 120 is specifically used to acquire the inductor current during the off period of the first switch transistor, and to determine that the first switch transistor satisfies a preset off condition when the inductor current drops to a preset current threshold.

According to another embodiment of the present invention, the controller 120 is specifically used to acquire the off time of the first switch transistor Q1 and to determine that the first switch transistor Q1 satisfies a preset off condition when the off time of the first switch transistor Q1 reaches a second set time, wherein the second set time is greater than the on set time.

According to another embodiment of the present invention, the controller 120 is specifically used to obtain the maximum current of the inductor L1 by the current detection module 130 during the initial ON period of the first switch transistor Q1, to identify a first time when the maximum current drops to zero, and to determine that the first switch transistor Q1 satisfies a preset OFF condition when the OFF time of the first switch transistor Q1 reaches a first time.

According to another embodiment of the present invention, the controller 120 is specifically used to obtain the maximum current of the inductor by the current detection module 130 during the initial on-period of the first switch transistor Q1, to identify a second time when the maximum current decreases to a preset current threshold, and to determine that the first switch transistor Q1 satisfies a preset off condition when the off-time of the first switch transistor Q1 reaches the second time.

According to one embodiment of the present invention, when the flyback element XL in the BUCK circuit is a second switch transistor, the controller 120 is further used to control the second switch transistor to the off state when the first switch transistor Q1 is turned on, and to control the second switch transistor to the on state when the first switch transistor Q1 is turned off.

According to one embodiment of the present invention, when the second switch transistor is ON, the controller 120 is further used to control the second switch transistor to turn OFF early if the current of the inductor L1 drops to zero and the first switch transistor Q1 does not satisfy a preset OFF condition.

For details regarding the BUCK circuit in this disclosure, please refer to the related explanation of the power-on control method for the BUCK circuit in this disclosure; specific details will not be repeated here.

According to the BUCK circuit of the embodiment of this disclosure, the controller identifies the current withstand capability of the first switch transistor and the saturation current of the inductor, and determines the set current according to the smaller of the two values. When the BUCK circuit is powered on, the controller controls the first switch transistor to be ON and acquires the inductor current. When the inductor current reaches the set current, the controller identifies the ON time of the first switch transistor, determines the OFF set time of the first switch transistor according to the ON time, and controls the first switch transistor to be OFF. When the OFF time of the first switch transistor reaches the OFF set time, the controller controls the first switch transistor to be ON, and this is repeated until the output voltage of the BUCK circuit reaches the target voltage. This effectively ensures the safety of the BUCK circuit during power-on by preventing the inductor current from damaging each element in the circuit.

Furthermore, the logic and/or steps shown in the flowchart or otherwise described herein can be thought of, for example, as an ordered list of executable instructions for realizing a logical function, which can be concretely realized on any computer-readable medium and used in or in combination with instruction execution systems, devices or equipment (for example, computer-based systems, which include a processor or a system that reads instructions from an instruction execution system, device or equipment and executes those instructions). For the purposes of this specification, “computer-readable medium” may be any device that contains, stores, communicates, propagates or transmits a program and can be used in combination with an instruction execution system, device or equipment or such instruction execution systems, devices or equipment. More specific examples of computer-readable mediums (a non-exclusive list) include electrical connections having one or more wires (electronic devices), portable computer disk cartridges (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), optical fiber devices, and portable disk read-only memory (CDROM). Furthermore, the computer-readable medium may, by extension, be paper or other suitable medium on which the program is printed. For example, the program may be acquired electronically by optically scanning paper or other suitable medium, and then editing, interpreting, or processing it in any other suitable manner as necessary, and then stored in computer memory.

It should be understood that each part of this disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the embodiments described above, multiple steps or methods can be implemented in software or firmware stored in memory and executed by an appropriate instruction execution system. When implemented in hardware, as in other embodiments, it can be implemented in any or a combination of technologies known in the art, such as discrete logic circuits having logic gate circuits for implementing logic functions for data signals, dedicated integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), and field-programmable gate arrays (FPGAs).

In this specification, the terms "one embodiment," "several embodiments," "examples," "specific examples," or "several examples" mean that the specific features, structures, materials, or characteristics described in combination with such embodiments or examples are included in at least one embodiment or example of this disclosure. In this specification, the exemplary descriptions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be appropriately combined in any one or more embodiments or examples.

Furthermore, the terms “first” and “second” are used solely for descriptive purposes and should not be understood as indicating the number of technical features of relative importance, either explicitly or implicitly. Therefore, features limited by “first” and “second” may explicitly or implicitly include at least one such feature. In this disclosure, “multiple” means at least two, for example, two, three, etc., unless otherwise specified.

In this disclosure, terms such as “attachment,” “connection,” “connection,” and “fixing” should be understood broadly unless otherwise specified and limited. For example, they may refer to fixed connections, detachable connections, integrated connections, mechanical connections, electrical connections, direct connections, indirect connections via an intermediate medium, internal communication between two elements, or interaction relationships between two elements. Unless otherwise explicitly limited, the specific meaning of these terms in this disclosure can be understood by those skilled in the art, depending on the context.

Although examples of the present disclosure have been described, these examples are illustrative and should not be understood as limiting the disclosure. Those skilled in the art will understand that various changes, modifications, substitutions, and variations are possible within the scope of the present disclosure.

Claims (17)

A method for controlling the power-on of a BUCK circuit,
The steps include: determining the current withstand capability of the first switch transistor in the BUCK circuit and determining the saturation current of the inductor in the BUCK circuit;
The steps include determining the set current and current rise time according to the smaller of the withstand current and the saturation current,
The steps include determining the ON setting time of the first switch transistor according to the current rise time,
A power-on control method for a BUCK circuit, characterized by including the step of switching the state of the first switch transistor according to the inductor current and the set current, or switching the state of the first switch transistor according to the on time of the first switch transistor and the on-set time, until the output voltage of the BUCK circuit reaches a target voltage when the BUCK circuit is powered on. The step of switching the state of the first switch transistor according to the inductor current and the set current is:
A power-on control method for a BUCK circuit according to claim 1, characterized in that when the BUCK circuit is powered on, the first switch transistor is controlled to turn on, an inductor current is obtained, when the inductor current reaches the set current, the on time of the first switch transistor is determined, the off setting time of the first switch transistor is determined according to the on time, the first switch transistor is controlled to turn off, and when the off time of the first switch transistor reaches the off setting time, the first switch transistor is controlled to turn on, and this process is repeated sequentially until the output voltage of the BUCK circuit reaches a target voltage. The step of determining the off setting time of the first switch transistor according to the on time is:
The steps include determining the control period of the first switch transistor,
When the ON time is equal to or greater than the control cycle, the time difference between the ON time and the control cycle is identified, and the difference between the control cycle and the time difference is set to the OFF setting time.
The power-on control method for a BUCK circuit according to claim 2, characterized by including the step of setting the difference between the control period and the on time to the off setting time when the on time is smaller than the control period. The step of determining the control period of the first switch transistor is:
The steps include: identifying a first time when the first switch transistor is first turned on, the inductor current rising to its maximum current value, controlling the first switch transistor to turn off, and identifying a second time when the inductor current falling from the maximum current value to zero;
The power-on control method for a BUCK circuit according to claim 3, characterized by including the step of setting the control period to be the sum of the first time and the second time. The step of determining the control period of the first switch transistor is:
The steps include: identifying a first time when the first switch transistor is first turned on, the inductor current rising to a maximum current value, controlling the first switch transistor to turn off, and identifying a third time when the inductor current drops from the maximum current value to a preset current threshold greater than zero;
The power-on control method for a BUCK circuit according to claim 3, characterized by including the step of setting the control period to be the sum of the first time and the third time. The step of switching the state of the first switch transistor according to the on time of the first switch transistor and the on-setting time is:
A power-on control method for a BUCK circuit according to claim 1, characterized in that it includes the step of controlling the first switch transistor to turn on when the BUCK circuit is powered on, controlling the first switch transistor to turn off when the on time of the first switch transistor reaches the on-set time, and controlling the first switch transistor to turn on when it is determined that the first switch transistor satisfies a preset off condition, and repeating this sequentially until the output voltage of the BUCK circuit reaches a target voltage. The step of determining that the first switch transistor satisfies a preset off condition is:
The steps include obtaining the current of the inductor during the off period of the first switch transistor,
The power-on control method for a BUCK circuit according to claim 6, comprising the step of determining that the first switch transistor satisfies a preset off condition when the current of the inductor drops to zero. The step of determining that the first switch transistor satisfies a preset off condition is:
The steps include obtaining the current of the inductor during the off period of the first switch transistor,
The power-on control method for a BUCK circuit according to claim 6, comprising the step of determining that the first switch transistor satisfies a preset off condition when the current of the inductor drops to a preset current threshold. The step of determining that the first switch transistor satisfies a preset off condition is:
The power-on control method for a BUCK circuit according to claim 6, comprising the step of obtaining the off time of the first switch transistor, and determining that the first switch transistor satisfies a preset off condition when the off time of the first switch transistor reaches a second set time, wherein the second set time is greater than the on set time. The step of determining that the first switch transistor satisfies a preset off condition is:
The steps include obtaining the maximum current of the inductor during the initial ON period of the first switch transistor,
A step of identifying a first time in which the maximum current decreases to zero,
The power-on control method for a BUCK circuit according to claim 6, comprising the step of determining that the first switch transistor satisfies a preset off condition when the off time of the first switch transistor reaches a first time. The step of determining that the first switch transistor satisfies a preset off condition is:
The steps include obtaining the maximum current of the inductor during the initial ON period of the first switch transistor,
A step of identifying a second time at which the maximum current decreases to a preset current threshold,
The power-on control method for a BUCK circuit according to claim 6, comprising the step of determining that the first switch transistor satisfies a preset off condition when the off time of the first switch transistor reaches a second time. When the flyback element in the BUCK circuit is a second switch transistor, the power-on control method for the BUCK circuit is:
When the first switch transistor is controlled to turn on, the second switch transistor is controlled to turn off,
The power-on control method for a BUCK circuit according to claim 2 , further comprising the step of controlling the second switch transistor to turn on when controlling the first switch transistor to turn off. When the second switch transistor is on, the power-on control method for the BUCK circuit is as follows:
The power-on control method for a BUCK circuit according to claim 12, further comprising the step of controlling the second switch transistor to turn off early if the inductor current drops to zero and the off time of the first switch transistor has not reached the off-setting time. A controller for a BUCK circuit, comprising memory, a processor, and a BUCK circuit power-on control program stored in memory and operable on the processor, wherein when the processor executes the BUCK circuit power-on control program, it implements the BUCK circuit power-on control method described in any one of claims 1 to 13. A computer-readable storage medium characterized in that it stores a power-on control program for a BUCK circuit, and when the power-on control program for the BUCK circuit is executed by a processor, the power-on control method for the BUCK circuit described in any one of claims 1 to 13 is realized. A power-on control device for a BUCK circuit,
A determination module for determining the current withstand capability of the first switch transistor in the BUCK circuit, determining the saturation current of the inductor in the BUCK circuit, determining the set current and current rise time according to the smaller of the current withstand capability and the saturation current, and determining the ON setting time of the first switch transistor according to the current rise time,
A power-on control device for a BUCK circuit, comprising: a control module for switching the state of the first switch transistor according to the inductor current and the set current, or for switching the state of the first switch transistor according to the on time of the first switch transistor and the on-set time, until the output voltage of the BUCK circuit reaches a target voltage when the BUCK circuit is powered on. It is a BUCK circuit,
Input capacitor and
One end of the first switch transistor is connected to one end of the input capacitor,
A flyback element is provided, with one end connected to the other end of the first switch transistor and the other end connected to the other end of the input capacitor.
One end is connected to an inductor that is connected to the other end of the first switch transistor,
An output capacitor, one end of which is connected to the other end of the inductor and the other end of which is connected to the other end of the flyback element,
An output voltage detection module for detecting the output voltage of the aforementioned BUCK circuit,
A current detection module for detecting inductor current,
The system includes a controller for determining the current withstand capability of the first switch transistor, determining the saturation current of the inductor, determining the set current and current rise time according to the smaller of the current withstand capability and the saturation current, and determining the ON setting time of the first switch transistor according to the current rise time.
The controller is further used to switch the state of the first switch transistor according to the inductor current and the set current, or according to the on time of the first switch transistor and the on-set time, when the BUCK circuit is powered on, until the output voltage of the BUCK circuit reaches a target voltage.