JP7842707B2 - Power conversion circuit control device - Google Patents

Description

This invention relates to a power conversion circuit control device, and more particularly to a device for controlling a plurality of power conversion circuits connected in parallel.

A power conversion circuit that couples two switching circuits with a transformer is widely used. The secondary switching circuit is connected to, for example, the electrical circuit installed in an electric vehicle, while the primary switching circuit is connected to, for example, the commercial power supply. Because the primary and secondary switching circuits are electrically isolated by the transformer, handling the commercial power supply becomes easier, even when a high-output voltage battery is installed.

Such power conversion circuits include those where the power transmitted from the primary side to the secondary side is determined by the difference between the switching phase of the primary-side switching circuit and the switching phase of the secondary-side switching circuit, as shown in Patent Document 1 below.

Japanese Patent Publication No. 2022-160093

Yeh Ting, Sjoerd de Haan, Jan A. Ferreira: "Modular Single-active Bridge DC-DC Converters", IEEE IAS. Magazine, Vol. 22, No. 5, pp. 43-52 (2016)

When increasing the power supplied from a power conversion circuit to a load circuit, it becomes necessary to increase the voltage withstand or current allowable of the switching elements used in the power conversion circuit, which can make the design of the power conversion circuit difficult. Therefore, as described in Non-Patent Document 1, a parallel-type power conversion device, in which multiple power conversion circuits are connected in parallel, has been considered. However, in a parallel-type power conversion device, it is necessary to provide an ammeter for each power conversion circuit in order to control each one, which can make the configuration of the control device for the parallel-type power conversion device complex.

The present invention aims to simplify the configuration of a device that controls multiple power conversion circuits connected in parallel.

The present invention is characterized by performing the following steps: a control variable determination process to determine a total control variable based on the difference between the measured value of the current flowing at the parallel connection terminals of a plurality of parallel-connected power conversion circuits and the current command value; a superposition process to generate a plurality of disturbance superposition signals by individually superimposing a plurality of different disturbance signals onto the total control variable; an error extraction process to determine one or more error components corresponding to the plurality of different disturbance signals by extracting one or more components corresponding to the plurality of different disturbance signals from the total control variable; a correction coefficient determination process to determine a correction coefficient for each of the plurality of disturbance superposition signals based on the error components; and a control variable determination process to determine a control variable for each of the plurality of power conversion circuits by applying a correction process using the correction coefficient to each of the plurality of disturbance superposition signals.

Preferably, the multiple disturbance signals are represented by an orthogonal sequence of functions.

Preferably, the multiple disturbance signals are represented by multiple mutually orthogonal trigonometric functions.

Preferably, the multiple disturbance signals are represented by multiple disturbance functions, where there is a time period in which the value of one function becomes an active value and the values of the other functions become inactive values, and each function becomes an active value one by one as time progresses.

Preferably, the multiple disturbance signals are multiple signals obtained by applying a low-pass filter to each of the multiple signals represented by the multiple disturbance functions.

Preferably, the error extraction process includes a process of extracting each error component from the overall manipulated variable by multiplying the value based on the overall manipulated variable by a plurality of disturbance signals.

Preferably, the error extraction process involves multiplying the value based on the overall manipulated variable by multiple disturbance signals to obtain the average value of the multiple multiplied values, and then subtracting the average value from each of the multiple multiplied values to obtain each of the error components.

Preferably, the correction coefficient determination process includes performing a time integral over each error component and determining each correction coefficient based on a monotonically increasing function whose independent variable is the value based on the time integral of each error component.

Preferably, the system includes a switching control unit that controls each of the multiple power conversion circuits based on the manipulated variable for each of the power conversion circuits, each power conversion circuit comprising a primary-side switching circuit and a secondary-side switching circuit coupled by a transformer, and the switching control unit controls the difference between the switching phase of the primary-side switching circuit and the phase of the secondary-side switching circuit based on the manipulated variable.

According to the present invention, the configuration of a device that controls multiple power conversion circuits connected in parallel can be simplified.

This is a diagram showing the configuration of a parallel power converter. This diagram shows the configuration of a parallel-type power converter in which three power conversion circuits are connected in parallel. This is a diagram showing the computational model of a power conversion system. This diagram shows an example configuration of a power conversion system equipped with three power conversion circuits. This is a diagram showing the configuration of a power conversion system. This is a diagram showing the configuration of a power conversion system. This figure shows the results of a simulation conducted on a power conversion system. This figure shows the results of a simulation conducted on a power conversion system.

Embodiments of the present invention will be described with reference to the figures. Identical components shown in multiple drawings are denoted by the same reference numerals to simplify their description. The terms indicating directions such as "up" and "down" as defined in each figure are for explanatory convenience and do not limit the orientation of each component when it is positioned.

Figure 1 shows the configuration of a parallel power converter 100 according to the basic technology of the present invention. The parallel power converter 100 comprises a plurality (N) of power conversion circuits 10-1 to 10-N connected in parallel. Here, parallel connection means that one input terminal and the other input terminal of each power conversion circuit 10-i (i=1 to N) are connected to each other, and one output terminal and the other output terminal of each power conversion circuit 10-i are connected to each other.

The positive input terminal Tp1, one of the pair of input terminals of each power conversion circuit 10-i, is commonly connected to the parallel terminal TP1. The negative input terminal Tg1, the other of the pair of input terminals of each power conversion circuit 10-i, is commonly connected to the parallel terminal TG1. The positive output terminal Tp2, one of the pair of output terminals of each power conversion circuit 10-i, is commonly connected to the parallel terminal TP2. The negative output terminal Tg2, the other of the pair of output terminals of each power conversion circuit 10-i, is commonly connected to the parallel terminal TG2.

A DC power source 200 is connected to parallel terminals TP1 and TG1 (a pair of parallel connection terminals). A load circuit 202 is connected to parallel terminals TP2 and TG2 (a pair of parallel connection terminals). Each power conversion circuit 10-i switches, boosting or lowering the DC voltage output from the DC power source 200, and outputting it to the load circuit 202. This supplies DC power from the DC power source 200 to the load circuit 202. The boosting or lowering of the voltage by each power conversion circuit 10-i ensures that an appropriate voltage is applied to the load circuit 202. Furthermore, by connecting multiple power conversion circuits 10-1 to 10-N in parallel, each power conversion circuit 10-i may utilize electrical circuit elements with low voltage withstand or current tolerance.

Figure 2 shows the configuration of a parallel-type power converter 101 in which three power conversion circuits 10-1 to 10-3 are connected in parallel. Each of the power conversion circuits 10-1 to 10-3 includes a primary-side switching circuit 12 and a secondary-side switching circuit 14. The primary-side switching circuit 12 includes parallel-connected switching bridges X1 and Y1. Switching bridge X1 includes series-connected switching elements S1 and S2. Switching bridge Y1 includes series-connected switching elements S3 and S4. Switching elements S1 to S4 may be IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Two IGBTs being connected in series means that the emitter terminal of one IGBT is connected to the collector terminal of the other IGBT. Two MOSFETs connected in series means that the source terminal of one MOSFET is connected to the drain terminal of the other MOSFET.

The primary switching circuit 12 further includes a capacitor C1 connected in parallel to switching bridges X1 and Y1. The upper parallel connection terminals of switching bridge X1, switching bridge Y1, and capacitor C1 are connected to the positive input terminal Tp1, and the lower parallel connection terminals are connected to the negative input terminal Tg1.

Switching elements S1 and S2 alternately switch on and off. That is, when switching element S1 switches from off to on, switching element S2 switches from on to off, and when switching element S1 switches from on to off, switching element S2 switches from off to on. Similarly, switching elements S3 and S4 alternately switch on and off. Switching elements S1 and S3 switch with a predetermined phase difference, for example, a phase difference of 180°.

The primary switching circuit 12 further includes an inductor L1. One end of the inductor L1 is connected to the connection point of switching elements S1 and S2, and the other end is connected to the connection point of switching elements S3 and S4.

The secondary switching circuit 14 comprises a switching bridge X2, a switching bridge Y2, a capacitor C2, and an inductor L2. The circuit configuration of the secondary switching circuit 14 is the same as that of the primary switching circuit 12. Switching bridges X2, Y2, capacitor C2, and inductor L2 correspond to switching bridges X1, Y1, capacitor C1, and inductor L1, respectively. Inductors L1 and L2 are magnetically coupled to form the transformer 15. The upper parallel connection terminals of switching bridges X2, Y2, and capacitor C2 are connected to the positive output terminal Tp2, and the lower parallel connection terminals are connected to the negative output terminal Tg2.

The inductor L1 of the primary-side switching circuit 12 in each of the power conversion circuits 10-1 to 10-3 may constitute a first connector. The inductor L2 of the secondary-side switching circuit 14 in each of the power conversion circuits 10-1 to 10-3 may constitute a second connector that is detachably attached to the first connector. By bringing the first and second connectors close together or mechanically coupling them, a transformer 15 is formed in each of the power conversion circuits 10-1 to 10-3.

The power transmitted from the primary switching circuit 12 to the secondary switching circuit 14 is determined according to the phase difference between the switching of the primary switching circuit 12 and the switching of the secondary switching circuit 14. An ammeter 13 is connected to the parallel terminal TP2. The ammeter 13 measures the current flowing through the parallel terminal TP2 and outputs the measured value of the total current _Iout . Here, the total current _Iout is the sum of the currents _I1 to _IN flowing out from the positive output terminal Tp2 of the power conversion circuits 10-1 to 10-N.

Figure 2 shows a parallel-type power converter 101 in which three power conversion circuits 10-1 to 10-3 are connected in parallel. However, the parallel-type power converter 101 may also have a circuit configuration in which two or more power conversion circuits 10-i, each having the circuit configuration shown in Figure 2, are connected in parallel.

In this case as well, the inductors L1 of the primary-side switching circuits 12 provided in the multiple power conversion circuits 10-i may constitute a single first connector. The inductors L2 of the secondary-side switching circuits 14 provided in the multiple power conversion circuits 10-i may constitute a single second connector. The first and second connectors are brought close together or mechanically coupled to form a transformer 15 in each power conversion circuit 10-i.

Furthermore, the primary-side switching circuit 12 and the secondary-side switching circuit 14 may be configured in a way that determines the power transmitted from the primary side to the secondary side according to the difference between the switching phase of the primary-side switching circuit 12 and the switching phase of the secondary-side switching circuit 14.

Figure 3 shows a calculation model of a power conversion system 104 according to an embodiment of the present invention. The power conversion system 104 comprises a parallel power converter 100 and a power conversion circuit control device 102. The parallel power converter 100 comprises power conversion circuits 10-1 to 10-N and an adder 24. The power conversion circuits 10-1 to 10-N are controlled by a phase difference _δ1 to _δN , respectively, to output currents _I1 to _IN . Here, when we say that the power conversion circuit 10-i is controlled by a phase difference _δi , we mean that control is performed to bring the switching phase difference of the primary-side switching circuit 12 and the secondary-side switching circuit 14 close to or match the phase difference _δi . The adder 24 is a virtual component in the calculation model, and it sums the currents _I1 to _IN and _outputs a total current Iout.

The current I _i is expressed using the phase difference δ _i as follows:

However, k is the coupling coefficient of inductors L1 and L2, V _in is the DC voltage applied to the positive input terminal Tp1 and the negative input terminal Tg1, ω is the switching angular frequency, and L is the inductance of inductors L1 and L2. G is the gain, which represents the variables multiplied before δ in the central equation. Each variable in (Equation 1), except V _in , is a unique value for each power conversion circuit 10-i. Each variable except V _in may be denoted by the subscript "i", but the subscript "i" is omitted for simplicity of notation. The function f(δ) shown for each power conversion circuit 10-i in Figure 3 is expressed by (Equation 2) below.

Furthermore, if u = f(δ), the inverse function of f(δ), f ^-1 (u), is expressed by the following equation (Equation 3).

Here, sgn(u) is a sign function that is +1 when u is positive and -1 when u is negative.

The power conversion circuit control device 102 comprises a subtractor 16, a proportional-integral controller 18, a control value calculation unit 20, and switching control units 22-1 to 22-N. The power conversion circuit control device 102 may include a processor that implements the functions of each component (subtractor 16, proportional-integral controller 18, control value calculation unit 20, and switching control units 22-1 to 22-N) by executing a program.

The subtractor 16 obtains the measured value of the total current _Iout (hereinafter simply referred to as the total current _Iout ) from the ammeter 13 connected to the parallel terminal TP2 of the parallel power converter 100. The total current _Iout represents the current flowing out of the parallel power converter 100. The subtractor 16 also obtains the current command value _Iref , which is the target value for the total current _Iout . The current command value _Iref may be obtained by the power conversion circuit control device 102 from another control device.

The subtractor 16 and the proportional-integral controller 18 perform an operation variable determination process to determine the total operation variable v based on the difference between the total current _Iout and the current command value _Iref . That is, the subtractor 16 calculates the current error d by subtracting the total current _Iout from the current command value _Iref and outputs it to the proportional-integral controller 18. The proportional-integral controller 18 integrates the current error d over a predetermined time, and calculates the total operation variable v by multiplying the time integral value obtained and the value of the current error d by a predetermined coefficient and taking the sum, and outputs it to the control value calculation unit 20. The control value calculation unit 20 calculates the operation variable _ui for each power conversion circuit 10-i based on the total operation variable v and outputs it to the switching control unit 22-i. The switching control unit 22-i calculates the phase difference _δi based on (Equation 3) and controls the power conversion circuit 10-i with the phase difference _δi .

Furthermore, instead of the proportional-integral controller 18 that performs proportional-integral control (PI control), a controller that performs proportional control (P control) or a controller that performs proportional-integral-derivative control (PID control) may be used. A controller that performs P control calculates the total manipulated variable v by multiplying the current error d by a predetermined coefficient and outputs it to the control value calculation unit 20. A controller that performs PID control obtains a time integral value by integrating the current error d over a predetermined time, and also obtains a derivative value by performing a derivative operation on the current error d. A controller that performs PID control calculates the total manipulated variable v by multiplying the time integral value, the time derivative value, and the current error d by a predetermined coefficient and summing them, and outputs it to the control value calculation unit 20.

The control value calculation unit 20 repeatedly determines the manipulated variables _u1 to _uN at a predetermined feedback period so that the currents _I1 to _IN output by the power conversion circuits 10-1 to 10-N become uniform, by the process described below.

Figure 4 shows an example configuration of a power conversion system 106 equipped with three power conversion circuits 10-1 to 10-3. The control value calculation unit 20a includes a disturbance generation unit 30, superposition units 32-1 to 32-3, multipliers 34-1 to 34-3, error extraction processing unit 36, integration processing unit 38, two-phase to three-phase conversion unit 40, and function processing unit 42.

The disturbance generator 30 outputs three disturbance signals _Δ1 to _Δ3 , shown in (Equation 4), to the superimposing units 32-1 to 32-3, respectively. The disturbance signals _Δ1 to _Δ3 are sine or cosine functions with respect to time t and frequency f, with a phase difference of 120° (2π/3). The frequency f may be determined such that its reciprocal, the period 1/f, is longer than the feedback period for repeatedly determining the manipulated variables _u1 to _uN .

The superimposing units 32-1 to 32-3 individually add (superimpose) the disturbance signals _Δ1 to _Δ3 to the total manipulated variable v, and output the disturbance superimposed signals _v1 to _v3 to the multipliers 34-1 to 34-3, respectively.

The error extraction processing unit 36 performs an error extraction calculation on the total manipulated variable v as shown in (Equation 5) to obtain the gain error rates Gerror _{: a} and Gerror _{: b} , and outputs them to the integration processing unit 38. The gain error rates Gerror _{: a} and Gerror _{: b} correspond to the error components that have been included in the total manipulated variable v after feedback due to the superposition of disturbance signals Δ1 to Δ3 on the total manipulated variable v.

Note that _{Geror: a} in (Equation 5) is obtained by multiplying the total manipulated variable v by cos(2πft) and extracting the DC component using a low-pass filter (LPF). _{Geror: b} is obtained by multiplying the total manipulated variable v by sin(2πft) and extracting the DC component using a low-pass filter (LPF).

The integration processing unit 38 integrates the gain error rates _{Gerror: a} and _{Gerror: b} over a predetermined time, multiplies the resulting time integral values by a predetermined proportionality constant (gain) to obtain gain correction amounts K _a and K _b , and outputs them to the two-phase three-phase conversion unit 40. In Figure 4, the integration operation is represented in the s-domain of the Laplace transform. T is a constant determined by the proportionality constant. The two-phase three-phase conversion unit 40 performs the two-phase three-phase conversion shown in (Equation 6) on the gain correction amounts K _a and K _b to obtain the three-phase gain correction amounts K _c1 , K _c2 , and K _c3 , and outputs them to the function processing unit 42.

The function processing unit 42 calculates the manipulated variable correction coefficients _K1 to _K3 as exponential values for the gain correction amounts _Kc1 to _Kc3 according to (Equation 7).

When determining the manipulated variable correction coefficients _K1 to _K3 , other monotonically increasing functions (functions with positive derivatives) with gain correction amounts _Kc1 to _Kc3 as variables may be used instead of exponential functions. The function processing unit 42 outputs the manipulated variable correction coefficients _K1 to _K3 to the multipliers 34-1 to 34-3, respectively.

In this way, the integration processing unit 38, the two-phase to three-phase conversion unit 40, and the function processing unit 42 perform a correction coefficient determination process to determine a correction coefficient for each of the three superimposed disturbance signals based on the error component of the total manipulated variable v based on the disturbance signals _Δ1 to _Δ3 , thereby determining the manipulated variable correction coefficients _K1 to _K3 .

Multipliers 34-1 to 34-3 apply a correction process to the disturbance superimposed signals _v1 to _v3 using manipulated variable correction coefficients _K1 to _K3 to generate manipulated variables _u1 to _u3 . That is, multipliers 34-1 to 34-3 multiply the disturbance superimposed signals _v1 to _v3 by the manipulated variable correction coefficients _K1 to _K3 , respectively, to generate manipulated variables _u1 to _u3 , and output them to switching control units 22-1 to 22-3, respectively. Switching control units 22-1 to 22-3 each determine the phase difference _δ1 to _δ3 based on (Equation 3). Switching control units 22-1 to 22-3 each control the power conversion circuits 10-1 to 10-3 with the phase difference _δ1 to _δ3 .

The control value calculation unit 20a repeatedly performs the process of determining the manipulated variables _u1 to _u3 based on the total current _Iout and the current command value _Iref at a predetermined feedback cycle. The switching control units 22-1 to 22-3 control the power conversion circuits 10-1 to 10-3 based on the manipulated variables _u1 to _u3 that have been determined sequentially over time. As a result, the currents _I1 to _I3 output by the power conversion circuits 10-1 to 10-3 converge to the same value and become uniform.

As described above, when the inductor L1 of the primary-side switching circuit 12 in each of the power conversion circuits 10-1 to 10-3 constitutes the first connector, and the inductor L2 of the secondary-side switching circuit 14 in each of the power conversion circuits 10-1 to 10-3 constitutes the second connector, the first and second connectors may be misaligned during coupling. According to this embodiment, even if a coupling misalignment occurs between the first and second connectors, and variations occur in the coupling coefficients of the transformers 15 in each power conversion circuit, the current input to each power conversion circuit, or the current output from each power conversion circuit, is made uniform.

The principle by which the currents _I1 to _I3 output by power conversion circuits 10-1 to 10-3 converge to the same value will be explained. When the total current _Iout follows the current command value _Iref , (Equation 8) holds true.

Solving (Equation 8) for the total manipulated variable v yields (Equation 9).

Here, G _mean is the average of _{K1 G1} , _{K2 G2} , and _{K3 G3} , and the gain error rates _Geror1 , _Geror2 , and _Geror3 are defined as shown in (Equation 10).

By utilizing the fact that the sum of the disturbance signals _Δ1 , _Δ2 , and _Δ3, which are three-phase AC signals, is 0, we can eliminate _{K1 G1} , _{K2 G2} , and K3 _G3 from (Equation ₉ ) and (Equation 10) to obtain (Equation 11).

The second term on the right-hand side of equation (11) is zero when the gain error rates _Geror1 , _Geror2 , and _Geror3 are zero, and has a non-zero AC component otherwise. That is, the second term on the right-hand side contains information about the gain error rates _Geror1 , _Geror2 , and _Geror3 . From this, we can estimate Geror _:a and _Geror:b, which are associated with each gain error rate _Geror1 , _Geror2 , and _Geror3 as follows.

The relationship between the gain error ratios G _{err 1} , G _{err 2} , and G _{err 3} , and G _{err: a} and G _{err: b} will be explained. The gain error ratios G _{err 1} , G _{err 2} , and G _{err 3} are interpreted as a symmetric three-phase AC where their sum is 0. The gain error ratios G _{err 1} , G _{err 2} , and G _{err 3} are expressed by the two-phase to three-phase conversion equation and the gain error ratios G _{err: a} and G _{err: b} as shown in (Equation 12).

Similarly, disturbance signals _Δ1 to _Δ3 can be expressed by their orthogonal two-phase components _Δa and _Δb as shown in (Equation 13).

By substituting the left-hand sides of (Equation 12) and (Equation 13) into (Equation 11), we obtain (Equation 14).

Furthermore, from (Equation 4) and (Equation 13), (Equation 15) can be obtained.

By substituting (Equation 15) into (Equation 14), we obtain (Equation 16).

Equation (16) shows that the cosine and sinusoidal components included in the total manipulated variable v are the gain error rates Gerror _{: a} and _{Gerror: b,} respectively. From Equation (16), it can be understood that the gain error rates Gerror _{: a} and _{Gerror: b} can be obtained by Equation (5).

The gain error rates Gerror _:a and Gerror _:b correspond to the error components of the disturbance signals _Δa and _Δb , respectively, obtained by converting the disturbance signals _Δ1 to _Δ3 from three-phase to two-phase. These error components correspond to the errors that become included in the superimposed disturbance signal when the disturbance signals _Δ1 to _Δ3 are superimposed on the overall manipulated variable v. The gain error rates _Gerror:a and _Gerror:b as error components are extracted from the overall manipulated variable v by (Equation 5).

In the power conversion system 106 shown in Figure 4, the two-phase gain error rates Gerror _:a and _Gerror:b are extracted from the total manipulated variable v, and the two-phase gain error rates _Gerror:a and _Gerror:b are integrated over time to obtain the two-phase gain correction amounts K _a and K _b . Furthermore, the two-phase to three-phase conversion unit 40 converts the two-phase gain error rates _Gerror:a and _Gerror:b into three-phase gain correction amounts K _c1 to K _c3 , and the function processing unit 42 obtains three-phase manipulated variable correction coefficients K _c1 to K _c3 from each of the gain correction amounts K _c1 to K _c3 .

Thus, in the power conversion system 106, the three-phase gain error rates Gerr _:1 to _Gerr:3 are not directly determined. Instead, the two-phase gain error rates Gerr _:a to _Gerr:b are determined, and the three-phase manipulated variable correction coefficients _K1 to _K3 are determined from the two-phase gain error rates Gerr _:a and _Gerr:b . Since the calculation process for determining the three-phase manipulated variable correction coefficients _K1 to _K3 is performed for two phases, the calculation process is simplified.

The reason why the directly obtainable value can be the value for two phases is due to the constraint that the sum of the gain error rates Gerr _:1 to Gerr _:3 is zero. In other words, one of the gain error rates Gerr _:1 to Gerr _:3 is represented by the other two values, and the gain error rates Gerr _:1 to _Gerr:3 actually contain information for two values.

Next, the operational stability of the power conversion system 106 will be described. From (Equation 7), (Equation 10), and (Equation 12), the following (Equation 17) is obtained.

By Taylor expanding equation (17) around a point that satisfies _G1 exp(K _c1 ) = _G2 exp(K _c2 ) = _G3 exp(K _c3 ), equation (18) can be obtained.

By substituting (Equation 6) into (Equation 18), eliminating K _c1 to K _c3 , and rearranging the expression, we obtain (Equation 19).

The processing performed by the integration processing unit 38 results in (Equation 20), and by eliminating the gain correction amounts _Ka and _Kb from (Equation 19) and (Equation 20), (Equation 21) is obtained.

This equation shows that _{Geror: a} and _{Geror: b} converge exponentially to zero with respect to the time constant T. Therefore, it can be said that the operation of the power conversion system 106 is stable.

Figure 5 shows the configuration of a power conversion system 108 according to a second embodiment of the present invention. The power conversion system 108 is a generalization where the number of power conversion circuits 10-i to be controlled is N (where N is an integer of 2 or more).

The control value calculation unit 20b, which constitutes the power conversion system 108, includes a disturbance generation unit 31, superimposing units 32-1 to 32-N, multipliers 34-1 to 34-N, a manipulated variable adjustment unit 44, an error extraction processing unit 48, an integration processing unit 50, an N-1 phase N-phase conversion unit 52, and a function processing unit 54.

The disturbance generation unit 31 outputs N disturbance signals _Δ1 to _ΔN to the superimposing units 32-1 to 32-N, respectively. Here, the disturbance signals _Δ1 to _ΔN are expressed as (Equation 22) using N-1 orthogonal function sequences _φ1 to _φN-1 and an invertible matrix A.

The superimposing units 32-1 to 32-N individually add (superimpose) the disturbance signals _Δ1 to _ΔN to the total manipulated variable v, and output the disturbance superimposed signals _v1 to _vN to the multipliers 34-1 to 34-N, respectively.

The manipulated variable adjustment unit 44 includes a high-pass filter (HPF) and a coefficient multiplier 46. The high-pass filter (HPF) generates a total manipulated variable _wac by removing the DC component from the total manipulated variable v. The coefficient multiplier 46 multiplies the total manipulated variable _wac by a constant value of -1/Δ and outputs the total manipulated variable _vac = _-wac /Δ to the error extraction processing unit 48.

The error extraction processing unit 48 performs an error extraction calculation on the total manipulated variable _vac as shown in (Equation 23), calculates the gain error rate g _{error: 1} to g _{error: N-1} , and outputs it to the integration processing unit 50.

The gain error rates g _{error: 1} and g _{error: N-1} correspond to the error components of the orthogonal function sequences _φ1 to φN _-1 obtained by transforming the disturbance signals _Δ1 to _ΔN with the inverse matrix of the invertible matrix A. These error components correspond to the errors that have been included in the disturbance-superimposed signal due to the superposition of the disturbance signals _Δ1 to _ΔN on the overall manipulated variable v. The gain error rates g _{error: 1} to g _{error: N-1} as error components are extracted from the overall manipulated variable v by (Equation 23).

The integration processing unit 50 integrates each of the gain error rates g _error:1 to g _error:N-1 over a predetermined time, multiplies the resulting time integral value by a predetermined proportionality constant to obtain the gain correction amounts K _d1 to K _dN-1 , and outputs them to the N-1 phase N-phase conversion unit 52. In Figure 5, the integration operation is represented in the s-domain of the Laplace transform. The N-1 phase N-phase conversion unit 52 performs an N-1 phase N-phase conversion on the gain correction amounts K _d1 to K _dN-1 as shown in (Equation 24), obtains the N-phase gain correction amounts K _c1 to K _cN , and outputs them to the function processing unit 54.

Here, the sign "t" superscripted to the upper right of A indicates that it is the transpose of A, and the sign "-1" indicates that it is the inverse of A ^t .

The function processing unit 54 calculates the manipulated variable correction coefficients _K1 to _KN by substituting each of the gain correction amounts _Kc1 to _KcN into the independent variable x of the monotonically increasing function h(x). Here, for example, the exponential function exp(x) may be used for the monotonically increasing function h(x).

In this way, the integration processing unit 50, the N-1 phase N phase conversion unit 52, and the function processing unit 54 perform a correction coefficient determination process to determine a correction coefficient for each of the N disturbance superimposed signals based on the error component of the total manipulated variable v, thereby determining the manipulated variable correction coefficients _K1 to _KN .

Multipliers 34-1 to 34-N apply a correction process to the disturbance superimposed signals _v1 to _vN using manipulated variable correction coefficients _K1 to _KN to generate manipulated variables _u1 to _uN . That is, multipliers 34-1 to 34-N multiply the disturbance superimposed signals _v1 to _vN by the manipulated variable correction coefficients _K1 to _KN to generate manipulated variables _u1 to _uN , which are then output to switching control units 22-1 to 22-N. Switching control units 22-1 to 22-N determine the phase difference _δ1 to _δN based on (Equation 3). Switching control units 22-1 to 22-N control the power conversion circuits 10-1 to 10-N with the phase difference _δ1 to _δN .

The control value calculation unit 20b repeatedly performs the process of determining the manipulated variables _u1 to _uN based on the total current _Iout and the current command value _Iref , at a predetermined feedback cycle. The switching control units 22-1 to 22-N control the power conversion circuits 10-1 to 10-N based on the manipulated variables _u1 to _uN that have been determined sequentially over time. As a result, the currents _I1 to _IN output by the power conversion circuits 10-1 to 10-N converge to the same value and become uniform.

The ammeter used in this control only needs to measure the total current I _out . Therefore, the number of ammeters used in the power conversion system 108 is reduced, and the configuration is simplified.

Furthermore, as described above, if the inductor L1 of the primary-side switching circuit 12 in each of the power conversion circuits 10-1 to 10-N constitutes a single first connector, and the inductor L2 of the secondary-side switching circuit 14 in each of the power conversion circuits 10-1 to 10-N constitutes a single second connector, the first and second connectors may be misaligned during coupling. According to this embodiment, even if misalignment occurs between the first and second connectors, and variations occur in the coupling coefficients of the transformers 15 in each power conversion circuit, the current input to each power conversion circuit, or the current output from each power conversion circuit, is made uniform.

The principle by which the currents _I1 to _IN output by power conversion circuits 10-1 to 10-N converge to the same value is explained. When the total current _Iout follows the current command value _Iref , equation (25) holds true as a generalization of equation (9).

By using disturbance signals _Δ1 to _ΔN whose sum is zero, the third term on the right-hand side of (Equation 25) becomes zero. Also, when a high-pass filter is applied to the total manipulated variable v, the first term on the right-hand side of (Equation 25) becomes zero. Under these conditions, (Equation 26) is obtained as the expression for the total manipulated variable _vac .

One method for determining the gain error rates _{Gerror: 1} to _{Gerror: N} from the total manipulated variable v _ac is to represent the disturbance signal _Δ1 to _ΔN as a sequence of orthogonal functions, or as a sequence of functions to which a constant is added to each function forming the orthogonal sequence. In this case, the gain error rate _{Gerror: i} (i = 1 to N) is obtained as a component of the disturbance signal _Δi included in the total manipulated variable v _ac .

The disturbance signal _Δi can be expressed using a regular matrix A and an orthogonal function sequence _φ1 to φN _-1 as shown in (Equation 27).

By substituting (Equation 27) into (Equation 26), we obtain (Equation 28).

Due to the properties of orthogonal function sequences, each component g _error:1 to g _error:N-1 of the orthogonal function sequence _φ1 to _φN-1 included in the total manipulated variable _vac can be expressed as follows (Equation 29).

Since the sum of the gain error rates is 0, by setting the Nth column of the invertible matrix A to all equal values, equation (30) holds.

By combining (Equation 29) and (Equation 30), we obtain (Equation 31).

By solving (Equation 31) for gain error rates Gerror _{: 1} to Gerror _{: N} , we obtain (Equation 32), which represents the gain error rates Gerror _{: 1} to _{Gerror: N.}

Equation 32 shows that the gain error ratios Gerror _{: 1} to Gerror _{: N} can be expressed using the gain error ratios _{gerror: 1} to _{gerror: N-1} and the invertible matrix A. As is clear from Equations 29 and 32, the gain error ratios _{Gerror: 1} to _{Gerror: N} can be expressed based on the components of N-1 orthogonal function sequences extracted from the total manipulated variable _vac .

In the power conversion system 108 shown in Figure 5, the gain error rates g _err:1 to g _err:N-1 of the N-1 phase are extracted from the total manipulated variable v _ac , and the gain error rates g _err:1 to g _err:N-1 of the N-1 phase are integrated over time to obtain the gain correction amounts K _d1 to K _dN-1 of the N-1 phase. Furthermore, the N-1 phase N-phase conversion unit 52 converts the gain error rates g _err:1 to g _err:N-1 of the N-1 phase into N-phase gain correction amounts K _c1 to K _cN , and the function processing unit 54 obtains the N-phase manipulated variable correction coefficients K ₁ to K _N from each of the gain correction amounts K _c1 to K _cN .

Thus, in the power conversion system 108, the gain error rates G _err:1 to G _err:N of the N phase are not directly determined. Instead, the gain error rates g _err:1 to g _err:N-1 of the N-1 phase are determined, and the N phase control variable correction coefficients K ₁ to K _N are determined from the N-1 phase gain error rates g _err:1 to g _err:N-1 . Since the calculation process for determining the N phase control variable correction coefficients K ₁ to K _N is performed for the N-1 phase, the calculation process is simplified.

The reason why the directly obtainable value can be the value for N-1 phases is due to the constraint that the sum of the gain error ratios _Gerror:1 to _Gerror:N is zero. In other words, one of the gain error ratios Gerror _:1 to Gerror _:N is represented by the other N-1 values, and the gain error ratios _Gerror:1 to Gerror _:N actually contain information for N-1 values.

The orthogonal function sequences _φ1 to φN _-1 may be multiple mutually orthogonal trigonometric functions. When there are three power conversion circuits, the orthogonal functions _φ1 and _φ2 and the invertible matrix A can be shown, for example, by (equation 33) as follows.

When there are two power conversion circuits, the function _φ1 and the invertible matrix A can be shown, for example, by (equation 34) as follows.

In this case, the disturbance signal is represented by (Equation 35), and the gain error rates Geror _:1 and Geror _:2 are represented by (Equation 36).

When there are four power conversion circuits, the orthogonal function sequences _φ1 to _φ3 and the invertible matrix A can be represented, for example, by (Equation 37). Here, when there are four or more power conversion circuits, the orthogonal function sequences include functions with frequencies of twice the frequency or higher.

If there are five power conversion circuits, the orthogonal function sequences _φ1 to _φ4 and the invertible matrix A can be represented, for example, by (Equation 38).

Figure 6 shows the configuration of a power conversion system 110 according to a third embodiment of the present invention. The control value calculation unit 20c of the power conversion system 110 includes a disturbance generation unit 33, superimposing units 32-1 to 32-4, multipliers 34-1 to 34-3, a manipulated variable adjustment unit 60, an error extraction processing unit 64, an integration processing unit 68, and a function processing unit 70.

The disturbance generation unit 33 includes low-pass filters LPF1 to LPF4 and coefficient multipliers 35-1 to 35-4. The disturbance generation unit 33 acquires disturbance function signals _φ1 to _φ4 , reduces the high-frequency components of each of the disturbance function signals _φ1 to _φ4 using the low-pass filters LPF1 to LPF4, and outputs them to the coefficient multipliers 35-1 to 35-4, respectively. The low-pass filters LPF1 to LPF4 reduce the slew rate of the disturbance function signals _φ1 to _φ4 . By reducing the slew rate of the disturbance function signals _φ1 to _φ4 , the tracking ability to the disturbance function signals _φ1 to _φ4 is improved when the manipulated variables _u1 to _uN are repeatedly determined. Each coefficient multiplier 35-1 to 35-4 generates disturbance signals _Δ1 to _Δ4 by multiplying the disturbance function signals _φ1 to _φ4 , which have been filtered by a low-pass filter (LPF), by an adjustment coefficient Δ, and outputs them to the superimposing units 32-1 to 32-4, respectively.

The disturbance function signals _φ1 to _φ4 may be signals represented by the disturbance function shown in (Equation 39). However, in this embodiment, N=4 in (Equation 39). The disturbance function signal _φk represented by (Equation 39) is an orthogonal signal.

For the disturbance function signals _φ1 to _φ4 shown in (Equation 39), there is a period of time when the value of one disturbance function signal is active and the values of the other disturbance function signals are inactive. Here, the active value is √FN or -√FN, and the inactive value is 0. The disturbance function signals _φ1 to _φ4 become active one by one as time progresses. The period 1/f for the state in which _φ1 to _φN sequentially take on active values may be determined to be longer than the feedback period for which the manipulated variables _u1 to _uN are repeatedly obtained.

The disturbance function signals _φ1 to _φ4 may be signals represented by the disturbance function shown in (Equation 40). However, in this embodiment, N = 4 in (Equation 40).

For the disturbance function signals _φ1 to _φ4 shown in (Equation 40), there is a time period in which the value of one disturbance function signal becomes an active value, and the values of the other disturbance function signals become inactive values. Here, the active value is 1 and the inactive value is 0. The disturbance function signals _φ1 to _φ4 become active one by one in sequence as time progresses. The period 1/f in which the state in which _φ1 to _φN sequentially take on active values is completed may be determined to be longer than the feedback period in which the manipulated variables _u1 to _uN are repeatedly obtained.

The superimposing units 32-1 to 32-4 each individually add the disturbance signals _Δ1 to _Δ4 to the total manipulated variable v, and output the disturbance superimposed signals _v1 to _v4 to the multipliers 34-1 to 34-4, respectively.

As described above, for the disturbance function signals _φ1 to _φ4 , there is a time period in which the value of one disturbance function signal becomes active, while the values of the other disturbance function signals become inactive. Then, the disturbance function signals _φ1 to _φ4 become active one by one as time progresses. Therefore, the superimposed disturbance signals _v1 to _v4 have values corresponding to the disturbance function signals _φ1 to _φ4 in a time-division manner as time progresses.

The manipulated variable adjustment unit 60 includes a high-pass filter (HPF) and a coefficient multiplier 62. The high-pass filter (HPF) generates a total manipulated variable w _ac by removing the DC component from the total manipulated variable v. The coefficient multiplier 62 multiplies the total manipulated variable v _ac by -4/Δ and outputs the total manipulated variable v _ac = -4v _ac /Δ to the error extraction processing unit 64.

The error extraction processing unit 64 includes multipliers 1-1 to 1-4, an average calculation unit 66, and subtractors 2-1 to 2-4. Multipliers 1-1 to 1-4 individually multiply the total manipulated variable w _ac output from the manipulated variable adjustment unit 60 by the disturbance function signals _φ1 to _φ4 , which have been subjected to a low-pass filter, to obtain the gain error rates G _err:1 to G _err:4 as multiplied values. The average calculation unit 66 calculates the average value V _mean of _φ1 v _ac to _φ4 v _ac . Subtractors 2-1 to 2-4 calculate the gain error rates Ge1 to _Ge4 by subtracting V _mean from each of the gain error rates G _{err:1 to} G _err:4 , and output them to the integration processing unit 68.

As described above, for the disturbance function signals _φ1 to _φ4 , there is a time period in which the value of one disturbance function signal is active and the values of the other disturbance function signals are inactive. Then, the disturbance function signals _φ1 to _φ4 become active one by one as time progresses. Furthermore, the gain error ratios Gerror _:1 to _Gerror:4 are values obtained by individually multiplying the total manipulated variable _vac by the disturbance function signals _φ1 to _φ4 , which have been subjected to low-pass filtering. Therefore, the instantaneous value of the gain error ratios Gerror _:1 to Gerror _:4 is the value extracted from the total manipulated variable _vac for any component of the disturbance function signals _φ1 to _φ4 . In other words, the gain error ratios Gerror _:1 to Gerror _:4 have values corresponding to the disturbance function signals _φ1 to _φ4 one by one as time progresses, in a time-division manner.

The gain error rates G _err:1 to G _err:4 correspond to the error components of the disturbance signals _Δ1 to _Δ4 , respectively. These error components correspond to the errors that become included in the superimposed disturbance signal when the disturbance signals _Δ1 to _Δ4 are superimposed on the overall manipulated variable v. The gain error rates G _e1 to G _e4 as error components are extracted from the overall manipulated variable v _ac by the error extraction processing unit 64.

Furthermore, the reason why subtractors 2-1 to 2-4 subtract V _mean from the gain error rates G _{err: 1} to G _{err: 4} is to make the sum of the gain error rates G _e1 to G _e4 equal to 0.

The integration processing unit 68 integrates each of the gain error rates G _e1 to G _e4 over a predetermined time, multiplies the resulting time integral value by a predetermined coefficient to obtain the gain correction amounts K _c1 to K _c4 , and outputs them to the function processing unit 70. The function processing unit 70 obtains the manipulated variable correction coefficients K ₁ to K ₄ as exponential values for the gain correction amounts K _c1 to K _c4 , and outputs them to the multipliers 34-1 to 34-4, respectively.

In this way, the integration processing unit 68 and the function processing unit 70 perform a correction coefficient determination process to determine the correction coefficient for each of the four disturbance superimposed signals based on the error component of the overall manipulated variable v, thereby determining the manipulated variable correction coefficients _K1 to _K4 .

Multipliers 34-1 to 34-4 apply a correction process to the disturbance superimposed signals _v1 to _v4 using manipulated variable correction coefficients _K1 to _K4 to generate manipulated variables _u1 to _u4 . That is, multipliers 34-1 to 34-4 multiply the disturbance superimposed signals _v1 to _v4 by the manipulated variable correction coefficients _K1 to _K4 to generate manipulated variables _u1 to _u4 , and output them to switching control units 22-1 to 22-4, respectively. Switching control units 22-1 to 22-4 determine the phase differences _δ1 to _δ4 , respectively, based on (Equation 3). Switching control units 22-1 to 22-4 control the power conversion circuits 10-1 to 10-4, respectively, with the phase differences δ1 to δ4.

The control value calculation unit 20c repeatedly performs the process of determining the manipulated variables _u1 to _u4 based on the total current _Iout and the current command value _Iref at a predetermined feedback cycle. The switching control units 22-1 to 22-4 control the power conversion circuits 10-1 to 10-4 based on the manipulated variables _u1 to _u4 that have been determined sequentially over time. As a result, the currents _I1 to _I4 output by the power conversion circuits 10-1 to 10-4 converge to the same value and become uniform.

The ammeter used in this control only needs to measure the total current I _out . Therefore, the number of ammeters used in the power conversion system 110 is reduced, and the configuration is simplified.

Figures 7 and 8 show the results of a simulation performed on the power conversion system 110 according to the third embodiment. In each figure, the horizontal axis represents time and the vertical axis represents current. The gains of the power conversion circuits 10-1 to 10-4 defined by (Equation 1) are _G1 to _G4 , respectively, and with gain _G2 as the reference, gain _G1 is set to +10%, gain _G3 to -10%, and gain _G4 to -20%. As shown in Figure 7, the currents _I1 to _I4 flowing out from the positive output terminal Tp2 of the power conversion circuits 10-1 to 10-4 converge toward the same value over time.

Figure 8 shows the currents _I1 to _I4 after they have converged, and the total current _Iout . The vertical axis in Figure 8 is stretched compared to the vertical axis in Figure _7. The ripple rate of currents _{I1 to I4} is 1.4%, and because the ripple components contained in currents _I1 to _I4 suppress each other, the ripple rate of the total current _Iout is suppressed to less than 1.4%.

The above describes an embodiment in which the current flowing through the parallel terminal TP2 of the parallel power conversion circuit is defined as the total current _Iout , and the parallel power conversion device is controlled based on the measured value of the total current _Iout . In addition to this control, the current flowing through the parallel terminal TG2, the current flowing through the parallel terminal TP1, or the current flowing through the parallel terminal TG2 is defined as the total current _Iout , and similar control may be performed on the parallel power conversion device based on the measured value of the total current _Iout . In this case, an ammeter 13 is connected to the terminal through which the current defined as the total current _Iout flows.

[Structure of the present invention]
Configuration 1:
A manipulated variable determination process that determines the overall manipulated variable based on the difference between the measured value of the current flowing at the parallel connection terminals of multiple power conversion circuits connected in parallel and the current command value,
A superposition process is performed to generate multiple superimposed disturbance signals by individually superimposing multiple different disturbance signals onto the aforementioned total manipulated quantity.
An error extraction process that extracts one or more components corresponding to multiple different disturbance signals from the total manipulated variable and determines one or more error components corresponding to multiple different disturbance signals,
A correction coefficient determination process that determines a correction coefficient for each of the multiple disturbance superimposed signals based on the error component,
A control variable determination process is performed to determine the control variable for each of the multiple disturbance superimposed signals by applying a correction process using the correction coefficient, and determining the control variable for each of the multiple power conversion circuits.
A power conversion circuit control device characterized by performing the following:
Configuration 2:
The power conversion circuit control device described in Configuration 1,
A power conversion circuit control device characterized in that the multiple disturbance signals are represented by an orthogonal function sequence.
Configuration 3:
The power conversion circuit control device described in configuration 2,
A power conversion circuit control device characterized in that the multiple disturbance signals are represented by a plurality of mutually orthogonal trigonometric functions.
Configuration 4
The power conversion circuit control device described in Configuration 1,
The power conversion circuit control device is characterized in that the multiple disturbance signals are represented by multiple disturbance functions, where there is a time period in which the value of one function becomes an active value and the values of the other functions become inactive values, and each of the multiple disturbance functions becomes an active value one by one as time progresses.
Configuration 5:
The power conversion circuit control device described in configuration 4,
Multiple disturbance signals are,
A power conversion circuit control device characterized by being a plurality of signals obtained by applying a low-pass filter to each of the plurality of signals represented by the plurality of disturbance functions.
Configuration 6:
A power conversion circuit control device according to configuration 4 or configuration 5,
The error extraction process described above is:
A power conversion circuit control device characterized by including a process of extracting each error component from the total manipulated variable by multiplying each of the disturbance signals by a value based on the total manipulated variable.
Configuration 7:
A power conversion circuit control device according to configuration 4 or configuration 5,
The error extraction process described above is:
A power conversion circuit control device characterized by calculating the average value of a plurality of multiplied values obtained by multiplying a value based on the total manipulated variable by a plurality of disturbance signals, and then calculating each error component by subtracting the average value from each of the plurality of multiplied values.
Configuration 8:
A power conversion circuit control device according to any one of configurations 1 to 7,
The correction coefficient determination process is as follows:
A power conversion circuit control device characterized by including a process of performing a time integral on each of the error components and determining each of the correction coefficients based on each monotonically increasing function whose independent variable is a value based on the time integral value of each of the error components.
Composition 9:
A power conversion circuit control device according to any one of configurations 1 to 8,
The system includes a switching control unit that controls each of the multiple power conversion circuits based on the operation amount for each of the power conversion circuits,
Each of the aforementioned power conversion circuits is:
It comprises a primary-side switching circuit and a secondary-side switching circuit coupled by a transformer,
The switching control unit,
A power conversion circuit control device characterized by controlling the difference between the switching phase of the primary switching circuit and the phase of the secondary switching circuit based on the manipulated amount.

10-1 to 10-N Power conversion circuit, 12 Primary switching circuit, 13 Ammeter, 14 Secondary switching circuit, 15 Transformer, 2-1 to 2-4, 16 Subtractor, 18 Proportional-integral controller, 20, 20a, 20b, 20c, 43 Control value calculation unit, 22-1 to 22-N Switching control unit, 24 Adder/totaler, 30, 31, 33 Disturbance generation unit, 32-1 to 32-N Superimulator, 1-1 to 1-4, 34-1 to 34-N Multiplier, 35-1 to 35-4, 46, 62 Coefficient multiplier, 36, 48, 64 Error extraction processing unit, 38, 50, 68 Integral processing unit, 40 Two-phase to three-phase conversion unit, 42, 54, 70 Function processing unit, 44, 60 Manipulated variable adjustment unit, 50 N-1 phase N phase conversion unit, 66 average value calculation unit, 100 parallel type power converter, 102 power conversion circuit control device, 104, 106, 108 power conversion system.

Claims (9)

A manipulated variable determination process that determines the overall manipulated variable based on the difference between the measured value of the current flowing at the parallel connection terminals of multiple power conversion circuits connected in parallel and the current command value,
A superposition process is performed to generate multiple superimposed disturbance signals by individually superimposing multiple different disturbance signals onto the aforementioned total manipulated quantity.
An error extraction process that extracts one or more components corresponding to multiple different disturbance signals from the total manipulated variable and determines one or more error components corresponding to multiple different disturbance signals,
A correction coefficient determination process that determines a correction coefficient for each of the multiple disturbance superimposed signals based on the error component,
A control variable determination process is performed to determine the control variable for each of the multiple disturbance superimposed signals by applying a correction process using the correction coefficient, and determining the control variable for each of the multiple power conversion circuits.
A power conversion circuit control device characterized by performing the following: A power conversion circuit control device according to claim 1,
A power conversion circuit control device characterized in that the multiple disturbance signals are represented by an orthogonal function sequence. A power conversion circuit control device according to claim 2,
A power conversion circuit control device characterized in that the multiple disturbance signals are represented by a plurality of mutually orthogonal trigonometric functions. A power conversion circuit control device according to claim 1,
The power conversion circuit control device is characterized in that the multiple disturbance signals are represented by multiple disturbance functions, where there is a time period in which the value of one function becomes an active value and the values of the other functions become inactive values, and each of the multiple disturbance functions becomes an active value one by one as time progresses. A power conversion circuit control device according to claim 4,
Multiple disturbance signals are,
A power conversion circuit control device characterized by having multiple signals obtained by applying a low-pass filter to each of the multiple signals represented by the multiple disturbance functions. A power conversion circuit control device according to claim 4 or claim 5,
The error extraction process described above is:
A power conversion circuit control device characterized by including a process of extracting each error component from the total manipulated variable by multiplying each of the disturbance signals by a value based on the total manipulated variable. A power conversion circuit control device according to claim 4 or claim 5,
The error extraction process described above is:
A power conversion circuit control device characterized by calculating the average value of a plurality of multiplied values obtained by multiplying a value based on the total manipulated variable by a plurality of disturbance signals, and then calculating each error component by subtracting the average value from each of the plurality of multiplied values. A power conversion circuit control device according to claim 1,
The correction coefficient determination process is as follows:
A power conversion circuit control device characterized by including a process of performing a time integral on each of the error components and determining each of the correction coefficients based on each monotonically increasing function whose independent variable is a value based on the time integral value of each of the error components. A power conversion circuit control device according to claim 1,
The system includes a switching control unit that controls each of the multiple power conversion circuits based on the operation amount for each of the power conversion circuits,
Each of the aforementioned power conversion circuits is:
It comprises a primary-side switching circuit and a secondary-side switching circuit coupled by a transformer,
The switching control unit,
A power conversion circuit control device characterized by controlling the difference between the switching phase of the primary switching circuit and the phase of the secondary switching circuit based on the manipulated amount.