JP7844296B2 - controller - Google Patents

Description

This embodiment relates to a controller.

Controllers that control industrial machinery and other equipment may independently and asynchronously perform data input/output processing from controlled industrial equipment, data task processing, and communication processing to output data to other controllers. Furthermore, such controllers may use time-controlled transmission queues to maintain real-time communication even when data with different priorities are mixed together.

However, when task processing and communication processing are asynchronous, strictly managing the transmission queue for transmission processing can lead to mismatches between the cycles of communication processing and task processing. This can result in data that should be transmitted being sent in the next cycle of communication processing. In this case, data transmission processing may be delayed, potentially compromising its real-time capabilities.

Japanese Patent Publication No. 2019-121822 Patent No. 5184597 Patent No. 6768625

This controller provides real-time data communication processing even when data task processing and transmission processing are asynchronous.

The controller according to this embodiment is a controller that controls a controlled object. The first interface controller is connected to the controlled object for communication and periodically receives data from the controlled object. The first storage unit stores the data. The arithmetic unit processes the input data, performs calculations, and transfers the results to the first storage unit. The second interface controller is connected to other controllers for communication and performs transmission processing to periodically send data to other controllers. If the start time of the transmission processing overlaps with the data input processing period, the arithmetic unit delays the start time of the transmission processing to a later time than the input processing period.

A block diagram showing an example configuration of an industrial controller system according to the first embodiment. A block diagram showing an example of the internal configuration of a controller. A conceptual diagram showing an example of the configuration and functions of a LAN controller. A timing diagram showing an example of the operation of the controller's input/output processing, calculation processing, and transmission processing. A timing diagram showing an example of the operation of the controller's input/output processing, calculation processing, and transmission processing. A flowchart illustrating an example of how a controller processes tasks. A flowchart illustrating an example of the controller's transmission process. A table showing the task processing time of the controller according to the second embodiment. A flowchart showing an example of controller operation according to the second embodiment.

The embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be identical to those of actual objects. In the specification and drawings, elements similar to those described above are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

(First Embodiment)
Figure 1 is a block diagram showing an example configuration of an industrial controller system (hereinafter simply referred to as "the system") 1 according to the first embodiment. The system 1 includes controllers 11 to 15 and is provided for controlling one or more industrial machines located outside the system 1.

Controllers 11-15 are connected to each other via a network 20, such as a LAN (Local Area Network), enabling communication between them. The network 20 may be wired or wireless. Each controller 11-15 is assigned a unique identifier that does not overlap with other controllers. Controllers 11-15 have internal timer functions, and their time is synchronized with high precision using a protocol such as PTP (Precision Time Protocol) as defined in IEEE 1588.

Controllers 11 to 15 may each have the same configuration. Furthermore, the number of controllers is not limited to five; it may be four or fewer, or six or more.

Figure 2 is a block diagram showing an example of the internal configuration of controller 11. Since the configurations of controllers 12-15 are the same as those of controller 11, only the configuration of controller 11 will be described here, and the configurations of controllers 12-15 will be omitted.

The controller 11 comprises a CPU 30, an I/O bus controller 40, a memory 50, a common memory 60, an interface bridge 70, and a LAN controller 80. The controller 11 is communicated to the industrial machine 100 via an I/O device 90.

As an example of a calculation unit, the CPU 30 processes input data from the industrial machine 100 received from the I/O bus controller 40. The input data may include, for example, information from various sensors installed on the industrial machine 100, more specifically, pressure information, temperature information, motor position information, etc. The CPU 30 performs input processing, receiving such input data from the I/O bus controller 40 and transferring it to the memory 50 and/or common memory 60. The CPU 30 also processes the input data, generates control commands accordingly, and outputs these control commands to the industrial machine 100 via the I/O bus controller 40. The control commands are transmitted to the industrial machine 100 via the I/O device 90 and used to control the industrial machine 100. For example, if the input data is temperature information, the control command is used to adjust the heater output to control the temperature of the industrial machine 100. Furthermore, the CPU 30 works in cooperation with the memory 50 to perform calculations on the input data and stores the resulting calculation data in the common memory 60.

The operating system (OS) installed in the CPU 30 is a real-time OS. The CPU 30 schedules software processing in real time, including input/output processing of input data and control commands, calculation processing of input data, and transmission of calculation result data. In input processing, the CPU 30 periodically processes input data and transfers the input data and calculation result data to the common memory 60.

An I/O bus controller 40, as an example of a first interface controller, is connected to an external industrial machine 100 via an I/O device 90 for communication. The I/O bus controller 40 controls the I/O device 90 to receive input data from the industrial machine 100 and outputs control commands from the CPU 30 to the industrial machine 100. The I/O bus controller 40 performs data input/output processing with the industrial machine 100 at a fixed interval (for example, approximately 200 μs). In this way, the I/O bus controller 40 controls the data input/output processing between the industrial machine 100 and the controller 11.

The second memory unit, memory 50, stores the program executed by the CPU 30, as well as various parameters used for processing input data. Memory 50 also temporarily stores input data received during input/output processing, or the calculation results obtained by processing the input data.

The common memory 60, acting as the first storage unit, manages a contiguous storage area divided into multiple blocks. Each block is pre-configured and associated with a controller identifier (hereinafter also referred to as the node number) used for transmission processing. Furthermore, each block is assigned a transmission priority of high speed, medium speed, and low speed. Data in high-speed blocks has higher priority than data in medium-speed or low-speed blocks. Data in medium-speed blocks has higher priority than data in low-speed blocks. Data in high-priority blocks is processed for transmission preferentially.

The common memory 60 stores input data and calculation result data received during the input/output processing of controller 11, and also stores data from other controllers 12-15 through an equalization process. For example, the data in each block of the common memory 60 is transmitted to other controllers 12-15 in the network 20 via multicast transmission, and the contents of the common memory 60 are equalized among the controllers. The equalization process is a process in which controllers 11-15 transmit their own data received from the industrial machine 100 during input/output processing to other controllers via the network 20, and also receive data from other controllers and store it in the common memory 60, thereby equalizing the data stored in the common memory 60. As a result, the data in the common memory 60 of controllers 11-15 is stored equally in each common memory 60, resulting in an equalized state.

The interface bridge 70 may be, for example, a PCI Express® bridge. The interface bridge 70 performs data protocol conversion, enabling data transmission from the LAN controller 80 to the network 20.

As an example of a second interface controller, the LAN controller 80 is connected to the other controllers 12-15 via the network 20 for communication. The LAN controller 80 periodically broadcasts data to the other controllers 12-15. When processing data to be transmitted (hereinafter also referred to as transmission data), such as data stored in the common memory 60, the LAN controller 80 performs gate control of the transmission queue. Each transmission data item is assigned priority information, and these are stored in the transmission queue according to their priority. The LAN controller 80 implements a function to gate each transmission queue so that one transmission data item is selected. As a result, the LAN controller 80 processes the transmission data stored in the transmission queue one block at a time in order of priority. This gate control function conforms to the IEEE 802.1Qbv standard, and the gate control settings are implemented as software.

Next, we will explain input processing, output processing, arithmetic processing, and transmission processing.

The input process involves receiving data from the industrial machine 100 into the controller 11 via the I/O device 90 and the I/O bus controller 40. The input process also includes inputting data from other controllers 12-15 from the equalized common memory 60 into memory 50. The output process involves outputting control commands, etc., to the industrial machine 100 via the I/O bus controller 40 and the I/O device 90. The output process also includes storing data from memory 50 into common memory 60. Hereinafter, the input and output processes will be collectively referred to as input/output processing.

The arithmetic processing is the process by which the CPU 30 performs calculations on data input to memory 50 and stores the calculation results in memory 50. The arithmetic processing is executed according to data priority, such as high-speed, medium-speed, and low-speed. Input processing, output processing, and arithmetic processing are initiated and executed periodically. Hereinafter, input/output processing and arithmetic processing will be collectively referred to as task processing.

The transmission process involves the CPU 30 requesting the LAN controller 80 to transmit data from the common memory 60. The LAN controller 80 then transmits the data stored in the transmission queue to other controllers 12-15 via the network 20. At this time, the LAN controller 80 stores the data in the transmission queue according to priority and broadcasts that data to the other controllers 12-15 according to priority. The transmission process is initiated and executed periodically, but it is performed asynchronously with the input/output and arithmetic processing described above.

Figure 3 is a conceptual diagram showing an example of the configuration and function of the LAN controller 80. The LAN controller 80 receives transmission data from the common memory 60 in blocks and stores it in one of the transmission queues Q1 to Q3 according to priority. The LAN controller 80 gates each transmission queue so that transmission data is selected block by block. At this time, to prevent overlapping transmissions from transmission queues Q1 to Q3, the gates of each transmission queue Q1 to Q3 are opened at different times without overlap. For example, the gate opening time for transmission queue Q1 is t1 to t2, the gate opening time for transmission queue Q2 is t3 to t4, and the gate opening time for transmission queue Q3 is t5 to t6. This allows the LAN controller 80 to transmit the transmission data one block at a time via the network 20 to other controllers 12 to 15 in order of priority, without overlapping. Note that the priority is not limited to three; it may be two or fewer, or four or more.

Furthermore, the control of the gate opening time for the transmission queue can be switched between enabled and disabled. When the gate opening time is disabled, the LAN controller 80 transmits in FIFO (First In First Out) order from transmission queues Q1 to Q4 in descending order of priority, without adhering to the opening time setting. When the gate opening time is enabled, the LAN controller 80 transmits according to the gate opening time setting. In this embodiment, the gate opening time is set to enabled.

Next, we will explain the operation of controller 11.

Figures 4 and 5 are timing diagrams showing examples of the operation of the input/output processing, arithmetic processing, and transmission processing of the controller 11. Figure 6 is a flowchart showing an example of the operation of the task processing of the controller 11. Figure 7 is a flowchart showing an example of the operation of the transmission processing of the controller 11. Since the transmission processing is executed asynchronously from the task processing, it is shown separately from the task processing in Figures 4 and 5.

Input/output processing refers to both input and output processing. Input/output processing and arithmetic processing are synchronous and executed repeatedly at a fixed period B. Transmission processing is executed repeatedly at a fixed period F, but it is executed asynchronously from input/output processing and arithmetic processing.

Furthermore, the execution period D for input processing, the first cycle B between one input process and the next, the execution period H for transmission processing, and the second cycle F between one transmission process and the next are predetermined and stored in memory 50.

First, as shown in Figure 4, input/output processing is performed at t11-t12 (S10 in Figure 6). That is, data from the industrial machine 100 is input into the controller 11 from the I/O device 90 and the I/O bus controller 40 and held in memory 50. The data is then transferred from memory 50 to common memory 60. At this time, data stored in common memory 60 is also input into memory 50 as needed for calculation processing. Furthermore, if there are control commands to be sent, these control commands are output from the I/O bus controller 40 and the I/O device 90 to the industrial machine 100.

Furthermore, at time t11, the CPU 30 uses a timer function to obtain the start time (first start time) t11 at that point in time and stores it in memory 50 (S10). Based on the start time t11 and the first cycle B, the CPU 30 calculates the start time (second start time) t17 of the next scheduled input/output process and stores it in memory 50 (S20 in Figure 6). For example, the CPU 30 can calculate the start time t17 by adding the first cycle B to the start time t11. The calculated start time t17 is a future scheduled time calculated by the process, and is also the start time of the next task process. The start time t17 of the next task process is stored in memory 50 in association with the data priority.

At time t12, once input/output processing is complete, the CPU 30 starts arithmetic processing using the input data, etc. (S30). In the arithmetic processing, the CPU 30 performs predetermined calculations using the input data, etc., and obtains calculation result data. The calculation result data is stored in memory 50 and common memory 60 (S32).

If there is a next task to process (YES in S34), the CPU 30 repeatedly executes steps S10 to S32. On the other hand, if there is no next task to process (NO in S34), the CPU 30 terminates the task process.

Meanwhile, at time t13 in Figure 4, the transmission process begins. During the transmission process, the CPU 30 uses a timer function to obtain the start time (third start time) t13 at the time the transmission process begins and stores it in memory 50 (S40). Based on the start time t13 and the second period F, the CPU 30 calculates the start time t15 of the next scheduled transmission process and stores it in memory 50 (S50). For example, the CPU 30 can calculate the start time t15 by adding the second period F to the start time t13. Note that the calculated start time t15 is a future scheduled time calculated through this process.

Here, the CPU 30 determines whether the start time t15 of the next transmission process falls within the input processing period (i.e., t17 to t17+D) starting from the start time t17 of the next input/output process (S60). t17+D is t19. That is, the CPU 30 determines whether the start time t15 of the next transmission process overlaps with the input/output processing period t17 to t19.

Memory 50 holds flag information (1-bit data) indicating whether the start time of the next transmission process is included in the period of the next input/output process. If the start time of the next transmission process is included in the period of the next input/output process (YES in S60), the CPU 30 sets the flag information (inverts the bit) (S75). If the start time of the next transmission process is not included in the period of the next input/output process (NO in S60), the CPU 30 does not set the flag information (does not invert the bit) (S70). In the example in Figure 4, the start time t15 of the next transmission process is not included in the period t17-t19 of the next input/output process (NO in S60), so the CPU 30 does not set the flag information (S70). The flag information is used to determine whether or not to delay the transmission process.

Furthermore, the CPU 30 checks whether the flag information is set for the current transmission process at t13-t14 (S80). If the flag information is set (YES in S80), the CPU 30 stops the transmission process timer (S82) and sets the start time of the current transmission process at t13-t14 to a time delayed by at least the execution period D of the input/output process (S84). For example, since the start time of the current transmission process at t13-t14 does not overlap with the input/output process period, the flag information corresponding to the transmission process at t13-t14 is not set. Therefore, the CPU 30 starts the transmission process at t13 as scheduled without delay (S100). In the transmission process, the CPU 30 transfers the data from the common memory 60 to the LAN controller 80 and requests transmission. The LAN controller 80 transmits the data accumulated in the transmission queue to the other controllers 12-15 via the network 20.

Once the transmission process in steps t13-t14 is complete, the CPU 30 checks if there is another task. If there is another task (YES in S110), the CPU 30 repeatedly executes steps S40-S100.

In the example shown in Figure 4, since the following task processing is involved, for example, in the transmission processing at t15 to t16, the CPU 30 executes steps S40 to S100. At this time, in step S80, the CPU 30 checks the flag information in memory 50 corresponding to the transmission processing at t15 to t16. Since the flag information corresponding to the transmission processing at t15 to t16 is not set, the CPU 30 executes the transmission processing at t15 to t16 without delay (S100).

Furthermore, at time t15, the CPU 30 executes steps S40 to S60 and calculates the start time (fourth start time) t18 of the next scheduled transmission process based on the start time t15 and the second period F, and stores it in memory 50. For example, the CPU 30 can calculate the start time t18 by adding the second period F to the start time t15. Note that the calculated start time t18 is a future scheduled time determined by calculation.

Here, the CPU 30 determines whether the start time t18 of the next transmission process falls within the period t17-t19 of the next input/output process (S60). That is, the CPU 30 determines whether the start time t18 of the next transmission process overlaps with the period t17-t19 of the next input/output process.

The start time t18 of the next transmission process is included in (overlaps with) the period t17-t19 of the next input/output process (YES in S60), so the CPU 30 sets the flag information (S75).

Next, at time t17, the task processing ends and the next task processing begins (YES in S34). Therefore, steps S10 to S32 in Figure 6 are executed again from time t17 to t19.

At this time, at t17, the CPU 30 uses its timer function to obtain the start time t17 when it starts the input/output processing and stores it in the memory 50 (S10). Based on the start time t17 and the first period B, the CPU 30 calculates the start time (second start time) t25 of the next planned input/output processing and stores it in the memory 50 (S20). For example, the CPU 30 can calculate the start time t25 by adding the first period B to the start time t17. Note that the calculated start time t25 is a future planned time calculated through this process.

Here, at time t17, the CPU 30 determines whether the start time t21 of the next transmission process falls within the input processing period (i.e., t25 to t25+D) starting from the start time t25 of the next input/output process (S60). t25+D is t26. That is, the CPU 30 determines whether the start time t21 of the next transmission process overlaps with the input/output processing period t25 to t26.

The CPU 30 determines that the start time t21 of the next transmission process is not included in the period t25-t26 of the next input/output process (NO in S60), therefore the CPU 30 does not set the flag information (S70).

Next, at the start time of the transmission process between t18 and t20, the CPU 30 executes steps S40 to S100 again. At this time, in steps S60 to S75, the CPU 30 determines whether the start time t21 of the next transmission process is included in the period t25 to t26 of the next input/output process, and sets (or does not set) flag information based on the result of that determination. For example, at the scheduled start time of the transmission process at t18, the CPU 30 calculates the start time (second start time) t21 of the transmission process to be executed next (second start time) based on the start time t18 and the second period F, and stores it in the memory 50. For example, the CPU 30 can calculate the start time t21 by adding the second period F to the start time t18. Furthermore, the CPU 30 determines whether the start time t21 of the next transmission process is included in the period t25 to t26 of the next input/output process (S60). In other words, the CPU 30 determines whether the start time t21 of the next transmission process overlaps with the period t25-t26 of the next input/output process. In this embodiment, the start time t21 of the next transmission process is not included in (does not overlap with) the period t25-t26 of the next input/output process (NO in S60), so the CPU 30 does not set the flag information (S70).

Furthermore, in step S80, the CPU 30 checks the flag information in memory 50 corresponding to the transmission processes t18 to t20. At this time, the CPU 30 finds that the flag information corresponding to the transmission processes t18 to t20 is set, so it delays the transmission processes t18 to t20. In this case, the CPU 30 stops the timer for the transmission process (S82). In addition, the CPU 30 sets the start time t18 of the current transmission process shown in Figure 4 to the time t18_1 in Figure 5, which is delayed by the execution period D or more of the input/output process from the start time t17 of the input/output process (S84). That is, the CPU 30 delays the transmission process to the time t18_1, which is obtained by adding the input/output process period D or more to the start time t18 of the transmission process. As a result, the start time t18 of the transmission process is shifted to t18_1, which is after the input/output process period from t17 to t19. As a result, the transmission processes from t18_1 to t20_1 no longer overlap with the input/output processes from t17 to t19. The CPU 30 sets the start time t18 of this transmission process to t18_1, and then starts the timer.

Here, we will explain the delay processing for transmission. As shown in Figure 4, if the start time of the transmission process at t18 overlaps with the input/output processing period t17-t19, the transmission process from t18-t20 will start before the calculation result data is stored in the common memory 60 during the input/output processing from t17-t19. Therefore, the calculation result data from t17-t19 is not yet ready for transmission during the transmission process from t18-t20 and cannot be sent to other controllers 12-15. In this case, as shown in Figure 4, the calculation result data processed during input/output at t17-t19 will be transmitted during the transmission process at t21-t22, which is started after the transmission process at t18-t20. Consequently, even with strict time management of the gate control for the transmission process, the real-time nature of the transmission of calculation result data from t17-t19 will be compromised.

Therefore, in this embodiment, as shown in Figure 5, when the flag information corresponding to the transmission processes t18 to t20 is set, the CPU 30 delays the transmission processes t18 to t20 by at least the input processing execution period D (S120 in Figure 6). As a result, the transmission processes t18 to t20 are delayed (corrected) to t18_1 to t20_1, shifting them immediately after the input/output processes t17 to t19. Consequently, the transmission processes t18_1 to t20_1 do not overlap with the input/output processes t17 to t19, allowing the CPU 30 to transmit the calculation result data from t17 to t19. This improves the real-time performance of the calculation result data transmission process.

As shown in Figure 5, the CPU 30 executes transmission processing in t18_1 to t20_1. During the transmission processing in t18_1 to t20_1, the CPU 30 transfers data from the common memory 60 to the LAN controller 80 and sends a transmission request. The LAN controller 80 transmits the data accumulated in the transmission queue to other controllers 12 to 15 via the network 20.

At this time, the gate opening time of the transmission queue corresponding to the data priority is rescheduled to match the timing of the transmission process. For example, if the data priority is "medium," the data is stored in transmission queue Q2 in Figure 3. At this time, the gate opening time of transmission queue Q2 (t3 to t4) is rescheduled (corrected) from t18 to t20 to t18_1 to t20_1. That is, the start time of gate opening t3 is set to the delayed start time of transmission processing t18_1, and the end time of gate opening t4 is set to the delayed start time of transmission processing t20_1. This allows the gate function of transmission queue Q2 to function effectively, improving the real-time nature of the data.

The CPU 30 sets the end time of the transmission process from t18_1 to t20_1 to t20_1, which is the time t20_1 after the start time t18_1 has elapsed by the duration H (for example, approximately 100 μs) of the calculation result data transmission process. The LAN controller 80 executes the transmission of the calculation result data from the start time t18_1 to the end time t20_1. Furthermore, for high-priority data, the LAN controller 80 delays the transmission process if the start time t18 falls within the input/output processing period t17 to t19.

If task processing is ongoing (NO in S110), the CPU 30 repeats steps S40 to S100. Similarly, if the next task processing begins in step S34, the CPU 30 repeats steps S40 to S100. When all task processing is completed (NO in S34), the task processing terminates. Note that none of the transmission processes at t21-t22, t23-t24, and t27-t28 overlap with the input/output processing periods. Therefore, these transmission processes are started as scheduled at t21, t23, and t27.

Thus, if the start time of the transmission process overlaps with the period of the input/output process, the controller 11 delays the transmission process by at least the execution period D of the input/output process. This allows the transmission process of the calculation result data to be executed immediately after the input/output process of that calculation result data, thereby improving the real-time performance of the calculation result data transmission process.

(Second Embodiment)
Figure 8 is a table showing the task processing times of controllers 11 to 15 according to the second embodiment. In the second embodiment, it is assumed that each of the controllers 11 to 15 has a function to correct the start time of the transmission process according to the first embodiment. In the second embodiment, the transmission processing period and the gate opening period of the transmission queue of the LAN controller 80 are adjusted among the controllers 11 to 15 so that the data of the multiple controllers 11 to 15 do not collide on the network 20.

In Figure 8, the next high-speed task activation time indicates the start time of the next high-priority task. The task start time is the same as the start time of the input/output processing (input and output processing), corresponding, for example, to t11, t17, and t25 in Figures 4 and 5. Furthermore, at time t11, the start time of the next task processing is t17, and at time t17, the start time of the next task processing is t25. The start time of the next task processing is calculated in step S20 of Figure 6. The data from the high-speed task processing is stored in the transmission queue Q1 shown in Figure 3 and transmitted via the network 20 at the next high-speed task activation time.

Furthermore, the next medium-speed task start time indicates a lower priority than the high-speed task processing and represents the start time of the next medium-speed task. Data from the medium-speed task processing is stored in transmission queue Q2, as shown in Figure 3. The next low-speed task start time indicates a lower priority than both the high-speed and medium-speed task processing and represents the start time of the next task. Data from the low-speed task processing is stored in transmission queue Q3, as shown in Figure 3.

Each of the controllers 11-15 transmits its own next high-speed task start time, next medium-speed task start time, and next low-speed task start time to the other controllers via multicast communication over the network 20. This allows controllers 11-15 to obtain information on their own and the other controllers' next high-speed task start times, next medium-speed task start times, and next low-speed task start times, as shown in Figure 8. These next high-speed task start times, next medium-speed task start times, and next low-speed task start times are stored in the memory 50 or common memory 60 of each controller 11-15.

Furthermore, controllers 11-15 transmit their own identifier (node number) along with their next high-speed task start time, next medium-speed task start time, next low-speed task start time, next high-speed transmission process start time, next medium-speed transmission process start time, and next low-speed transmission process start time. This allows each controller 11-15 to identify which controller the information originated from.

Controllers 11 to 15 each calculate the next transmission process start time using the process shown in Figure 7 of the first embodiment, and set flag information if the next transmission process start time falls within the period D of the input/output process execution time, from the next task start time. The transmission process start time is the start time of the transmission process, for example, t13, t15, t18, t21, t23, and t27 in Figures 4 and 5. At time t13, the next transmission process start time is t15, and at time t15, the next transmission process start time is t18. Similarly, at t18, t21, and t23, the next transmission process start times are t21, t23, and t27, respectively. The next transmission process start time is calculated in step S50 of Figure 7. The flag information is set in step S70 or S75 of Figure 7.

In this way, controllers 11 to 15 obtain and share information about the next high-speed task start time, the next medium-speed task start time, and the next low-speed task start time of other controllers via multicast communication. Furthermore, controllers 11 to 15 also obtain and share information about the next high-speed transmission process start time, the next medium-speed transmission process start time, and the next low-speed transmission process start time of other controllers via multicast communication.

The transmission processing period is calculated by adding the transmission processing start time to the transmission processing duration H.

In controllers 11-15, the LAN controller 80 allocates data transmission periods in order of priority. Even between different controllers 11-15, the LAN controller 80 allocates data transmission periods in order of priority. Therefore, if the data transmission periods of any of the controllers 11-15 overlap, the LAN controller 80 of controllers 11-15 allocates the transmission period to the data with the highest priority. If the transmission periods of data with the same priority overlap, the LAN controller 80 of controllers 11-15 allocates the transmission periods in order of the controller identifiers (node numbers). This assignment of transmission periods is performed equally in each of the controllers 11-15 and is shared as the same assignment information.

The CPUs 30 of controllers 11-15, upon completion of the transmission process, set the start time for their next transmission process and the release time of the transmission queue, according to the assigned transmission period. The start time for the next transmission process is adjusted by disabling the timer function of the CPU 30. The LAN controller 80 changes the transmission queue release time setting shown in Figure 3 to the start time (e.g., t18_1) and end time (e.g., t18_1+H) of the next transmission process.

Thus, in the second embodiment, the transmission processing time and the release period of the transmission queue can be scheduled considering the task processing and transmission processing of multiple controllers 11-15 connected to the network 20. As a result, the real-time nature of the communication data can be further improved.

Figure 9 is a flowchart showing an example of the operation of controllers 11-15 according to the second embodiment. Note that the operation in steps S200-S270 may be the same as the operation in steps S40-S84 in Figure 7.

First, controllers 11 to 15 each update the information shown in Figure 8 at their own node (their own controller) (S200). The information updates for controllers 11 to 15 can be performed via multicast communication over the network 20, as described above.

Next, the current time, task processing cycle information, and elapsed time from the start of task processing to the present (timer information) are obtained (S210).

Next, the remaining time for the task is calculated by subtracting the elapsed time from the task processing cycle information. This remaining time is then added to the current time to calculate the start time for the next task processing (S220).

Next, the CPU 30 determines whether the processing start time for the next transmission process falls within the period of the node's next task processing (S230). In other words, it determines whether the next transmission process overlaps with the node's next task processing.

If the processing start time for the next transmission process falls within the duration of the next task (YES in S230), the flag information is set (S240). In this case, the CPU 30 sets the start time for the next transmission process of its own node to the task start time + task duration (S250). This delays the next transmission process, preventing it from overlapping with the next task.

On the other hand, if the processing start time for the next transmission process is not within the period of the next task processing (NO in S230), the flag information is not set (S260). In this case, the CPU 30 sets the next transmission process start time for its own node to the next transmission process start time calculated in step S220. The next transmission process does not overlap with the next task processing even without delay.

Next, the local node selects the next transmission process in order of priority (S280). The selected next transmission process is executed so as not to overlap with the transmission process periods of other nodes or the local node. For example, the CPU 30 determines whether the start time of the selected next transmission process falls within the transmission process period of other nodes or the local node (S290, S291). If the start time of the selected next transmission process falls within the transmission process period of other nodes (YES in S290), the CPU 30 compares the priority of the local node's transmission process with that of other nodes (S293). If the priority of the local node's transmission process is higher than that of other nodes (YES in S293), the CPU 30 executes the transmission process at the start time of the next transmission process without changing the start time of the selected next transmission process on the local node (S294). On the other hand, if the priority of the local node's transmission process is lower than the priority of the other nodes' transmission processes (NO in S293, YES in S295), the CPU 30 adds the transmission process duration H to the selected next transmission process start time (S300). This delays the next transmission process, preventing it from overlapping with the transmission process duration of other nodes.

Furthermore, there are cases where the priority of the local node's transmission process is the same as the priority of the other node's transmission process (YES in S295). In this case, the CPU 30 compares the local node's node number with the other node's node number (S296). If the local node's node number is smaller than the other node's node number (YES in S296), the CPU 30 does not change the selected start time of the next transmission process for the local node and executes the transmission process at the next transmission process start time (S294). On the other hand, if the local node's node number is larger than the other node's node number (NO in S296), the CPU 30 adds the transmission process period H to the selected start time of the next transmission process for the local node (S300). Furthermore, the CPU 30 sets flag information (S310). The CPUs 30 of the other nodes also process steps S280 to S300 in the same way. In this manner, if the transmission processing periods of controllers 11-15 overlap, the transmission processing is executed in order of highest priority. Furthermore, if the priorities are the same, the transmission processing is executed in order of lowest node number. Since each controller (11-15) has a unique node number, the node numbers will never be the same (overlap). This allows controllers 11-15 to adjust their respective node transmission processing periods so that they do not overlap with the transmission processing periods of other nodes.

Furthermore, if the start time of the selected next transmission process falls within the local node's transmission process period (YES in S291), the CPU 30 compares the priority of the selected next transmission process with other overlapping transmission processes (S292). If the priority of the selected next transmission process is lower than that of the other transmission processes (NO in S292), the CPU 30 adds the transmission process period H to the selected next transmission process start time (S300). The CPU 30 then sets a flag (S310). This delays the next transmission process to prevent it from overlapping with the local node's transmission process period. On the other hand, if the priority of the selected next transmission process is higher than that of the other transmission processes (YES in S292), the CPU 30 does not change the start time of the selected next transmission process and executes the transmission process at the scheduled start time (S294).

If the selected start time for the next transmission process is not within the transmission process period of other nodes or the local node (NO in S290, NO in S291), the start time for the next transmission process will remain unchanged.

The CPU 30 similarly selects other transmission processes in order of priority and executes steps S290 to S310 (YES in S320).

After executing steps S290 to S310 for all transmission processes (NO in step S320), the CPU 30 executes a transmission process depending on whether the flag information is set or not (S330). If the flag information is set (YES in S330), it indicates that the original next transmission process time overlaps with the next task processing period or another transmission process period at the local node. Therefore, for example, the CPU 30 temporarily stops the periodic timer that starts the transmission process (S340) and sets it as the new next transmission process start time set (modified) in step S250 or step S300 (S350). Here, the transmission process start time set (modified) in step S250 may be further modified in step S300. In this case, the next transmission process start time will be the task start time + task processing period + transmission process period H.

Next, the CPU 30 starts a fixed-period timer to initiate the transmission process (S360).
On the other hand, if the flag information is not set (NO in S330), it indicates that the original next transmission processing time at the local node does not overlap with the next task processing period or other transmission processing periods. Therefore, the CPU 30 executes the transmission process without stopping the timer or correcting the next transmission processing start time.

During the transmission process, the CPU 30 sets the next transmission process startup time for its own node at the start time of the release of the transmission queue corresponding to the priority of each transmission process (S370). Furthermore, the CPU 30 sets the next transmission process startup time for its own node plus the transmission process duration H at the end time of the release of the transmission queue corresponding to the priority of each transmission process (S380).

This completes the task processing.

Thus, in the second embodiment, the transmission processing time and the release period of the transmission queue can be scheduled considering the task processing and transmission processing of the multiple controllers 11-15 connected to the network 20. As a result, real-time performance can be further improved while suppressing collisions of communication data.

While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the claims and its equivalents.

11-15 Controllers, 20 Networks, 30 CPUs, 40 I/O Bus Controllers, 50 Memory, 60 Common Memory, 70 Interface Bridges, 80 LAN Controllers, 90 I/O Devices, 100 Industrial Machinery

Claims (8)

A controller that controls the object being controlled,
A first interface controller is connected to the controlled object in a communication manner and periodically receives data from the controlled object.
A first storage unit for storing the aforementioned data,
A calculation unit that inputs the aforementioned data, performs calculations on it, and transfers it to the first storage unit,
It comprises a second interface controller that is connected to communicate with other controllers and performs a transmission process that periodically transmits the data to the other controllers,
The calculation unit is a controller that, when the start time of the transmission process overlaps with the period of the data input process, delays the start time of the transmission process to a later time than the period of the input process. The controller according to claim 1, wherein the data transmission process is an equalization process that transmits the data to the other controller and stores the data from the other controller in the first storage unit. The system further includes a second storage unit that stores the period of input processing for inputting the data from the first interface controller, a first period from the input processing of the first data to the input processing of the next second data, and a second period from the transmission processing of the first data to the transmission processing of the second data.
The calculation unit has a timer function, and when the input processing of the first data is actually started, it calculates the second start time of the input processing of the second data to be input next, based on the first start time at that time and the first cycle, and stores it in the second storage unit.
The calculation unit, upon actually starting the transmission process of the first data, calculates the fourth start time of the transmission process of the second data to be transmitted next, based on the third start time at that time and the second cycle, and stores it in the second storage unit.
The controller according to claim 1 or 2, wherein the calculation unit delays the fourth start time to a period of time longer than or equal to the period of time The controller according to claim 3, wherein the calculation unit calculates the second start time by adding the first period to the first start time at the first start time, and calculates the fourth start time by adding the second period to the third start time at the third start time. The controller according to claim 3, wherein the calculation unit delays the transmission process of the second data until a fifth start time obtained by adding a period equal to or greater than the duration of the input processing to the fourth start time. The controller according to claim 5, wherein the calculation unit stops the timer function for a period longer than the input processing period. The second storage unit has flag information that is inverted when the fourth start time is included within the period of the input processing from the second start time,
The controller according to claim 3, wherein the calculation unit delays the transmission process of the second data based on the flag information. A control method for a controller that controls a controlled object, comprising: a first interface controller connected to a controlled object in a communicative manner; a second interface controller connected to another controller in a communicative manner; a first storage unit; and an arithmetic unit, wherein the controller controls the controlled object,
The first interface controller receives data from the controlled object.
The aforementioned data is periodically input and processed and stored in the first storage unit.
A controller control method comprising: when the second interface controller performs a transmission process in which it periodically transmits the data to the other controller, if the start time of the transmission process overlaps with the period of the data input process, delaying the start time of the transmission process to a later period than the period of the input process.