JP7850349B2 - Display panel and display device - Google Patents

Description

This application claims priority to the Chinese patent application filed with the China Patent Office on July 26, 2023, application number 202310938917.5, and all contents of the aforementioned application are incorporated into this application by reference.

The embodiments of this application relate to the field of display technology, for example, to display panels and display devices.

Flat-panel displays based on technologies such as organic light-emitting diodes (OLEDs) and light-emitting diodes (LEDs) offer advantages such as high image quality, low power consumption, thin design, and a wide range of applications. Therefore, they are widely used in various consumer electronic products such as mobile phones, televisions, laptops, and desktop computers, and have become the mainstream type of display device.

However, there is still room for improvement in the display effectiveness of OLED display products in related technologies.

Embodiments of the present application provide a display panel and a display device.

The embodiments of this application are as follows:
Bass and,
An array circuit layer located on the aforementioned base and comprising multiple drive transistors,
A plurality of subpixel units, each having a pixel definition layer and a first electrode, are located on the side of the array circuit layer that is separated from the base.
The device comprises a first electrode plate provided in the same layer as the first electrode and covered by the pixel definition layer, and a second electrode plate located on the side away from the base of the pixel definition layer, wherein the orthographic projection of the first electrode plate on the base and the orthographic projection of the second electrode plate on the base at least partially overlap, and the first electrode plate comprises a first capacitor connected to the gate electrode of the drive transistor.
Provides a display panel.

The embodiments of this application are as follows:
Bass and,
An array circuit layer located on the aforementioned base and comprising multiple drive transistors,
A plurality of subpixel units, each having a pixel definition layer located on the side of the array circuit layer away from the base, the pixel definition layer having a pixel definition section and an aperture area enclosed and closed by the pixel definition section, and a first electrode exposed from the aperture area,
A first capacitor comprising a first plate and a second plate whose orthographic projections on the base at least partially overlap, wherein the first plate is connected to the gate electrode of the drive transistor,
The system includes an isolation portion located on one side of the base, at least partially surrounding the opening area, the orthographic projection of the base at least partially overlapping with the orthographic projection of the first electrode plate at the base, and at least a portion of which is also used as the second electrode plate,
Further display panels will be provided.

The embodiments of this application are as follows:
To provide the base,
Forming an array circuit layer comprising multiple drive transistors on the aforementioned base,
A first electrode plate connected to the gate electrode of the drive transistor and a first electrode in the subpixel unit are formed on the side of the array circuit layer that is separated from the base,
A pixel definition layer is formed covering the first electrode plate on the side of the first electrode plate that is separated from the base,
The second electrode plate is formed on the side of the pixel definition layer that is separated from the base, and the orthographic projection of the first electrode plate on the base and the orthographic projection of the second electrode plate on the base at least partially overlap, and the first electrode plate and the second electrode plate constitute the two electrodes of the first capacitor,
Further information on the manufacturing method of display panels will be provided.

The embodiments of this application further provide a display device comprising the display panel described in any embodiment of this application.

The display panel, its manufacturing method, and display device according to the embodiment of the present application utilize a first capacitor to store the gate electrode voltage of the drive transistor. For example, the first electrode plate may be provided in the same layer as the first electrode, and the second electrode plate may be provided on the side away from the base of the pixel definition layer. The first and second electrode plates may be insulated by the pixel definition layer. By using the pixel definition layer as a capacitor dielectric layer between the first and second electrode plates, it is advantageous to increase the capacitance value of the first capacitor, improve the stability of the gate electrode voltage of the drive transistor, and improve the display effect of the display panel.

As can be seen from the above, the present invention's technical solution, by forming a first capacitor and using it as a storage capacitor in the pixel circuit, is advantageous in increasing the capacitance value of the storage capacitor, avoids the constraints on the capacitance value of the storage capacitor due to the design of high pixel density units (Pixels Per Inch, PPI), improves the stability of the gate electrode voltage of the drive transistor, and improves the display effect of the display panel.

This is a plan view of a display panel according to an embodiment of the present invention. This is a cross-sectional view obtained by cutting the display panel shown in Figure 1 along the cutting line BB'. This is a schematic diagram of the structure of a pixel circuit according to an embodiment of the present invention. This is another cross-sectional view obtained by cutting the display panel shown in Figure 1 along the cutting line BB'. Figure 1 is a magnified view of the M region in the display panel shown. This is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present invention. This is a schematic diagram of the flow chart for the manufacturing method of the display panel according to the embodiment of the present invention. This is a schematic diagram of the structure of a display panel formed in some steps of the method for manufacturing a display panel according to an embodiment of the present invention. This is a schematic diagram of the structure of a display panel formed in another step of the method for manufacturing a display panel according to an embodiment of the present invention. This is a schematic diagram of the structure of a display panel formed in another step of the method for manufacturing a display panel according to an embodiment of the present invention. This is a schematic diagram of the structure of a display panel formed in another step of the method for manufacturing a display panel according to an embodiment of the present invention.

The terms "First," "Second," etc., in the specification, claims, and drawings of this application do not need to be used to describe a specific order or sequence, but are intended to distinguish similar subjects. The data used in this manner is replaceable where appropriate, and it should be understood that the embodiments of this application described herein can be carried out in an order other than that illustrated or described herein. Furthermore, the terms "includes" and "have," and any variations thereof, are intended to cover non-exclusive inclusion, and may include, for example, other processes, methods, systems, products, or equipment of a set of steps or units shown in the embodiments of this application, other processes, methods, systems, products, or equipment not explicitly mentioned, or other steps or units specific to those processes, methods, systems, products, or equipment.

In display panels with high pixel density units (Pixels Per Inch, PPI), the limited area of a single subpixel makes it difficult to increase the size of the storage capacitor in the pixel circuit. This affects the stability of the gate electrode voltage of the drive transistor in the pixel circuit, resulting in display abnormalities such as flicker and bright spots on a black screen, thus limiting improvements in display performance.

This embodiment provides a display panel. Figure 1 is a plan view of the display panel according to this embodiment, Figure 2 is a cross-sectional view obtained by cutting the display panel shown in Figure 1 along the cutting line BB', and Figure 3 is a schematic diagram of the pixel circuit structure according to this embodiment. Referring to Figures 1 to 3, the display panel comprises a base 10, an array circuit layer 20, a pixel definition layer 30, a first capacitor Cst1, and a plurality of sub-pixel units PX. This embodiment forms the first capacitor without adding extra film layers and corresponding mask plates to the display panel, making the first capacitor a storage capacitor in the pixel circuit. This increases the capacitance value of the storage capacitor, avoids the constraints on the capacitance value of the storage capacitor due to the high PPI design, improves the stability of the gate electrode voltage of the drive transistor, and improves the display effect of the display panel.

The array circuit layer 20 is located on the base 10 and comprises multiple pixel circuits, each of which is equipped with a drive transistor DT. The pixel definition layer 30 and sub-pixel unit PX are located on the side of the array circuit layer 20 away from the base 10, and the sub-pixel unit PX comprises a first electrode 40. The first capacitor Cst1 comprises a first plate 110 and a second plate 120. The first plate 110 is provided in the same layer as the first electrode 40, the pixel definition layer 30 covers the first plate 110, and the second plate 120 is located on the side of the pixel definition layer 30 away from the base 10. The orthographic projection of the first plate 110 on the base 10 and the orthographic projection of the second plate 120 on the base 10 at least partially overlap, and the first plate 110 is connected to the gate electrode 220 of the drive transistor DT.

The base 10 can provide protection and support for the display panel. The base 10 may be a flexible base, and the material of the flexible base may be polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a mixture of the above materials. The base 10 may also be a rigid base formed from a material such as glass.

The display panel has a display area AA and a non-display area NAA. Multiple sub-pixel units PX are provided in the display area AA, and the sub-pixel units PX are located in a region defined by the pixel definition layer 30. Each sub-pixel unit PX has a first electrode 40, and the pixel circuit is electrically connected to the first electrode 40 of the corresponding sub-pixel unit PX to drive the light emission of the corresponding sub-pixel unit PX. Exemplarily, each sub-pixel unit PX includes a light-emitting element D0, which may be an organic light-emitting diode (OLED) or a micro-light-emitting diode (Micro-LED). The first electrode 40 is an electrode of the light-emitting element D0, for example, an anode. The drive transistor DT and the light-emitting element D0 are connected between the first power line ELVDD and the second power line ELVSS. The drive transistor DT can generate a drive current based on its gate electrode voltage to drive the light emission of the light-emitting element D0, so that the display panel becomes displayable.

An overlapping region exists between the orthographic projection of the first electrode plate 110 on the base 10 and the orthographic projection of the second electrode plate 120 on the base 10. The pixel definition layer 30 covers the first electrode plate 110, while the second electrode plate 120 is located on the side of the pixel definition layer 30 that is separated from the base 10. As a result, the first electrode plate 110 and the second electrode plate 120 are insulated by the pixel definition layer 30, and the first electrode plate 110 and the second electrode plate 120 can constitute the first capacitor Cst1. The first electrode plate 110 of the first capacitor Cst1 is connected to the gate electrode 220 of the drive transistor DT. Thus, the first capacitor Cst1 can act as a storage capacitor in the pixel circuit, storing the gate electrode voltage of the drive transistor DT.

The present invention's embodiment utilizes a first capacitor Cst1 as a storage capacitor to store the gate electrode voltage of the drive transistor DT. The first electrode plate 110 is provided in the same layer as the first electrode 40, and the second electrode plate 120 is provided on the side of the pixel definition layer 30 that is separated from the base 10. The first electrode plate 110 and the second electrode plate 120 are insulated by the pixel definition layer 30. Because the material of the pixel definition layer 30 has a high dielectric constant and is typically thin, using the pixel definition layer 30 as a capacitor dielectric layer between the first electrode plate 110 and the second electrode plate 120 is advantageous for increasing the capacitance value of the first capacitor Cst1, improving the stability of the gate electrode voltage of the drive transistor DT, and thus improving the display effect of the display panel.

As can be seen from the above, the technical method of the embodiment of this application allows the first capacitor to be formed without adding extra film layers and corresponding mask plates to the display panel, and the first capacitor can be used as a storage capacitor in the pixel circuit. This is advantageous for increasing the capacitance value of the storage capacitor, avoiding the constraints on the capacitance value of the storage capacitor due to the design of high PPI, and by increasing the capacitance value of the storage capacitor, the stability of the gate electrode voltage of the drive transistor is improved, and the display effect of the display panel is improved.

There are various specific installation methods for the first capacitor Cst1; however, several of these will be explained exemplified below.

Referring to Figures 1 to 3, in one embodiment, the subpixel unit PX further comprises a second electrode 60 located on the side away from the base 10 of the pixel definition layer 30, and the second electrode plate 120 and the second electrode 60 contain different materials. The second electrode 60 may be the cathode of the light-emitting element D0. Both the second electrode plate 120 and the second electrode 60 are located on the side away from the base 10 of the pixel definition layer 30, and both the second electrode plate 120 and the second electrode 60 may contain conductive materials, and the light transmittance of the second electrode 60 is greater than the light transmittance of the second electrode plate 120. Preferably, the second electrode plate 120 and the second electrode 60 are provided in different layers, that is, they may be located in different layers, and both the second electrode plate 120 and the second electrode 60 are located on the side away from the base 10 of the pixel definition layer 30, but the second electrode plate 120 and the second electrode 60 are formed in different film layer manufacturing processes. For example, the second electrode plate 120 may be formed first on the side away from the base 10 of the pixel definition layer 30, and then the second electrode 60 may be formed on the side away from the base 10 of the pixel definition layer 30. By including different materials in the second electrode plate 120 and the second electrode 60, and/or positioning them in different layers, the second electrode plate 120 and the second electrode 60 are formed as separate structures rather than as an integrated structure. The second electrode plate 120 and the second electrode 60 are then installed using the space on the side of the pixel definition layer 30 that is separated from the base 10, thereby achieving the aforementioned effects while avoiding an increase in the thickness of the display panel.

Preferably, the pixel definition layer 30 comprises a pixel definition section 310 and an opening area 320 enclosed and closed by the pixel definition section 310, the opening area 320 exposing the first electrode 40. The pixel definition section 310 covers the first electrode plate 110, the second electrode plate 120 is located on the side of the pixel definition section 310 away from the base 10, and the pixel definition section 310 isolates the first electrode plate 110 and the second electrode plate 120, thereby insulating them. The display panel further comprises a light-emitting layer 50, the light-emitting layer 50 is provided in the opening area 320, and the light-emitting layer 50 is located on the side of the first electrode 40 away from the base 10. The second electrode 60 is located on the side of the light-emitting layer 50 that is separated from the base 10. A power supply voltage is applied to the second electrode 60, and the second electrode plate 120 contacts the second electrode 60 so that the power supply voltage is applied. The power supply voltage may be a fixed voltage or a voltage with a variable value. For example, the power supply voltage may remain constant within the same display cycle, while the numerical value of the power supply voltage may differ within different display cycles.

The pixel definition section 310 is made of an insulating material with a high dielectric constant and thin thickness. Using the pixel definition section 310 as a capacitor dielectric layer between the first electrode plate 110 and the second electrode plate 120 is advantageous for increasing the capacitance value of the first capacitor Cst1, improving the stability of the gate electrode voltage of the drive transistor DT, and improving the display effect of the display panel. The second electrode 60 is located on the side of the light-emitting layer 50 that is separated from the base 10, and part of the pixel definition section 310 is located on the side of the pixel definition section 310 that is separated from the base 10. The second electrode 60 and the second electrode plate 120 are in contact to achieve electrical connection. The second electrode 60 is connected to the second power line ELVSS as the cathode of the light-emitting element D0. The second power line ELVSS receives the power supply voltage, that is, the second power line ELVSS transmits the power supply voltage to the second electrode 60, thereby supplying the power supply voltage to both the second electrode 60 and the second electrode plate 120. By ensuring that the second electrode plate 120 contacts the second electrode 60 so that the power supply voltage is input, the potential of the second electrode plate 120 is fixed within the same display cycle. The first capacitor Cst1 stores the gate electrode voltage of the drive transistor DT. This eliminates the need to provide a fixed voltage to the second electrode plate 120 independently; the power supply voltage can be used as the fixed voltage input to the second electrode plate 120. This is advantageous in simplifying the display panel structure by reducing the number of signal terminals and signal lines for transmitting voltage signals in the display panel.

Figure 4 is another cross-sectional view obtained by cutting the display panel shown in Figure 1 along the cutting line BB'. Referring to Figures 3 and 4, in another embodiment, the display panel comprises a base 10, an array circuit layer 20, a pixel definition layer 30, a first capacitor Cst1, an isolation section 70, and a plurality of sub-pixel units PX. The array circuit layer 20 is located on the base 10 and comprises a plurality of pixel circuits, each of which is provided with a drive transistor DT. The sub-pixel units PX are provided with a first electrode 40, the pixel definition layer 30 and the first electrode 40 are located on the side of the array circuit layer 20 away from the base 10, the pixel definition layer 30 comprises a pixel definition section 310 and an opening area 320 enclosed and closed by the pixel definition section 310, the opening area 320 exposing the first electrode 40. The first capacitor Cst1 comprises a first plate 110 and a second plate 120. The orthographic projection of the first plate 110 on the base 10 and the orthographic projection of the second plate 120 on the base 10 overlap at least partially, and the first plate 110 is connected to the gate electrode 220 of the drive transistor DT. The isolation portion 70 is located on the base 10, and the orthographic projection of the isolation portion 70 on the base 10 and the orthographic projection of the first plate 110 on the base 10 overlap at least partially, with at least a portion of the isolation portion 70 also serving as the second plate 120.

The isolation portion 70 includes a conductive material, for example, a metallic material. The isolation portion 70 may be provided on the side of the pixel definition layer 30 that is away from the base 10, for example, the isolation portion 70 is provided to surround at least a portion of the aperture area 320. Preferably, the first electrode plate 110 is provided in the same layer as the first electrode 40, the pixel definition layer 30 covers the first electrode plate 110, and the isolation portion 70 is located on the side of the pixel definition layer 30 that is away from the base 10, thereby insulating the first electrode plate 110 and the isolation portion 70 from the pixel definition layer 30. The subpixel unit PX may include a first electrode 40, a light-emitting layer 50, and a second electrode 60, and the isolation portion 70 is located between adjacent subpixel units PX so as to isolate adjacent subpixel units PX. Since the first electrode plate 110 and the isolation portion 70 are insulated by the pixel definition layer 30, and the orthographic projection of the isolation portion 70 on the base 10 overlaps with the orthographic projection of the first electrode plate 110 on the base 10, the isolation portion 70 can also be used as the second electrode plate 120. This allows the first capacitor Cst1 to be formed using the first electrode plate 110 and the isolation portion 70, and the first capacitor Cst1 can function as a storage capacitor. In achieving the aforementioned effects, the existing isolation portion 70 in the display panel can be used as the second electrode plate 120, eliminating the need to install an extra second electrode plate 120, which is advantageous in simplifying the display panel manufacturing process.

Preferably, by inputting the power supply voltage to the isolation section 70, which also serves as the second electrode plate 120, the potential of the second electrode plate 120 within the same display cycle is fixed. This allows the first capacitor Cst1 to store the gate electrode voltage of the drive transistor DT. In this way, it is not necessary to provide a fixed voltage to the second electrode plate 120 independently; the power supply voltage can be used as the fixed voltage that needs to be input to the second electrode plate 120. This is advantageous in simplifying the structure of the display panel by reducing the number of signal terminals and signal lines for transmitting voltage signals in the display panel.

Preferably, the isolation portion 70 is located on the side of the pixel definition portion 310 that is separated from the base 10, and the pixel definition portion 310 covers the first electrode plate 110, insulating the first electrode plate 110 from the isolation portion 70. The first electrode 40, light-emitting layer 50, and second electrode 60 located in the same aperture area 320 are the same subpixel unit PX, and the light-emitting layer 50 of the subpixel unit PX has a gap on the side surface of the isolation portion 70, that is, the light-emitting layers 50 of multiple subpixel units PX are separated by the side surface of the isolation portion 70, the light-emitting layers 50 of adjacent subpixel units PX are isolated by the isolation portion 70, and the second electrode 60 is superimposed and connected to the isolation portion 70.

As can be seen from the above, the technical solution of the embodiment of the present application is such that the first electrode plate 110 is connected to the gate electrode of the drive transistor DT, the first electrode plate 110 and the first electrode 40 are provided in the same layer, the first electrode plate 110 is one electrode plate of the first capacitor Cst1, the isolation portion 70 is the other electrode plate of the first capacitor Cst1, the pixel definition portion 310 is the capacitor dielectric layer between the two electrodes, and in order to realize the above-mentioned effects, the isolation portion 70 is also used as the second electrode plate 120, the second electrode 60 is connected in overlapping manner to adjacent isolation portions 70, and by inputting a power supply voltage to the isolation portion 70, the first capacitor Cst1 can store the gate electrode voltage of the drive transistor DT, thus eliminating the need to provide a fixed voltage to the isolation portion 70 alone. The power supply voltage can also be used as a fixed voltage that needs to be input to the second electrode plate 120. This is advantageous in simplifying the structure of the display panel by reducing the number of signal terminals and signal lines for transmitting voltage signals in the display panel. Furthermore, by inputting the power supply voltage to both the second electrode 60 and the isolation section 70, the overall resistance of the second electrode 60 and the isolation section 70 is reduced. This mitigates the effect of the voltage drop at the second electrode 60 on the magnitude of the power supply voltage, reduces the difference in magnitude of the power supply voltage input to different areas of the display panel, avoids sudden changes in the power supply voltage affecting the amount of charge stored in the first capacitor Cst1, and contributes to ensuring the stability of the gate electrode voltage of the drive transistor DT.

Referring to Figure 4, preferably, the isolation section 70 comprises a first sub-isolation section 710, a second sub-isolation section 720, and a third sub-isolation section 730, which are sequentially stacked on the side of the pixel definition section 310 that is separated from the base 10. One of the first sub-isolation section 710, the second sub-isolation section 720, and the third sub-isolation section 730, or at least two adjacent sections, are conductive isolation sections. The orthographic projection of the conductive isolation section on the base 10 and the orthographic projection of the first electrode plate 110 on the base 10 overlap at least partially, and at least a portion of the conductive isolation section is also used as the second electrode plate 120, receiving the power supply voltage.

Any one of the first sub-isolation section 710, the second sub-isolation section 720, and the third sub-isolation section 730 may be a conductive isolation section, or the first sub-isolation section 710 and the second sub-isolation section 720 may be conductive isolation sections, or the second sub-isolation section 720 and the third sub-isolation section 730 may be conductive isolation sections, or all three sub-isolation sections 710, 720, and 730 may be conductive isolation sections. The conductive isolation section is made from a conductive material (e.g., a metal material), and by having at least a portion of the conductive isolation section also function as the second electrode plate 120 to receive the power supply voltage, it is possible to achieve the aforementioned effects without needing to install an additional second electrode plate 120. This allows the conductive isolation section to function as the second electrode plate 120, which is advantageous in simplifying the display panel manufacturing process.

Preferably, along the direction perpendicular to the base 10, the cross-sections of the first sub-isolation section 710 and the third sub-isolation section 730 are rectangular, and the cross-section of the second sub-isolation section 720 is rectangular or trapezoidal. If the cross-section of the second sub-isolation section 720 is trapezoidal, the lower base of the trapezoid is adjacent to the first sub-isolation section 710, the upper base of the trapezoid is adjacent to the third sub-isolation section 720, the orthographic projection of the third sub-isolation section 730 on the base 10 covers the orthographic projection of the first sub-isolation section 710 on the base 10, and the orthographic projection of the third sub-isolation section 730 on the base 10 covers the orthographic projection of the second sub-isolation section 720 on the base 10.

For example, the length of the third sub-isolation section 730 may be greater than or equal to the length of the first sub-isolation section 710, and the length of the third sub-isolation section 730 may be greater than or equal to the length of the second sub-isolation section 720, where the length of the second sub-isolation section 720 may be the length on the side closer to the first sub-isolation section 710 or the third sub-isolation section 730, where the length of each sub-isolation section is the size of the edge parallel to the first direction Y of each sub-isolation section, and the first direction Y is parallel to the surface of the base 10 on the side closer to the isolation section 70. In this way, the orthographic projection of the third sub-isolation section 730 on the base 10 covers the orthographic projection of the first sub-isolation section 710 on the base 10, and the orthographic projection of the third sub-isolation section 730 on the base 10 covers the orthographic projection of the second sub-isolation section 720 on the base 10, that is, along the first direction Y, the first sub-isolation section 710 The edges on both sides of the second sub-isolation section 720 are designed to contract inward relative to either of the edges on both sides of the third sub-isolation section 730, and the edges on both sides of the second sub-isolation section 720 are designed to contract inward relative to either of the edges on both sides of the third sub-isolation section 730. This allows the second electrode 60 of adjacent sub-pixel units PX to be separated by the first sub-isolation section 710 in the isolation section 70, and the second electrode 60 to be formed between adjacent isolation sections 70. Furthermore, the second electrode 60 can be superimposed on the first sub-isolation section 710, or superimposed on either the first sub-isolation section 710 or the second sub-isolation section 720. If the first sub-isolation section 710 is a conductive isolation section, or if both the first sub-isolation section 710 and the second sub-isolation section 720 are conductive isolation sections, the power supply voltage is input to the conductive isolation section by the second electrode 60.

Continuing with Figure 4, the pixel definition section 310 includes an inorganic insulating layer material, preferably comprising at least one of a silicon oxide layer and a silicon nitride layer. For example, the pixel definition section 310 may be made of silicon oxide material, i.e., the pixel definition section 310 is a silicon oxide layer, or the pixel definition section 310 may be made of silicon nitride material, i.e., the pixel definition section 310 is a silicon nitride layer, or the pixel definition section 310 may comprise at least one silicon oxide layer and at least one silicon nitride layer arranged in a laminate. Forming the pixel definition section 310 with an inorganic insulating layer material such as silicon oxide and/or silicon nitride is advantageous in increasing the dielectric constant of the pixel definition section 310 and thereby increasing the capacitance value of the first capacitor Cst1.

Preferably, the total thickness of the pixel definition section 310 is in the range of 100 nm to 1000 nm. For example, the total thickness of the pixel definition section 310 may be 500 nm. In this way, the thickness of the pixel definition section 310 can be reduced, and the capacitance value of the first capacitor Cst1 can be further increased.

Figure 5 is an enlarged view of region M in the display panel shown in Figure 1, where only a portion of the film layer of the display panel is shown. Referring to Figures 4 and 5, preferably, the first electrode plate 110 and the first electrode 40 are insulated, the first electrode plate 110 is located between adjacent first electrodes 40, and by providing the first electrode plate 110 using the region between adjacent first electrodes 40, the space utilization rate of the display panel can be improved while achieving the aforementioned effects.

Preferably, in one embodiment, the first electrode plate 110 is provided surrounding the first electrode 40, forming an annular structure that encircles the periphery of the first electrode 40, and the second electrode plate 120 is provided surrounding the aperture area 320 of the pixel definition layer 30. Furthermore, the overlapping region of the orthographic projection of the first electrode plate 110 on the base 10 and the orthographic projection of the second electrode plate 120 on the base 10 surrounds the aperture area 320. This further improves the space utilization rate of the display panel, and simultaneously increases the area of the first electrode plate 110 and the second electrode plate 120, increasing the vertically overlapping area of the first electrode plate 110 and the second electrode plate 120, increasing the capacitance value of the first capacitor Cst1, further improving the stability of the gate electrode voltage of the drive transistor DT, and contributing to improved display effectiveness.

Referring to Figures 3 to 5, preferably, the first electrode plate 110 of the first capacitor Cst1 connected to the same pixel circuit is provided surrounding the first electrode 40 of the sub-pixel unit PX driven by the pixel circuit. Exemplarily, the sub-pixel unit PX comprises a sub-pixel unit having a first color light-emitting layer 501, a sub-pixel unit having a second color light-emitting layer 502, and a sub-pixel unit having a third color light-emitting layer 503. Unlike the first, second, and third colors, for example, the first color is red, the second color is green, and the third color is blue. The first electrode plate 110 of the first capacitor Cst1 connected to each pixel circuit is provided surrounding the first electrode 40 of the sub-pixel unit PX driven by the pixel circuit, facilitating the connection between the first electrode plate 110 and the corresponding drive transistor DT in the pixel circuit, thereby simplifying the display panel manufacturing process.

Referring to Figures 2 and 3, the display panel further comprises a connecting electrode 250 provided in the same layer as the source electrode 230 or drain electrode 240 of the drive transistor DT. The connecting electrode 250 is electrically connected to the gate electrode 220 and the first plate 110 of the drive transistor DT, respectively. The first plate 110 is connected to the gate electrode 220 of the drive transistor DT via the connecting electrode 250, and the orthographic projection of the connecting electrode 250 on the base 10 overlaps with the orthographic projection of the gate electrode 220 of the drive transistor DT on the base 10.

For illustrative purposes, the transistor shown in Figure 3 may be a drive transistor DT. The orthographic projection of the first plate 110 on the base 10 overlaps with the orthographic projection of the second plate 120 on the base 10. The connecting electrode 250 is electrically connected to the gate electrode 220 and the first plate 110 of the drive transistor DT, respectively. Furthermore, the orthographic projection of the connecting electrode 250 on the base 10 overlaps with the orthographic projection of the gate electrode 220 of the drive transistor DT on the base 10. Therefore, the first capacitor Cst1 may be equivalently a capacitor formed by the gate electrode 220 and the second plate 120 of the drive transistor DT. By inputting a fixed voltage to the second plate 120, the gate electrode voltage of the drive transistor DT is stored by the first capacitor Cst1. This corresponds to increasing the vertically overlapping area between the gate electrode 220 and the second plate 120 of the drive transistor DT, which is advantageous for increasing the capacitance value of the first capacitor Cst1.

Figure 2 shows a case where the connecting electrode 250 is directly electrically connected to the first electrode plate 110. Referring to Figures 3 and 4, in another embodiment, the display panel further includes a connecting portion 260, which is connected between the first electrode plate 110 and the connecting electrode 250. The connecting portion 260 is located within the metal layer between the first electrode plate 110 and the connecting electrode 250, electrically connecting the first electrode plate 110 and the connecting electrode 250.

Referring to Figures 3 and 4, the array circuit layer 20 comprises multiple metal layers, with an insulating layer between two adjacent metal layers. The multiple metal layers include a first metal layer M1 and a second metal layer M2. The gate electrode 220 of the drive transistor DT is located on the first metal layer M1. The array circuit layer 20 further includes a third electrode plate 130 located on the second metal layer M2. The orthographic projection of the third electrode plate 130 on the base 10 and the orthographic projection of the gate electrode 220 of the drive transistor DT on the base 10 overlap at least partially. The third electrode plate 130 and the gate electrode 220 of the drive transistor DT constitute the two electrodes of the second capacitor Cst2.

For example, a fixed voltage is input to the third electrode plate 130. For instance, the third electrode plate 130 is electrically connected to the first power line ELVDD, and the power supply voltage is transmitted to the third electrode plate 130 by the first power line ELVDD, becoming the fixed voltage input to the third electrode plate 130. The third electrode plate 130 and the gate electrode 220 of the drive transistor DT can constitute a second capacitor Cst2, and the gate electrode voltage of the drive transistor DT is stored by the second capacitor Cst2. In this case, the first power line ELVDD receives the first power supply voltage, and the second power line ELVSS receives the second power supply voltage. That is, the second electrode plate 120 contacts the second electrode 60 so that the second power supply voltage is input. The first and second power supply voltages are different; for example, the voltage value of the first power supply voltage is a positive number, and the voltage value of the second power supply voltage is a negative number or zero. The present invention's embodiment achieves the aforementioned effects by using the first capacitor Cst1 and the second capacitor Cst2 together as the storage capacitors for the pixel circuit. In this configuration, the total capacitance of the storage capacitors in the pixel circuit becomes the sum of the capacitance values of the first capacitor Cst1 and the second capacitor Cst2. Even in designs with high PPI (Power Print Intake), this increases the capacitance value of the storage capacitors, further improving the stability of the gate electrode voltage of the drive transistor DT, and thus further improving the display effect of the display panel.

Continuing with Figure 4, the array circuit layer 20 further comprises an active layer 210, a third metal layer M3, and a fourth metal layer M4. The active layer 210, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are sequentially stacked on one side of the base 10. The source electrode 230 and drain electrode 240 of the drive transistor DT, and the connecting electrode 250 may all be provided within the third metal layer M3, and the connecting portion 260 may be provided within the fourth metal layer M4. Preferably, the display panel further comprises a first sealing layer 810, a second sealing layer 820, and a third sealing layer 830. The first sealing layer 810 is formed on the side of the second electrode 60 and the isolation portion 70 away from the base 10, covering the second electrode 60 and at least a portion of the isolation portion 70. The second sealing layer 820 is formed on the side of the first sealing layer 810 and the isolation portion 70 away from the base 10, covering the first sealing layer 810 and the isolation portion 70. The third sealing layer 830 is formed on the side of the second sealing layer 820 away from the base 10, covering the second sealing layer 820.

Figure 6 is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present application. Referring to Figure 6, the pixel circuit comprises a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a drive transistor DT, and further comprises a first capacitor Cst1 and a second capacitor Cst2 as in the above arbitrary embodiment. Exemplarily, the operation stages of the pixel circuit include an initialization stage, a data writing stage, and an illumination stage. In the initialization stage, the third transistor T3 and the fourth transistor T4 are controlled to turn on in response to the first scanning signal S1, and the gate electrode voltage of the drive transistor DT is initialized by transmitting the initialization voltage input via the initialization signal line Vref to the gate electrode of the drive transistor DT by the third transistor T3, thereby controlling the drive transistor DT to turn on, and the anode voltage of the light-emitting element D0 can be initialized by transmitting the initialization voltage input via the initialization signal line Vref to the anode of the light-emitting element D0 by the fourth transistor T4. During the data writing phase, the first transistor T1 and the second transistor T2 are controlled to turn on in response to the second scanning signal S2, enabling the data voltage input via the data line Data to be sequentially transmitted to the gate electrode of the drive transistor DT by the first transistor T1, the drive transistor DT, and the second transistor T2. The gate electrode voltage of the drive transistor DT is associated with both the data voltage and the threshold voltage of the drive transistor DT, allowing for simultaneous writing of the data voltage to the drive transistor DT and compensation of the threshold voltage. The gate electrode voltage of the drive transistor DT is then stored by the first capacitor Cst1 and the second capacitor Cst2. During the light emission phase, the fifth transistor T5 and the sixth transistor T6 are controlled to turn on in response to the light emission control signal EM. By turning off the first transistor T1 through the fourth transistor T4, a conductive path is formed between the first power line ELVDD and the second power line ELVSS. The drive transistor DT can then generate a drive current based on the voltages stored in the first capacitor Cst1 and the second capacitor Cst2, driving the light-emitting element D0 to emit light.

The present invention's technical solution involves using the first capacitor Cst1 and the second capacitor Cst2 together as storage capacitors in the pixel circuit. This increases the capacitance value of the storage capacitors, avoiding the constraints on the storage capacitor's capacitance value imposed by high PPI designs. This improves the stability of the gate electrode voltage of the drive transistor DT, thereby contributing to an improved display effect of the display panel.

The embodiments of this application further provide a method for manufacturing a display panel for producing a display panel in any of the embodiments described above. Figure 7 is a schematic flowchart of the method for manufacturing a display panel according to the embodiments of this application. Referring to Figure 7, the method specifically includes the following steps.

In S110, the base is provided.

In S120, an array circuit layer comprising multiple drive transistors is formed on the base.

In S130, the first electrode plate connected to the gate electrode of the drive transistor and the first electrode in the sub-pixel unit are formed on the side away from the base of the array circuit layer.

Figures 8 to 11 are schematic diagrams of the structure of a display panel formed in the steps of the manufacturing method for a display panel according to an embodiment of the present invention. Referring to Figure 8, a base 10 is provided, and an array circuit layer 20 is formed on the base 10, on which multiple pixel circuits are formed, and a drive transistor DT is provided within the pixel circuit. Exemplarily, the array circuit layer 20 comprises an active layer 210, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4. The gate electrode 220 of the drive transistor DT is located in the first metal layer M1, and the source electrode 230 and drain electrode 240 of the drive transistor DT are located in the third metal layer M3.

After forming the array circuit layer 20, the first electrode 40 and the first electrode plate 110 are formed on the side of the array circuit layer 20 that is separated from the base 10. For example, the first electrode 40 and the first electrode plate 110 may be provided on the side of the fourth metal layer M4 that is separated from the base 10, and the first electrode plate 110 may be connected to the gate electrode 220 of the drive transistor by the connection portion 260 in the fourth metal layer M4 and the connecting electrode 250 in the third metal layer M3.

In step S140, a pixel definition layer is formed covering the first electrode plate on the side of the first electrode plate that is separated from the base of the first electrode.

In S150, a second electrode plate is formed on the side away from the base of the pixel definition layer. The orthographic projection of the base of the first electrode plate and the orthographic projection of the base of the second electrode plate overlap at least partially, and the first and second electrode plates constitute the two electrodes of the first capacitor.

Referring to Figure 9, a pixel definition layer 30 is formed on the side of the first electrode 40 and the first electrode plate 110 that is separated from the base 10. Referring to Figure 10, a second electrode plate 120 is formed on the side of the pixel definition layer 30 that is separated from the base 10. As a result, the orthographic projection of the first electrode plate 110 on the base 10 and the orthographic projection of the second electrode plate 120 on the base 10 overlap at least partially, and the first electrode plate 110 and the second electrode plate 120 constitute the two electrodes of the first capacitor Cst1.

The present invention's embodiment allows for the formation of a first capacitor without adding extra film layers and corresponding mask plates to the display panel. This first capacitor can then be used as a storage capacitor in the pixel circuit, which is advantageous for increasing the capacitance value of the storage capacitor. This avoids the constraints on the storage capacitor's capacitance value imposed by high PPI designs. By increasing the storage capacitor's capacitance value, the stability of the gate electrode voltage of the drive transistor is improved, thereby enhancing the display effect of the display panel.

Referring to Figure 10, preferably, step S150 specifically includes forming an isolation portion 70 on the side of the pixel definition layer 30 that is separated from the base 10, such that the orthographic projection of the base 10 and the orthographic projection of the first electrode plate 110 on the base 10 at least partially overlap, and using at least a portion of the isolation portion 70 as the second electrode plate 120.

Preferably, after step S150, the process further includes forming an opening area 320 within the pixel definition layer 30 such that the pixel definition layer 30 consists of a pixel definition section 310 and an opening area 320 enclosed and closed by the pixel definition section 310, and the pixel definition section 310 covers the first electrode plate 110, thereby exposing the first electrode plate 110. Exemplarily, after forming the isolation section 70, the opening area 320 of the pixel definition layer 30 may be formed between the regions enclosed and closed by the isolation section 70, so that the isolation section 70 surrounds the opening area 320. In other embodiments, the opening area 320 of the pixel definition layer 30 may be formed first, and then step S150 may be performed, for example, by forming the isolation section 70 on the side of the pixel definition section 310 that is separated from the base 10 and surrounding the opening area 320.

Referring to Figure 11, the method further includes the following S160: The light-emitting layer 50 of the subpixel unit PX is formed in the aperture area 320 so as to be located on the side of the first electrode 40 away from the base 10, and the light-emitting layers 50 of adjacent subpixel units PX are isolated by the isolation portion 70. The second electrode 60 is formed on the side of the light-emitting layer 50 away from the base 10, and the second electrodes 60 of adjacent subpixel units PX are separated by the isolation portion 70. The first electrode 40, light-emitting layer 50, and second electrode 60 of the same subpixel unit PX are located in the same aperture area 320, and the light-emitting layers 50 and second electrodes 60 of different subpixel units PX are isolated by the isolation portion 70. This makes it easier to control each subpixel unit PX individually, and in the display panel manufacturing process, there is no need to use extra mask plates to isolate different subpixel units PX, which is advantageous in reducing the manufacturing cost of the display panel. Referring to Figure 4, after forming the second electrode 60, a first sealing layer 810 may be formed on the side of the second electrode 60 and the isolation portion 70 that is separated from the base 10, so as to cover the second electrode 60 and at least a portion of the isolation portion 70. Then, a second sealing layer 820 may be formed on the side of the first sealing layer 810 and the isolation portion 70 that is separated from the base 10, so as to cover the first sealing layer 810 and the isolation portion 70. Finally, a third sealing layer 830 may be formed on the side of the second sealing layer 820 that is separated from the base 10, so as to cover the second sealing layer 820. This completes the sealing process for the display panel, and the display panel shown in Figure 4 is obtained.

The embodiments of this application further provide a display device comprising a display panel as described in any of the above embodiments, and therefore possess a functional structure and effects corresponding to the display panel, which will not be described repeatedly here. The display device may be a mobile phone, or any electronic product with a display function, including but not limited to categories such as televisions, laptop computers, desktop displays, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, and touch-interactive terminals. The embodiments of this application are not particularly limited in this regard.

Claims (7)

Bass and,
An array circuit layer located on the aforementioned base and comprising multiple drive transistors,
A plurality of subpixel units comprising a pixel definition layer and a first electrode located on the side of the array circuit layer away from the base, and a light-emitting layer and a second electrode stacked on the side of the first electrode away from the base ,
The device comprises a first electrode plate provided in the same layer as the first electrode and covered by the pixel definition layer, and a second electrode plate located on the side of the pixel definition layer away from the base, wherein the orthographic projection of the first electrode plate on the base and the orthographic projection of the second electrode plate on the base at least partially overlap, and the first electrode plate is connected to a first capacitor connected to the gate electrode of the drive transistor,
The pixel definition layer is located on the side away from the base, the orthographic projection on the base at least partially overlaps with the orthographic projection of the first electrode plate at the base, at least a portion of which is also used as the second electrode plate, and includes an isolation portion used to isolate the light-emitting layer and the second electrode between adjacent subpixel units .
Display panel. The second plate and the second electrode comprise different materials.
The second electrode plate and the second electrode are provided in different layers.
The display panel according to claim 1. The light-emitting layer of the subpixel unit has a gap on the side surface of the isolation portion, and the second electrode is superimposed and connected to the isolation portion .
The isolation portion comprises a first sub-isolation portion, a second sub-isolation portion, and a third sub-isolation portion, which are sequentially stacked on the side of the pixel definition layer that is separated from the base.
Any one or at least two adjacent of the first sub-isolation section, the second sub-isolation section, and the third sub-isolation section is a conductive isolation section, and the orthographic projection of the conductive isolation section on the base and the orthographic projection of the first electrode plate on the base overlap at least partially, and at least a portion of the conductive isolation section is used as the second electrode plate and is configured to receive the power supply voltage.
Along the direction perpendicular to the base, the cross-section of the second sub-isolation portion is rectangular or trapezoidal, and if the cross-section of the second sub-isolation portion is trapezoidal, the lower base of the trapezoid is adjacent to the first sub-isolation portion, the upper base of the trapezoid is adjacent to the third sub-isolation portion, and the orthogonal projection of the third sub-isolation portion on the base covers the orthogonal projection of the first sub-isolation portion on the base and covers the orthogonal projection of the second sub-isolation portion on the base.
The display panel according to claim 1 . The pixel definition layer comprises a pixel definition section and an opening area enclosed and closed by the pixel definition section, which exposes the first electrode.
The pixel definition unit covers the first electrode plate, the second electrode plate is located on the side away from the base of the pixel definition unit, and the pixel definition unit isolates the first electrode plate and the second electrode plate, thereby insulating the first electrode plate and the second electrode plate.
The display panel according to claim 1. The pixel definition unit comprises at least one of a silicon oxide layer and a silicon nitride layer,
Along the direction perpendicular to the base, the thickness range of the pixel definition portion is 100 nm to 1000 nm.
The light-emitting layer is provided in the opening area ,
The second electrode is configured to receive a power supply voltage and contacts the second electrode plate,
The first electrode plate and the first electrode are insulated, and the first electrode plate is located between adjacent first electrodes.
The first electrode plate is provided surrounding the first electrode,
The second electrode plate is provided surrounding the aperture area of the pixel definition layer, and the overlapping region of the orthographic projection of the base of the first electrode plate and the orthographic projection of the base of the second electrode plate surrounds the aperture area.
The display panel according to claim 4 . The drive transistor further comprises a connecting electrode provided in the same layer as the source electrode or drain electrode, the connecting electrode being electrically connected to the gate electrode and the first electrode plate of the drive transistor, and the orthographic projection of the connecting electrode on the base and the orthographic projection of the gate electrode on the base of the drive transistor overlap at least partially.
The display panel according to claim 1. The array circuit layer further comprises multiple metal layers and a third electrode plate.
An insulating layer is provided between two adjacent metal layers, the plurality of metal layers comprises a first metal layer and a second metal layer, and the gate electrode of the drive transistor is located on the first metal layer.
The third plate is located in the second metal layer, and the orthographic projection of the third plate on the base and the orthographic projection of the gate electrode of the drive transistor on the base overlap at least partially, and the third plate and the gate electrode of the drive transistor constitute two plates of the second capacitor.
The display panel according to claim 1.