JP7850583B2 - power supply - Google Patents

Description

This disclosure relates to a power supply device.

Patent Document 1 describes a DAB (Dual Active Bridge) type DC-DC converter. A DAB type converter is a converter that enables bidirectional power transmission by controlling the phase between the drive pulse that drives the primary bridge circuit and the drive pulse that drives the secondary bridge circuit.

Japanese Patent Publication No. 2020-5429

In DAB converters, capacitors are connected to the input and output sections to eliminate ripple current. Depending on the application using the DAB converter, it may be necessary to quickly reduce the output voltage after operation stops. In this case, the energy stored in the output capacitor connected to the output section must be discharged quickly. Since DAB converters are capable of bidirectional power conversion, it is conceivable to reduce the output voltage by transferring the energy from the output capacitor to the input side. However, it may not be possible to discharge the voltage below the lower limit design value of the DAB converter's output voltage, or the input voltage may rise if the energy transferred to the input side is not consumed. Therefore, to quickly discharge the energy stored in the output capacitor, a discharge circuit may be required, leading to a more complex configuration, higher costs, and larger size.

This disclosure aims to provide a power supply device that can reduce the output voltage without increasing costs or size.

The power supply device of this disclosure includes: a first bridge circuit that includes a plurality of arms, each having a high-side switch element and a low-side switch element, and converts a DC voltage to an AC voltage for output; a transformer that includes a first winding and a second winding, to which the AC voltage output from the first bridge circuit is input, and the induced AC voltage is output from the second winding; a second bridge circuit that includes a plurality of arms, each having a high-side switch element and a low-side switch element, and converts the AC voltage output from the second winding of the transformer to a DC voltage for output to a load; and DC voltage input to the first bridge circuit The system comprises a first capacitor for smoothing the voltage, a second capacitor for smoothing the DC voltage output from the second bridge circuit, and a control unit that outputs a plurality of first drive pulses to the switch element of the first bridge circuit to cause the switch element of the first bridge circuit to switch, and outputs a plurality of second drive pulses to the switch element of the second bridge circuit to cause the switch element of the second bridge circuit to switch. The control unit controls the duty cycle of the second drive pulses to 2/3 of the standard value, thereby causing the switch element of the second bridge circuit to switch.

In the power supply device of this disclosure, the control unit stops the switching operation of the switch element of the first bridge circuit while it is controlling the duty cycle of the second drive pulse to 2/3 of the standard value.

In the power supply device of this disclosure, while the control unit is controlling the duty cycle of the second drive pulse to be 2/3 of the standard value, it also controls the duty cycle of the first drive pulse to be 2/3 of the standard value, thereby causing the switch element of the first bridge circuit to switch.

In the power supply device of this disclosure, the control unit controls the duty cycle of the second drive pulse to 2/3 of the standard value based on a control signal indicating the start of discharge of the second capacitor, thereby causing the switch element of the second bridge circuit to switch.

According to this disclosure, the output voltage can be reduced without increasing costs or size.

Figure 1 shows an example of the configuration of a power supply device according to an embodiment. Figure 2 shows an example of the configuration of the transformer section according to the embodiment. Figure 3 is a diagram illustrating the control method of a power supply device according to a comparative example. Figure 4 is a diagram illustrating the control method of the power supply device according to the embodiment. Figure 5 is a diagram illustrating the definition of the duty cycle according to this embodiment. Figure 6 is a diagram illustrating the control method of the power supply device when performing a discharge process according to the embodiment.

The embodiments of this disclosure will be described in detail below with reference to the attached drawings. Note that this embodiment does not limit the disclosure, and redundant descriptions will be omitted by using the same reference numerals for the same parts in the following embodiments.

[Embodiment]
An example of the configuration of a power supply device according to the embodiment will be explained using Figure 1. Figure 1 is a diagram showing an example of the configuration of a power supply device according to the embodiment.

The power supply unit 100 shown in Figure 1 is a DAB-type power supply unit according to this embodiment. The power supply unit 100 receives a primary voltage V1, which is a DC voltage output from the power supply 1 and smoothed by the smoothing capacitor 2. The DC voltage output from the power supply unit 100 is smoothed by the smoothing capacitor 3, and the secondary voltage V2 is input to the load 4.

The power supply unit 100 includes a first bridge circuit 10, a second bridge circuit 20, a reactor 31, a reactor 32, a reactor 33, a transformer unit 40, and a control unit 50.

The first bridge circuit 10 includes a first arm 10a, a second arm 10b, and a third arm 10c. The first bridge circuit 10 is a three-phase bridge circuit containing three arms. The first arm 10a is the U-phase arm. The second arm 10b is the V-phase arm. The third arm 10c is the W-phase arm. The phase difference between the first arm 10a and the second arm 10b is 120 degrees. The phase difference between the second arm 10b and the third arm 10c is 120 degrees. The phase difference between the third arm 10c and the first arm 10a is 120 degrees.

The first arm 10a includes switch element 11 and switch element 12. The second arm 10b includes switch element 13 and switch element 14. The third arm 10c includes switch element 15 and switch element 16.

Switch elements 11, 13, and 15 are high-side switch elements. Switch elements 12, 14, and 16 are low-side switch elements.

Switch elements 11 to 16 are, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), but are not limited to these. Switch elements 11 to 16 may also be silicon power devices, GaN power devices, SiC power devices, IGBTs (Insulated Gate Bipolar Transistors), etc.

Switch elements 11 through 16 have parasitic diodes (body diodes). A parasitic diode is a pn junction between the back gate and the source and drain of a MOSFET. The parasitic diode can be used as a freewheeling diode to dissipate transient back electromotive force when the transistor is off. In addition to the parasitic diodes, diode elements may be added in antiparallel between the drain and source of each transistor.

The source terminal of switch element 11 is electrically connected to the drain terminal of switch element 12. The drain terminal of switch element 11 is electrically connected to the drain terminal of switch element 13. The source terminal of switch element 12 is electrically connected to the source terminal of switch element 14.

The source terminal of switch element 13 is electrically connected to the drain terminal of switch element 14. The drain terminal of switch element 13 is electrically connected to the drain terminal of switch element 15. The source terminal of switch element 14 is electrically connected to the source terminal of switch element 16.

The source terminal of switch element 15 is electrically connected to the drain terminal of switch element 16.

The connection point N1 between the drain terminal of switch element 11, the drain terminal of switch element 13, and the drain terminal of switch element 15 is one input terminal of the power supply unit 100. The connection point N2 between the source terminal of switch element 12, the source terminal of switch element 14, and the source terminal of switch element 16 is the other input terminal of the power supply unit 100.

Connection point N1 is electrically connected to the high-potential side of the smoothing capacitor 2. Connection point N2 is electrically connected to the low-potential side of the smoothing capacitor 2. A DC voltage smoothed by the smoothing capacitor 2 is input between connection point N1 and connection point N2.

The connection point N3 between the source terminal of switch element 11 and the drain terminal of switch element 12 is the first output terminal of the first bridge circuit 10. The connection point N4 between the source terminal of switch element 13 and the drain terminal of switch element 14 is the second output terminal of the first bridge circuit 10. The connection point N5 between the source terminal of switch element 15 and the drain terminal of switch element 16 is the third output terminal of the first bridge circuit 10.

The second bridge circuit 20 includes a first arm 20a, a second arm 20b, and a third arm 20c. The second bridge circuit 20 is a three-phase bridge circuit containing three arms. The first arm 20a is the U-phase arm. The second arm 20b is the V-phase arm. The third arm 20c is the W-phase arm. The phase difference between the first arm 20a and the second arm 20b is 120 degrees. The phase difference between the second arm 20b and the third arm 20c is 120 degrees. The phase difference between the third arm 20c and the first arm 20a is 120 degrees.

The first arm 20a includes switch element 21 and switch element 22. The second arm 20b includes switch element 23 and switch element 24. The third arm 20c includes switch element 25 and switch element 26.

Switch elements 21, 23, and 25 are high-side switch elements. Switch elements 22, 24, and 26 are low-side switch elements.

Switch elements 21 to 26 are, for example, MOSFETs, but are not limited to these. Switch elements 21 to 26 may also be silicon power devices, GaN power devices, SiC power devices, IGBTs, etc.

Switch elements 21 through 26 have parasitic diodes (body diodes). A parasitic diode is a pn junction between the back gate and the source and drain of a MOSFET. The parasitic diode can be used as a freewheeling diode to dissipate transient back electromotive force when the transistor is off. In addition to the parasitic diodes, diode elements may be added in antiparallel between the drain and source of each transistor.

The source terminal of switch element 21 is electrically connected to the drain terminal of switch element 22. The drain terminal of switch element 21 is electrically connected to the drain terminal of switch element 23. The source terminal of switch element 22 is electrically connected to the source terminal of switch element 24.

The source terminal of switch element 23 is electrically connected to the drain terminal of switch element 24. The drain terminal of switch element 23 is electrically connected to the drain terminal of switch element 25. The source terminal of switch element 24 is electrically connected to the source terminal of switch element 26.

The source terminal of switch element 25 is electrically connected to the drain terminal of switch element 26.

The connection point N6 between the source terminal of switch element 21 and the drain terminal of switch element 22 is the first input terminal of the second bridge circuit 20. The connection point N7 between the source terminal of switch element 23 and the drain terminal of switch element 24 is the second input terminal of the second bridge circuit 20. The connection point N8 between the source terminal of switch element 25 and the drain terminal of switch element 26 is the third input terminal of the second bridge circuit 20.

The connection point N9 between the drain terminal of switch element 21, the drain terminal of switch element 23, and the drain terminal of switch element 25 is one output terminal of the power supply unit 100. The connection point N10 between the source terminal of switch element 22, the source terminal of switch element 24, and the source terminal of switch element 26 is the other output terminal of the power supply unit 100.

Connection point N9 is electrically connected to the high-potential side of the smoothing capacitor 3. Connection point N10 is electrically connected to the low-potential side of the smoothing capacitor 3. The secondary voltage V2 of the smoothing capacitor 3 becomes the output voltage of the power supply unit 100.

The high-potential side of the smoothing capacitor 3 is electrically connected to the high-potential side of the load 4. The low-potential side of the smoothing capacitor 3 is electrically connected to the low-potential side of the load 4.

One end of the reactor 31 is electrically connected to connection point N3. The other end of the reactor 31 is electrically connected to the transformer section 40.

One end of the reactor 32 is electrically connected to connection point N4. The other end of the reactor 32 is electrically connected to the transformer section 40.

One end of the reactor 33 is electrically connected to connection point N5. The other end of the reactor 33 is electrically connected to the transformer section 40.

The transformer section 40 includes a first winding, a second winding, and a core. The transformer section 40 is a type of transformer.

Figure 2 shows an example of the configuration of the transformer section according to the embodiment. As shown in Figure 2, the transformer section 40 includes transformer 40a, transformer 40b, and transformer 40c. In this embodiment, the transformer section 40 is a three-phase transformer. In the example shown in Figure 2, the transformer section 40 is a Y-connected three-phase transformer. Although Figure 2 shows the transformer section 40 as a Y-connected three-phase transformer, this disclosure is not limited to this. For example, the transformer section 40 may be a delta-connected three-phase transformer.

Transformer 40a includes a first winding 41a, a second winding 42a, a core 43a, a first terminal 44a, and a second terminal 45a. Transformer 40a is a U-phase transformer.

The first winding 41a is the primary winding. The second winding 42a is the secondary winding. Both the first winding 41a and the second winding 42a are wound around the core 43a. One end of the first winding 41a is electrically connected to the first terminal 44a. The first terminal 44a is electrically connected to the other end of the reactor 31. One end of the second winding 42a is electrically connected to the second terminal 45a. The second terminal 45a is electrically connected to connection point N6.

Transformer 40b includes a first winding 41b, a second winding 42b, a core 43b, a first terminal 44b, and a second terminal 45b. Transformer 40b is a V-phase transformer.

The first winding 41b is the primary winding. The second winding 42b is the secondary winding. Both the first winding 41b and the second winding 42b are wound around the core 43b. One end of the first winding 41b is electrically connected to the first terminal 44b. The first terminal 44b is electrically connected to the other end of the reactor 32. One end of the second winding 42b is electrically connected to the second terminal 45b. The second terminal 45b is electrically connected to connection point N7.

Transformer 40c includes a first winding 41c, a second winding 42c, a core 43c, a first terminal 44c, and a second terminal 45c. Transformer 40c is a W-phase transformer.

The first winding 41c is the primary winding. The second winding 42c is the secondary winding. Both the first winding 41c and the second winding 42c are wound around the core 43c. One end of the first winding 41c is electrically connected to the first terminal 44c. The first terminal 44c is electrically connected to the other end of the reactor 33. One end of the second winding 42c is electrically connected to the second terminal 45c. The second terminal 45c is electrically connected to connection point N8.

The other end of the first winding 41a, the other end of the first winding 41b, and the other end of the first winding 41c are electrically connected. The other end of the second winding 42a, the other end of the second winding 42b, and the other end of the second winding 42c are also electrically connected.

The control unit 50 controls the first bridge circuit 10 and the second bridge circuit 20. The control unit 50 includes, for example, an information processing device such as a CPU (Central Processing Unit) or an MPU (Micro Processing Unit), and a storage device such as a RAM (Random Access Memory) or ROM (Read Only Memory). The control unit 50 may be implemented using an integrated circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). The control unit 50 may also be implemented using a combination of hardware and software.

The control unit 50 switches the on and off states of switch element 16 from switch element 11 by outputting a primary drive pulse to the first bridge circuit 10. Specifically, the control unit 50 switches switch element 16 to the on state by outputting a high-level primary drive pulse from switch element 11 to the gate terminal of switch element 16. The control unit 50 switches switch element 16 to the off state by outputting a low-level primary drive pulse from switch element 11 to the gate terminal of switch element 16.

The control unit 50 switches the on and off states of switch element 26 from switch element 21 by outputting a secondary drive pulse to the second bridge circuit 20. Specifically, the control unit 50 switches switch element 26 to the ON state by outputting a high-level secondary drive pulse from switch element 21 to the gate terminal of switch element 26. The control unit 50 switches switch element 26 to the OFF state by outputting a low-level secondary drive pulse from switch element 21 to the gate terminal of switch element 26.

In this embodiment, the control unit 50 can discharge the energy stored in the smoothing capacitor 2 by, for example, controlling the duty cycle of the primary drive pulse. The control unit 50 can also discharge the energy stored in the smoothing capacitor 3 by, for example, controlling the duty cycle of the secondary drive pulse.

(Control method for comparative example)
Before describing this embodiment, the control method of a power supply device according to a comparative example will be described. Figure 3 is a diagram illustrating the control method of a power supply device according to a comparative example. The configuration of the power supply device according to the comparative example is the same as that of the power supply device 100 shown in Figure 1. In the following, for the sake of simplicity, the processing on the secondary side will be described as an example. The processing on the primary side is the same as the processing on the secondary side, so the explanation will be omitted.

Figure 3 shows the pulse patterns of each part of the secondary side and the output voltages of each phase. The switching frequency of the secondary side drive pulses input to each switch element is constant. The duty cycle of the secondary side drive pulses input to each part is 0.5. However, in the definition of this embodiment, the duty cycle is 1, as shown in equation (1) described later.

Waveform 111 shows the secondary drive pulse input to the gate terminal of switch element 21. Waveform 112 shows the secondary drive pulse input to the gate terminal of switch element 22. Waveform 113 shows the secondary drive pulse input to the gate terminal of switch element 23. Waveform 114 shows the secondary drive pulse input to the gate terminal of switch element 24. Waveform 115 shows the secondary drive pulse input to the gate terminal of switch element 25. Waveform 116 shows the secondary drive pulse input to the gate terminal of switch element 26. Waveform 117 shows the output voltage from the first arm 20a. Waveform 118 shows the output voltage from the second arm 20b. Waveform 119 shows the output voltage from the third arm 20c. Time t0 to time t6 constitutes one cycle of the control pattern of the power supply unit 100. The periods from time t0 to time t1, from time t1 to time t2, from time t2 to time t3, from time t3 to time t4, from time t4 to time t5, and from time t5 to time t6 are all of the same length.

Between time t0 and time t3, a low-level secondary drive pulse is input to the gate terminal of the switch element 21. The switch element 21 is in the off state between time t0 and time t3. Between time t3 and time t6, a high-level secondary drive pulse is input to the gate terminal of the switch element 21. The switch element 21 is in the on state between time t3 and time t6. Between time t6 and time t9, a low-level secondary drive pulse is input to the gate terminal of the switch element 21. The switch element 21 is in the off state between time t6 and time t9.

Between time t0 and time t3, a high-level secondary drive pulse is input to the gate terminal of the switch element 22. The switch element 22 is in the ON state between time t0 and time t3. Between time t3 and time t6, a low-level secondary drive pulse is input to the gate terminal of the switch element 22. The switch element 22 is in the OFF state between time t3 and time t6. Between time t6 and time t9, a high-level secondary drive pulse is input to the gate terminal of the switch element 22. The switch element 22 is in the ON state between time t6 and time t9.

From time t0 to time t1, a low-level secondary drive pulse is input to the gate terminal of switch element 23. Switch element 23 is in the off state from time t0 to time t1. From time t1 to time t4, a high-level secondary drive pulse is input to the gate terminal of switch element 23. Switch element 23 is in the on state from time t1 to time t4. From time t4 to time t7, a low-level secondary drive pulse is input to the gate terminal of switch element 23. Switch element 23 is in the off state from time t4 to time t7. From time t7 to time t9, a high-level secondary drive pulse is input to the gate terminal of switch element 23. Switch element 23 is in the on state from time t7 to time t9.

From time t0 to time t1, a high-level secondary drive pulse is input to the gate terminal of the switch element 24. The switch element 24 is ON from time t0 to time t1. From time t1 to time t4, a low-level secondary drive pulse is input to the gate terminal of the switch element 24. The switch element 24 is OFF from time t1 to time t4. From time t4 to time t7, a high-level secondary drive pulse is input to the gate terminal of the switch element 24. The switch element 24 is ON from time t4 to time t7. From time t7 to time t9, a low-level secondary drive pulse is input to the gate terminal of the switch element 24. The switch element 24 is OFF from time t7 to time t9.

Between time t0 and time t2, a high-level secondary drive pulse is input to the gate terminal of the switch element 25. The switch element 25 is in the ON state between time t0 and time t2. Between time t2 and time t5, a low-level secondary drive pulse is input to the gate terminal of the switch element 25. The switch element 25 is in the OFF state between time t2 and time t5. Between time t5 and time t8, a high-level secondary drive pulse is input to the gate terminal of the switch element 25. The switch element 25 is in the ON state between time t5 and time t8. Between time t8 and time t9, a low-level secondary drive pulse is input to the gate terminal of the switch element 25. The switch element 25 is in the OFF state between time t8 and time t9.

Between time t0 and time t2, a low-level secondary drive pulse is input to the gate terminal of the switch element 26. The switch element 26 is in the off state between time t0 and time t2. Between time t2 and time t5, a high-level secondary drive pulse is input to the gate terminal of the switch element 26. The switch element 26 is in the on state between time t2 and time t5. Between time t5 and time t8, a low-level secondary drive pulse is input to the gate terminal of the switch element 26. The switch element 26 is in the off state between time t5 and time t8. Between time t8 and time t9, a high-level secondary drive pulse is input to the gate terminal of the switch element 26. The switch element 26 is in the on state between time t8 and time t9.

As shown in waveforms 111 to 116, in the control method according to the comparative example, there is no pattern in which all of the high-side switch elements, switch elements 21, 23, and 25, are simultaneously on or off. Similarly, in the control method according to the comparative example, there is no pattern in which all of the low-side switch elements, switch elements 22, 24, and 26, are simultaneously on or off.

(Control method of the embodiment)
Next, a control method according to the embodiment will be described. For example, the control unit 50 provides a pattern in which all of the high-side switch elements, such as switch element 21, switch element 23, and switch element 25, are simultaneously turned on or off in order to discharge the energy stored in the smoothing capacitor 3 shown in Figure 1, and controls the duty cycle to a predetermined value.

The control method of the power supply device according to the embodiment will be explained using Figure 4. Figure 4 is a diagram illustrating the control method of the power supply device according to the embodiment.

Waveform 121 shows the secondary drive pulse input to the gate terminal of switch element 21. Waveform 122 shows the secondary drive pulse input to the gate terminal of switch element 22. Waveform 123 shows the pulse input to the secondary drive gate terminal of switch element 23. Waveform 124 shows the secondary drive pulse input to the gate terminal of switch element 24. Waveform 125 shows the secondary drive pulse input to the gate terminal of switch element 25. Waveform 126 shows the secondary drive pulse input to the gate terminal of switch element 26. Waveform 127 shows the output voltage from the first arm 20a. Waveform 128 shows the output voltage from the second arm 20b. Waveform 129 shows the output voltage from the third arm 20c.

As shown in Figure 4, waveforms 121 to 126 have additional pulse patterns, specifically additional patterns P1 to P9, added to waveforms 111 to 116 shown in Figure 3.

The additional pattern P1 is an additional pattern added between time t0 and time t1. The additional pattern P1 is a pulse pattern in which a low-level secondary drive pulse is input to the gate terminal of each switch element on the high-side, and a high-level secondary drive pulse is input to the gate terminal of each switch element on the low-side. That is, in the additional pattern P1, all switch elements 21, 23, and 25 are in the off state, and all switch elements 22, 24, and 26 are in the on state. While the additional pattern P1 is shown as being added in the middle of the interval between time t0 and time t1, this disclosure is not limited thereto.

The additional pattern P2 is an additional pattern added between time t1 and time t2. The additional pattern P2 is a pulse pattern in which a high-level secondary drive pulse is input to the gate terminal of each switch element on the high-side, and a low-level secondary drive pulse is input to the gate terminal of each switch element on the low-side. That is, in the additional pattern P2, all switch elements 21, 23, and 25 are in the ON state, and all switch elements 22, 24, and 26 are in the OFF state. While the additional pattern P2 is shown as being added in the middle between time t1 and time t2, this disclosure is not limited thereto.

Additional pattern P3 is an additional pattern added between time t2 and time t3. Since the pulse pattern of additional pattern P3 is the same as the pulse pattern of additional pattern P1, its explanation is omitted.

Additional pattern P4 is an additional pattern added between time t3 and time t4. Since the pulse pattern of additional pattern P4 is the same as the pulse pattern of additional pattern P2, its explanation is omitted.

Additional pattern P5 is an additional pattern added between time t4 and time t5. Since the pulse pattern of additional pattern P5 is the same as the pulse pattern of additional pattern P1, its explanation is omitted.

Additional pattern P6 is an additional pattern added between time t5 and time t6. Since the pulse pattern of additional pattern P6 is the same as the pulse pattern of additional pattern P2, its explanation is omitted.

Additional pattern P7 is an additional pattern added between time t6 and time t7. Since the pulse pattern of additional pattern P7 is the same as the pulse pattern of additional pattern P1, its explanation is omitted.

Additional pattern P8 is an additional pattern added between time t7 and time t8. Since the pulse pattern of additional pattern P8 is the same as the pulse pattern of additional pattern P2, its explanation is omitted.

Additional pattern P9 is an additional pattern added between time t8 and time t9. Since the pulse pattern of additional pattern P9 is the same as the pulse pattern of additional pattern P1, its explanation is omitted.

Waveforms 121 to 126 each have a smaller duty cycle than waveforms 111 to 116 shown in Figure 4.

Figure 5 is a diagram illustrating the definition of the duty cycle according to the embodiment. In Figure 5, the horizontal axis represents time, and the vertical axis represents the signal level input to the gate terminal of the switch element. Period T is the duration of one control cycle. Duty cycle interval Tduty is the duration of the additional pattern section. In this embodiment, the duty cycle D is defined as follows.
D=(Period T/2-Duty ratio interval Tduty)/(Period T/2)...(1)

In this embodiment, as shown in equation (1), the duty cycle D decreases as the duty cycle interval Tduty lengthens. Furthermore, the duty cycle D is 1 (standard value) when the duty cycle interval Tduty is 0.

As shown in Figures 4 and 5, in this embodiment, the control unit 50 can control the duty cycle by adding an additional pattern to the secondary drive pulse.

(Discharge control process)
In this embodiment, when the control unit 50 discharges the energy stored in the smoothing capacitor 3 shown in Figure 1, it controls the duty cycle of the second drive pulse output to the second bridge circuit 20 to 2/3 of the standard value. In the following description, the duty cycle of the second drive pulse is controlled to 2/3 of the standard value, but the disclosure is not limited thereto. In this disclosure, the control unit 50 may control the duty cycle of the second drive pulse within the range of 2/3 ± X (where X is an arbitrary coefficient). For example, if the standard value of the duty cycle of the second drive pulse is 1, the control unit 50 may control the duty cycle of the second drive pulse to 0.65 or the like.

Figure 6 is a diagram illustrating the control method of the power supply device when performing discharge processing according to the embodiment.

Waveform 131 shows the secondary drive pulse input to the gate terminal of switch element 21. Waveform 132 shows the secondary drive pulse input to the gate terminal of switch element 22. Waveform 133 shows the pulse input to the secondary drive gate terminal of switch element 23. Waveform 134 shows the secondary drive pulse input to the gate terminal of switch element 24. Waveform 135 shows the secondary drive pulse input to the gate terminal of switch element 25. Waveform 136 shows the secondary drive pulse input to the gate terminal of switch element 26. Waveform 137 shows the output voltage from the first arm 20a. Waveform 138 shows the output voltage from the second arm 20b. Waveform 139 shows the output voltage from the third arm 20c.

As shown in Figure 6, waveforms 131 to 136 have additional pulse patterns, specifically additional patterns P11 to P19, added to waveforms 111 to 116 shown in Figure 3.

The additional pattern P11 is an additional pattern added between time t0 and time t1. The additional pattern P11 is a pulse pattern in which a low-level secondary drive pulse is input to the gate terminal of each switch element on the high-side, and a high-level secondary drive pulse is input to the gate terminal of each switch element on the low-side. That is, in the additional pattern P11, all switch elements 21, 23, and 25 are in the off state, and all switch elements 22, 24, and 26 are in the on state.

Additional pattern P12 is an additional pattern added between time t1 and time t2. Additional pattern P12 is a pulse pattern in which a high-level secondary drive pulse is input to the gate terminal of each switch element on the high-side, and a low-level secondary drive pulse is input to the gate terminal of each switch element on the low-side. That is, in additional pattern P2, switch elements 21, 23, and 25 are all in the ON state, and switch elements 22, 24, and 26 are all in the OFF state.

Additional pattern P13 is an additional pattern added between time t2 and time t3. Since the pulse pattern of additional pattern P13 is the same as the pulse pattern of additional pattern P11, its explanation is omitted.

Additional pattern P14 is an additional pattern added between time t3 and time t4. Since the pulse pattern of additional pattern P14 is the same as the pulse pattern of additional pattern P12, its explanation is omitted.

Additional pattern P15 is an additional pattern added between time t4 and time t5. Since the pulse pattern of additional pattern P15 is the same as the pulse pattern of additional pattern P11, its explanation is omitted.

Additional pattern P16 is an additional pattern added between time t5 and time t6. Since the pulse pattern of additional pattern P16 is the same as the pulse pattern of additional pattern P12, its explanation is omitted.

Additional pattern P17 is an additional pattern added between time t6 and time t7. Since the pulse pattern of additional pattern P17 is the same as the pulse pattern of additional pattern P11, its explanation is omitted.

Additional pattern P18 is an additional pattern added between time t7 and time t8. Since the pulse pattern of additional pattern P18 is the same as the pulse pattern of additional pattern P12, its explanation is omitted.

Additional pattern P19 is an additional pattern added between time t8 and time t9. Since the pulse pattern of additional pattern P19 is the same as the pulse pattern of additional pattern P11, its explanation is omitted.

In the example shown in Figure 6, the control unit 50 controls the duty cycle of switch element 21 to switch element 26 to 2/3 of the standard value.

As shown in waveforms 137, 138, and 139, the output voltages from the first arm 20a, the second arm 20b, and the third arm 20c are 0V. That is, the control unit 50 can control the switch element 26 from switch element 21 to switch element 26 to 2/3 of the standard value, thereby preventing voltage output from the first arm 20a, the second arm 20b, and the third arm 20c. This prevents energy from the second bridge circuit 20 from being transmitted to the first bridge circuit 10.

The control unit 50 switches switch element 21 to switch element 26 when the energy from the second bridge circuit 20 is not transmitted to the first bridge circuit 10. This allows the control unit 50 to discharge the energy stored in the smoothing capacitor 3 through the switching loss between switch element 21 and switch element 26, without transmitting energy from the second bridge circuit 20 to the first bridge circuit 10.

The control unit 50, for example, when the power supply unit 100 stops operating, performs the operation described in Figure 6 to discharge the energy stored in the smoothing capacitor 3. At this time, the control unit 50 starts the discharge process of the smoothing capacitor 3 based on a control signal indicating the start of discharge of the smoothing capacitor 3. For example, the control signal indicating the start of discharge of the smoothing capacitor 3 could be a control signal indicating the cessation of the DC voltage output operation to the load 4. For example, the control signal indicating the start of discharge of the smoothing capacitor 3 could also be a control signal indicating the cessation of operation of the power supply unit 100.

Furthermore, when another power supply is connected in parallel to power supply unit 100, it is conceivable that energy may be stored in the smoothing capacitor 3 as the output voltage from the other power supply flows into power supply unit 100. Therefore, the control signal indicating the start of discharge of the smoothing capacitor 3 may also be a control signal indicating the shutdown of the other power supply. In this case, power supply unit 100 may also be equipped with a voltage sensor that detects the flow of output voltage from the other power supply into the smoothing capacitor 3. The control unit 50 may then, for example, start the discharge process of the smoothing capacitor 3 when the voltage sensor detects the output voltage from the other power supply and detects that the flow of output voltage from the other power supply has stopped.

Furthermore, the control signal indicating the start of discharge of the smoothing capacitor 3 is not limited to the above and may be any other control signal.

The control unit 50 may, for example, perform the operation described in Figure 6 when starting the operation of the power supply unit 100 to discharge the energy stored in the smoothing capacitor 3. This allows the control unit 50 to discharge any residual charge remaining in the smoothing capacitor 3. The control unit 50 may, for example, start the discharge process of the smoothing capacitor 3 based on a control signal indicating the start of the power supply unit's operation. The control unit 50 may also, for example, start the discharge process if the residual charge stored in the smoothing capacitor 3, as measured by a residual charge measuring device (not shown), exceeds a predetermined level.

The control unit 50 preferably stops the switching operation of the switch elements 11 to 16 of the first bridge circuit 10 while, for example, the energy stored in the smoothing capacitor 3 is being discharged.

Furthermore, in this embodiment, the control unit 50 may control the duty cycle of the primary drive pulse of the switch element of the first bridge circuit 10 to 2/3 to switch element 11 to switch element 16. This allows the control unit 50 to discharge the energy stored in the smoothing capacitor 2 through the switching loss between switch element 11 and switch element 16, without transferring energy from the first bridge circuit 10 to the second bridge circuit 20.

As described above, this embodiment allows the energy stored in the smoothing capacitor 3 on the second bridge circuit 20 to be discharged without adding an external discharge circuit or the like. This makes it possible to discharge the energy stored in the output capacitor without increasing the cost and size of the DAB converter configuration.

The embodiments of this disclosure have been described above, but the disclosure is not limited by the content of these embodiments. Furthermore, the aforementioned components include those that are readily conceivable to those skilled in the art, those that are substantially identical, and those that fall within the so-called equivalent range. Moreover, the aforementioned components can be combined as appropriate. Furthermore, various omissions, substitutions, or modifications of the components can be made without departing from the spirit of the embodiments described above.

1 Power supply 2,3 Smoothing capacitor 4 Load 10 First bridge circuit 20 Second bridge circuit 10a,20a First arm 10b,20b Second arm 10c,20c Third arm 11,12,13,14,15,16,21,22,23,24,25,26 Switch element 31,32,33 Reactor 40 Transformer section 40a,40b,40c Transformer 41a,41b,41c First winding 42a,42b,42c Second winding 43a,43b,43c Core 44a,44b,44c First terminal 45a,45b,45c Second terminal 50 Control unit 100 Power supply unit

Claims (4)

A first bridge circuit includes multiple arms, each having a high-side switch element and a low-side switch element, which converts a DC voltage to an AC voltage and outputs it.
A transformer comprising a first winding and a second winding, wherein an AC voltage output from the first bridge circuit is input to the first winding, and the induced AC voltage is output from the second winding,
A second bridge circuit includes a plurality of arms, each having a high-side switch element and a low-side switch element, which converts the AC voltage output from the second winding of the transformer into a DC voltage and outputs it to the load.
A first capacitor smooths the DC voltage input to the first bridge circuit,
A second capacitor smooths the DC voltage output from the second bridge circuit,
A control unit that outputs a plurality of first drive pulses to the switch element of the first bridge circuit to cause the switch element of the first bridge circuit to switch, and outputs a plurality of second drive pulses to the switch element of the second bridge circuit to cause the switch element of the second bridge circuit to switch,
Equipped with,
When the duty cycle of the second drive pulse is D, the control period for one cycle of the switch element is period T, and the period of the additional pattern added to the second drive pulse is duty cycle interval Tduty, the duty cycle of the second drive pulse is defined by the following equation (1):
D=(cycle T/2-duty ratio interval Tduty/(cycle T/2))...(1)
If the duty cycle of the second drive pulse when the duty cycle interval Tduty is 0 is taken as the standard value,
The control unit,
The duty cycle of the second drive pulse is controlled to be 2/3 of the standard value, causing the switch element of the second bridge circuit to switch.
power supply. While the control unit is controlling the duty cycle of the second drive pulse to 2/3 of the standard value, it stops the switching operation of the switch element of the first bridge circuit.
The power supply device according to claim 1. While the control unit is controlling the duty cycle of the second drive pulse to be 2/3 of the standard value, it also controls the duty cycle of the first drive pulse to be 2/3 of the standard value, thereby causing the switch element of the first bridge circuit to switch.
The power supply device according to claim 1 or 2. The control unit, based on a control signal indicating the start of discharge of the second capacitor, controls the duty cycle of the second drive pulse to 2/3 of the standard value, thereby causing the switch element of the second bridge circuit to switch.
A power supply device according to any one of claims 1 to 3.