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JPS5516451A - Method of manufacturing semiconductor device - Google Patents
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JPS5516451A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JPS5516451A
JPS5516451A JP8945578A JP8945578A JPS5516451A JP S5516451 A JPS5516451 A JP S5516451A JP 8945578 A JP8945578 A JP 8945578A JP 8945578 A JP8945578 A JP 8945578A JP S5516451 A JPS5516451 A JP S5516451A
Authority
JP
Japan
Prior art keywords
recess
grooves
pellet
stem
voids
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8945578A
Other languages
Japanese (ja)
Inventor
Hitoshi Ishimori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8945578A priority Critical patent/JPS5516451A/en
Publication of JPS5516451A publication Critical patent/JPS5516451A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07311—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE: To reduce the amount of the voids appeared in the solder layer by forming the recess on the soldering surface of the stem in advance and then forming the grooves extending outwards in the radial direction and connecting to the recess at plural positions in the circumferential direction.
CONSTITUTION: On a stem 2 formed is a recess 2b which has such arrangement as capable of holding hold a pellet 4 without being fallen down within it. For example, the recess 2 has the diameter a little shorter than the diagonal line length of the pellet 4 and the protruded portion forming a semi-spherical surface 2a at its bottom. In addition formed are grooves 2c extending outwards in the radial direction and connecting to the recess 2b at plural positions in the circumferential direction, for example, at 4 positions corresponding to each side of the pellet 4. With the recess 2b and grooves 2c formed on the stem 2, the voids often produced during in the soldering process can easily run away through the recess 2b and grooves 2c. This reduces the amount of the voids appeared in the solder layer significantly.
COPYRIGHT: (C)1980,JPO&Japio
JP8945578A 1978-07-24 1978-07-24 Method of manufacturing semiconductor device Pending JPS5516451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8945578A JPS5516451A (en) 1978-07-24 1978-07-24 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8945578A JPS5516451A (en) 1978-07-24 1978-07-24 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPS5516451A true JPS5516451A (en) 1980-02-05

Family

ID=13971162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8945578A Pending JPS5516451A (en) 1978-07-24 1978-07-24 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPS5516451A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61106493A (en) * 1984-10-31 1986-05-24 Nec Corp Molecular beam epitaxial growing method
JPS6230317A (en) * 1985-04-02 1987-02-09 Fujitsu Ltd Method and apparatus for growing semiconductor crystal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61106493A (en) * 1984-10-31 1986-05-24 Nec Corp Molecular beam epitaxial growing method
JPS6230317A (en) * 1985-04-02 1987-02-09 Fujitsu Ltd Method and apparatus for growing semiconductor crystal

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