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JPS5578263A - Semiconductor integrated circuit - Google Patents
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JPS5578263A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5578263A
JPS5578263A JP15254278A JP15254278A JPS5578263A JP S5578263 A JPS5578263 A JP S5578263A JP 15254278 A JP15254278 A JP 15254278A JP 15254278 A JP15254278 A JP 15254278A JP S5578263 A JPS5578263 A JP S5578263A
Authority
JP
Japan
Prior art keywords
test mode
circuit
level
signal
exceeds
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15254278A
Other languages
Japanese (ja)
Other versions
JPS6219709B2 (en
Inventor
Tsutomu Iima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15254278A priority Critical patent/JPS5578263A/en
Publication of JPS5578263A publication Critical patent/JPS5578263A/en
Publication of JPS6219709B2 publication Critical patent/JPS6219709B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To enable to set the mode into test mode, by giving signal to the test mode generation circuit from the terminal which can commonly be used as the input terminal for normal input logical operation circuit. CONSTITUTION:The test mode generation circuit 13 and the inverter 14 for output inversion are connected to the terminal Common for use with normal input logic and test mode generation. The said circuit 13 is connected with FETMT for drive and FETML for load in series. When the signal fed to Common exceeds the logical amplitude range (O-+Vcc) and exceeds the threshold value of FETM7, FETM7 thrns on and a signal is produced to the output of the circuit 13 by taking the level determined with the conduction resistance ratio of the high resistor load ML as ''0'' level. If the output of the inverter 14 in-phase with the signal of Common exceeds the threshold of the drive transistor for NOR gates 15, 16, T1, T2 are at ''0'' level to obtain the test mode independently of the level of normal input logic circuit.
JP15254278A 1978-12-08 1978-12-08 Semiconductor integrated circuit Granted JPS5578263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15254278A JPS5578263A (en) 1978-12-08 1978-12-08 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15254278A JPS5578263A (en) 1978-12-08 1978-12-08 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS5578263A true JPS5578263A (en) 1980-06-12
JPS6219709B2 JPS6219709B2 (en) 1987-04-30

Family

ID=15542723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15254278A Granted JPS5578263A (en) 1978-12-08 1978-12-08 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5578263A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4612499A (en) * 1983-11-07 1986-09-16 Texas Instruments Incorporated Test input demultiplexing circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5396740A (en) * 1977-02-04 1978-08-24 Hitachi Ltd Test system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5396740A (en) * 1977-02-04 1978-08-24 Hitachi Ltd Test system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4612499A (en) * 1983-11-07 1986-09-16 Texas Instruments Incorporated Test input demultiplexing circuit

Also Published As

Publication number Publication date
JPS6219709B2 (en) 1987-04-30

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