JPS5710249A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5710249A JPS5710249A JP8473280A JP8473280A JPS5710249A JP S5710249 A JPS5710249 A JP S5710249A JP 8473280 A JP8473280 A JP 8473280A JP 8473280 A JP8473280 A JP 8473280A JP S5710249 A JPS5710249 A JP S5710249A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- resist
- layer
- insulating film
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000010410 layer Substances 0.000 abstract 7
- 239000002184 metal Substances 0.000 abstract 4
- 238000000034 method Methods 0.000 abstract 3
- 239000011229 interlayer Substances 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To facilitate the formation work, by remaining a resist which is used as an etching mask for a metal film, forming an insulating film between wiring patterns by a lift off method, thereafter providing an upper layer wiring via the interlayer insulating film, and flattening a multi-layer wiring structure. CONSTITUTION:The metal film 12 of Al and the like is formed on the entire surface of a substrate 11. The metal film 12 is etched by using a resist pattern 13, and a first wiring layer 14 is formed. With said resist 13 being remained, the insulating film 15 is formed to the thickness which is the same as that of the wiring 14 by the sputtering method and the like. Thereafter, the resist 13 is removed, and the insulating film 15 on the resist is lifted off. After a first insulating layer (interlayer film) 18 has been formed, a metal film 19 is etched by using a resist 20, and a second wiring layer 21 is obtained. In this method, the difference in steps due to the wiring layer can be almost entirely removed, and the breaking of the upper wiring and the short circuit between the wiring can be prevented. By repeating the lift off method, the more number of layers can be provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8473280A JPS5710249A (en) | 1980-06-23 | 1980-06-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8473280A JPS5710249A (en) | 1980-06-23 | 1980-06-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5710249A true JPS5710249A (en) | 1982-01-19 |
Family
ID=13838859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8473280A Pending JPS5710249A (en) | 1980-06-23 | 1980-06-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5710249A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61241989A (en) * | 1985-04-19 | 1986-10-28 | Agency Of Ind Science & Technol | Manufacture of superconducting line |
| JPS61244078A (en) * | 1985-04-22 | 1986-10-30 | Agency Of Ind Science & Technol | Manufacture of superconducting lines |
| US5455183A (en) * | 1994-01-03 | 1995-10-03 | Honeywell Inc. | Method for fabricating a FET having a dielectrically isolated gate connect |
-
1980
- 1980-06-23 JP JP8473280A patent/JPS5710249A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61241989A (en) * | 1985-04-19 | 1986-10-28 | Agency Of Ind Science & Technol | Manufacture of superconducting line |
| JPS61244078A (en) * | 1985-04-22 | 1986-10-30 | Agency Of Ind Science & Technol | Manufacture of superconducting lines |
| US5455183A (en) * | 1994-01-03 | 1995-10-03 | Honeywell Inc. | Method for fabricating a FET having a dielectrically isolated gate connect |
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