JPS5810016B2 - Kaidan Hashingou Hatsuseiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a staircase wave signal generator. There are eight color bar signals (including black) in the NTSC system, and there are also eight luminance signals, that is, staircase wave signals.

In order to measure the linearity of a video amplifier of a monitor receiver or the like using this staircase wave signal, the number of steps is small and measurement is difficult.

On the other hand, it is difficult to measure horizontal sag because the pulse width of the staircase wave signal is narrow.

Therefore, it is necessary to arbitrarily change the number of steps of the staircase wave signal using a simple circuit configuration.

Therefore, an object of the present invention is to provide a staircase wave signal generator that can adjust the number of steps of a staircase wave signal with a simple circuit configuration.

FIG. 1 is a block diagram of an embodiment of the staircase wave signal generator of the present invention.

In the figure, a phase comparator (hereinafter referred to as PD) 1, a low pass filter/DC amplifier (hereinafter referred to as LPF-DCAMP) 2, a voltage controlled oscillator (hereinafter referred to as vCO) 3, and a programmable counter circuit 4 form a closed loop. to configure a phase-locked loop circuit.

The register circuit 5 is composed of a flip-flop circuit, etc., and a specific example thereof is shown in FIG.

The staircase wave generation circuit 6 obtains a staircase wave by adding signals using a resistor or the like, and a concrete example thereof is shown in FIG. 3, and its output is given to the AGC circuit 1.

In Figure 2, 8 is a NOT circuit, 9 is a NAND circuit,
10 to 13 are flip-flop circuits at J-.

In FIG. 3, 14-17 are transistors, 18-2
1 is a resistor, and 22 to 24 are diodes.

FIG. 4 is a time chart for explaining the operation of FIGS. 1 to 3, and waveform a=e is the waveform of signal a=e in FIGS. 1 to 3.

In operation, first, the programmable counter circuit 4
is set to u8v to form an octal counter circuit.

A horizontal drive signal (hereinafter referred to as HD) a is supplied to PDl, J- of the register circuit 5, and reset terminals R of flip-flop circuits 10 to 13.

The output of the counter circuit 4 is supplied to PDl, and the phase is compared with the HD, the output is supplied to the VCO 3 via the LPF-DCAMP 2, and the oscillation output of the VCO 3 is supplied to the counter circuit 4.

If there is no phase difference between the two inputs of PDl within this closed loop.

In other words, when 1/8 of the oscillation frequency of VCO3 is locked to HD, the oscillation output of VCO3 will be approximately 120.8 times that of HD.
84KHz waves are generated.

The output of this VCO3 is NANDed via NOT circuit 8.
A circuit 9 gates the horizontal blanking signal (hereinafter referred to as H-BLK) C.

The output signal d of this NAND circuit 9 is supplied to clock terminals C of flip-flop circuits (hereinafter referred to as FF) 10 to 13 at J-.

The J terminal of FF10 is raised to high level,
The terminals of FF10 to 13 have their respective outputs 21 and 22.
', 23. ...Connected to 2n.

Also, the J terminal of FF11 to 13 is the Q output 21 of the previous stage FF.
22, . . . 2n-1.

Since FFs 10 to 13 have been reset by the HD, their outputs are high, the J terminals of FF 10 are high, and the J terminals of FFs 11 to 13 are low.

When the clock d is supplied, either the Q output e of the FF 10 is inverted and becomes high, or the outputs of the FFs 11 to 13 are not inverted because the J terminal is low.

At this time, the terminal of FF10 becomes low.

When the Q output e of FF10 becomes high, the J terminal of FF11 also becomes high.

When the next clock d is supplied, the Q output f of the FF 11 is inverted and becomes high, and since the terminal of the FF 10 is low, the Q output e is not inverted.

In this way, FF10 to 13 are sequentially brought to high level by clock d, reset by HDa, and FF10 to FF13 are reset by HDa.
13 has a waveform as shown in FIG. 4e-.

The outputs of these FFs 10 to 13 are supplied to the staircase wave generation circuit 6 shown in FIG.

That is, the Q output e of the FF 10 is supplied to the base of the transistor 14.

During the period when the signal e is high, the transistor 14 is turned on.
The collector is at ground potential.

Furthermore, during the period when the signal e is low, the transistor 14 is OFF.
, and the collector potential is about to become 10B1.

Here, since the voltage of 10B2 is lower than the voltage of 10B1,
The diode 22 is turned on, and the collector of the transistor 14 is fixed at a potential approximately 0.6 μ higher than 1 B2.

As described above, the switch 14 performs a switching operation to invert the output.

Similarly, the transistors 15 and 16 also perform switching operations in response to the signals f to k, and when the transistors 15 and 16 are turned off, the potential at their collectors is the same as that of the diodes 23 and 24.
N and becomes constant.

These collector outputs are added by resistors 18 to 20 and resistor 21 and supplied to the base of transistor 17.

As a result, a staircase wave signal e is generated from the emitter of the transistor 17.

In this way, a staircase wave signal can be obtained, but depending on the settings of the programmable counter circuit 4 described above,
The number of circuits of the register circuit 5 composed of F10 to F13 and the like and the number of switching circuits of the staircase wave generation circuit 6 for adding by resistance change.

There is no problem depending on the number of circuits in the resistor circuit 5, but depending on the number of switching circuits in the staircase wave generation circuit 6, the resistance may be 18 to 2.
The 1st order relationship is broken and the amplitude of the staircase wave signal e changes.

The AGC circuit 7
The amplitude of the output signal e is kept constant.

In this way, a staircase wave signal having an arbitrary number of steps within one horizontal period can be generated by setting the programmable counter circuit 4.

As described above, according to the staircase wave signal generator of the present invention,
A staircase wave signal with an arbitrary number of steps can be generated within a fixed period with a simple circuit configuration.

As a result, when measuring the linearity of a video amplifier, etc., a signal close to a triangular wave signal can be obtained simply by increasing the number of programmable counter settings.

Conversely, when measuring horizontal sag, a signal with a wide pulse width can be obtained by simply increasing the number of programmable counter settings.

In this way, there is an advantage that appropriate signals can be easily generated depending on various types of measurements.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the staircase wave generator of the present invention, FIG. 2 is a specific circuit example of the register circuit used in FIG. 1, and FIG. 3 is a block diagram of the staircase wave generator circuit used in FIG. 1. A specific circuit example, FIG. 4 is a time chart of signals of each part of FIGS. 1 to 3. 1... Phase comparator, 2... LPF-D
CAMP, 3... Voltage controlled oscillator, 4...
...Programmable counter, 5...Register circuit, 6...Staircase wave generation circuit, 7...
・AGC circuit.

Claims (1)

[Claims] 1. A reference signal generation circuit that generates a reference signal, a phase-locked loop circuit that generates a clock signal with a frequency that is an arbitrary integral multiple of the frequency of this reference signal, and a circuit that counts and stores the clock signal and resets it with the reference signal. a staircase signal generating circuit that generates a sawtooth staircase signal by digital-to-analog conversion of the output of the register, and an AGC circuit that maintains the amplitude of the sawtooth staircase signal constant. wave signal generator.