JPS5810036B2 - Multi-frequency signal transmission method - Google Patents
Multi-frequency signal transmission methodInfo
- Publication number
- JPS5810036B2 JPS5810036B2 JP11575878A JP11575878A JPS5810036B2 JP S5810036 B2 JPS5810036 B2 JP S5810036B2 JP 11575878 A JP11575878 A JP 11575878A JP 11575878 A JP11575878 A JP 11575878A JP S5810036 B2 JPS5810036 B2 JP S5810036B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency signal
- frequency
- time slot
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/30—Signalling arrangements; Manipulation of signalling currents
- H04Q1/44—Signalling arrangements; Manipulation of signalling currents using alternate current
- H04Q1/444—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
- H04Q1/45—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling
- H04Q1/457—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals
- H04Q1/4575—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals which are transmitted in digital form
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
Description
【発明の詳細な説明】
本発明は、複数のディジクル化された単周波信号からデ
ィジクル化多周波信号を作成し、伝送路に送出する多周
波信号送出方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-frequency signal sending method for creating a digitized multi-frequency signal from a plurality of digitized single-frequency signals and sending it out to a transmission path.
第1図は従来性なわれてきたディジタル化多周波信号送
出方式を実現する多周波信号送出装置の1例を示すもの
である、単周波信号を選択するセレクタ1a、1b1選
択された2つの単周波信号を加算する加算器2、加算き
れた多周波信号にレベル信号を乗算する乗算器3、乗算
結果を圧縮する圧縮器4、レベル信号を送出するレジス
フ5、単周波選択信号を記憶するメモリ6、各種タイミ
ングを発生し、各部を制御する制御回路7およびメモリ
6のアドレスを切替えるセレクタ8より構成される。Figure 1 shows an example of a multi-frequency signal transmitting device that realizes the conventional digitized multi-frequency signal transmitting system. An adder 2 that adds frequency signals, a multiplier 3 that multiplies the added multi-frequency signal by a level signal, a compressor 4 that compresses the multiplication result, a register 5 that sends out a level signal, and a memory that stores a single-frequency selection signal. 6. Consists of a control circuit 7 that generates various timings and controls each section, and a selector 8 that switches addresses of the memory 6.
第2図は本発明の対象となる多周波信号送出方式の入力
信号と出力信号の関係を示すタイムチャートである。FIG. 2 is a time chart showing the relationship between the input signal and the output signal of the multi-frequency signal transmission system to which the present invention is applied.
入力信号である単周波信号は、各周波数のアナログ信号
を毎秒8000回サンプリングし、サンプリング結果を
16bitでコード化しく通常音声のサンプリング情報
は8bitでコード化されるが、この場合には加算、乗
算等の演算処理が行われるので歪を少なくするため16
ビツトコード化が必要であるとされている。The single-frequency signal that is the input signal is an analog signal of each frequency that is sampled 8000 times per second, and the sampling results are coded with 16 bits. Normally, audio sampling information is coded with 8 bits, but in this case, addition and multiplication are required. 16 to reduce distortion.
It is said that bit encoding is required.
)8.192Mb/sの速度で送られてくる。) 8.192 Mb/s.
8Kb/sのクロックはサンプリング周期を示しており
、同−周期内の単周波信号は同じ信号である。The 8 Kb/s clock indicates a sampling period, and single frequency signals within the same period are the same signal.
出力の信号線は8bit単位のタイムスロットがNo、
0=No。The output signal line has a time slot of 8 bits,
0=No.
127の128あり、又8Kb/sのクロックは、No
、0タイムスロツトのはじめを示す。There are 127 and 128, and the 8Kb/s clock is No.
, indicates the beginning of the 0 time slot.
以下第1図および第2図を用いて従来技術について説明
する。The prior art will be explained below with reference to FIGS. 1 and 2.
外部装置は、送出したい多周波信号の選択信号データを
メモリ6に書込む。The external device writes selection signal data of the multi-frequency signal to be sent into the memory 6.
なお、この際メモリ6のアドレスとタイムスロット番号
は対応しており、外部装置は送出したいタイムスロット
番号すなわちメモリ6のアドレスをセレクタ8を介して
メモリ6に入力する。At this time, the address of the memory 6 and the time slot number correspond, and the external device inputs the time slot number to be transmitted, that is, the address of the memory 6, to the memory 6 via the selector 8.
一方制御回路7は外部からもらう第2図に示す8Kb/
sおよび8.192Mb/sのクロックからタイムスロ
ット2つに1回、例えば偶数タイムスロット時のみ、メ
モリ6を読み出し、メモリ6の内容に従い、セレクタ1
aおよび1bで2つの単周波信号を選択し、加算器2で
混合し多数波信号を作成し、その多周波信号にレジスタ
5より送られてくるレベル信号を乗算器3で乗算し、圧
縮器4で15bitの信号を8bitに圧縮し、出力信
号として外部に送出する。On the other hand, the control circuit 7 receives an 8Kb/8Kb signal from the outside as shown in FIG.
s and 8.192 Mb/s clock once every two time slots, for example, only in even time slots, and according to the contents of the memory 6, selector 1 is read out.
Two single frequency signals are selected by a and 1b, mixed by adder 2 to create a multi-frequency signal, multiplier 3 multiplies the multi-frequency signal by the level signal sent from register 5, and the compressor 4 compresses the 15-bit signal to 8-bit and sends it to the outside as an output signal.
なお、内部の演算により生じた遅れに従い、8.192
Mb/sおよび8Kb/sリランク信号も遅らせ外部に
送出する。In addition, according to the delay caused by internal calculation, 8.192
Mb/s and 8Kb/s rerank signals are also delayed and sent to the outside.
以上述べた従来の多周波信号送出方式では、入力信号が
15bitであり、それを演算し、8bitに圧縮して
タイムスロットに入れるため、連続する2つのタイムス
ロットに多周波信号を送出することが出来ないという欠
点があった。In the conventional multi-frequency signal transmission method described above, the input signal is 15 bits, which is computed, compressed to 8 bits, and placed in the time slot, so it is not possible to send the multi-frequency signal in two consecutive time slots. The drawback was that it couldn't be done.
また連続する2つのタイムスロットに多周波信号を送出
するためには、例えば偶数タイムスロット用と偶数タイ
ムスロット用に第1図に示すハードウェアを2つ用意し
なければならず多大なハードウェアとなるという欠点が
あった。Furthermore, in order to send multifrequency signals to two consecutive time slots, it is necessary to prepare two pieces of hardware, one for even numbered time slots and the other for even numbered time slots, as shown in Figure 1, which requires a large amount of hardware. There was a drawback.
本発明の目的は、上記従来技術の欠点をなくし、少ない
ハードウェアで連続する2つのタイムスロットに多周波
信号を送出できる多周波信号方式を提供することにある
。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a multi-frequency signal system that can transmit multi-frequency signals in two consecutive time slots with a small amount of hardware.
本発明の特徴は、タイムスロットとは非同期にあらかじ
め考えられる多周波信号をすべて作成、記憶し、外部よ
り指定されたタイムスロットにあらかじめ作成した多周
波信号から外部より指定された1つを選び送出すること
にある。The feature of the present invention is that all possible multi-frequency signals are created and stored in advance asynchronously with the time slots, and one externally specified multi-frequency signal is selected and sent out from the multi-frequency signals created in advance at an externally specified time slot. It's about doing.
以下本発明を第2図および第3図を用いて説明する。The present invention will be explained below with reference to FIGS. 2 and 3.
なお、第3図は本発明による多周波信号送出方式を実現
する多周波信号送出装置の1構成例を示すものであり、
単周波信号を選択するセレクタ9a+9b)選択された
2つの単周波信号を加算する加算器10、加算された多
周波信号にレベル信号を乗算する乗算器11、乗算結果
を圧縮する圧縮器12、レベル信号を送出するレジスタ
13、各種タイミングを作成し各部を制御する制御回路
14、外部からの指示を記憶するオーダメモリ16、オ
ーダメモリ16のアドレスを切替えるセレクタ15、多
周波信号を記憶するバッファメモリ18、バッファメモ
リ18のアドレスを切替えるセレクタ17および出力信
号を送出するシフトレジスタ19より構成される。It should be noted that FIG. 3 shows an example of the configuration of a multi-frequency signal sending device that realizes the multi-frequency signal sending method according to the present invention.
Selector 9a+9b for selecting a single frequency signal) Adder 10 for adding the two selected single frequency signals, Multiplier 11 for multiplying the added multifrequency signal by a level signal, Compressor 12 for compressing the multiplication result, Level A register 13 that sends signals, a control circuit 14 that creates various timings and controls each part, an order memory 16 that stores instructions from the outside, a selector 15 that switches the address of the order memory 16, and a buffer memory 18 that stores multifrequency signals. , a selector 17 that switches the address of the buffer memory 18, and a shift register 19 that sends out an output signal.
外部装置はタイムスロット番号に対応するオーダメモリ
16のアドレスに従いそのタイムスロットに送出したい
多周波信号種別をオーダメモリ16に書込む。The external device writes in the order memory 16 the type of multifrequency signal that it wants to send to the time slot according to the address in the order memory 16 that corresponds to the time slot number.
一方、制御回路14は、あらかじめ考えられるすべての
単周波信号の組合せについて、その多周波演算が8K(
zの1周期内に終るように単周波選択信号を順次発生す
る。On the other hand, the control circuit 14 performs 8K (
Single frequency selection signals are generated sequentially so as to end within one period of z.
この信号によりセレクタ9aおよび9bを介して2つの
単周波信号が選択され、加算器10で混合され多周波信
号が作成される。Based on this signal, two single frequency signals are selected via selectors 9a and 9b, and mixed by adder 10 to create a multifrequency signal.
この多周波信号にレジスタ13から送られてくるレベル
信号を乗算器11で乗算し、圧縮器12で15bit信
号を8bitに圧縮し、バッファメモリ18のその多周
波信号に対応するアドレスに書込む。This multifrequency signal is multiplied by the level signal sent from the register 13 in the multiplier 11, and the compressor 12 compresses the 15-bit signal into 8 bits, which is written to the address corresponding to the multifrequency signal in the buffer memory 18.
すなわち、バッファメモリ18は考えられるすべての多
周波信号の数だけのワード数を有し、その内容は8KH
zの1周期の間に1回、すなわち125μSの1回書き
替えられる。That is, the buffer memory 18 has the number of words equal to the number of all possible multi-frequency signals, and its contents are 8KH.
It is rewritten once during one cycle of z, that is, once every 125 μS.
また制御回路14は、タイムスロット毎にセレクタ15
を介し、オーダメモリ16を読み、オーダメモリ16の
内容に従い、そのタイムスロットに送出すべき多周波信
号をバッファメモリ18から読み出し、シフトレジスタ
19にセラ・し、8.192Mb/sの信号でシリアル
に外部に送り出す。The control circuit 14 also controls a selector 15 for each time slot.
According to the contents of the order memory 16, the multi-frequency signal to be sent in that time slot is read out from the buffer memory 18, transferred to the shift register 19, and serially transmitted as an 8.192 Mb/s signal. to the outside.
以上述べたように、タイムスロットとは非同期にあらか
じめ考えられる多周波信号をすべて作成記憶し、外部か
ら指定されたタイムスロットにあらかじめ作成した多周
波信号から指定された1つをえらび送出することにより
、ハード量が少なく連続する2つのタイムスロットに多
周波信号を送出できる多周波信号送出方式が実現できる
。As mentioned above, a time slot is a process in which all conceivable multi-frequency signals are asynchronously created and stored, and a designated one is selected and sent out from the multi-frequency signals created in advance at a designated time slot from the outside. , it is possible to realize a multi-frequency signal transmission method that can transmit multi-frequency signals in two consecutive time slots with a small amount of hardware.
第1図は従来技術による多周波信号送出方式を実現する
多周波信号送出装置の1例を示すブロック図、第2図は
本発明の対象となる多周波信号送出方式の入力信号と出
力信号の関係を示すタイムチャート、第3図は本発明に
よる多周波信号送出方式を実現する多周波信号送出装置
の1実施例を示す1177図である。
9a、9b・・・・・・セレクタ、10・・・・・・加
算器、11・・・・・・乗算器、12・・・・・・圧縮
器、13・・・・・・レジスタ、14・・・・・・制御
回路、15.17・・・・・・セレクタ、16・・・・
・・オーダメモリ、18・・・・・・バッファメモリ、
19・・・・・・シフトレジスタ。FIG. 1 is a block diagram showing an example of a multi-frequency signal transmission device that realizes a multi-frequency signal transmission method according to the prior art, and FIG. A time chart showing the relationship, FIG. 3 is a diagram 1177 showing one embodiment of a multi-frequency signal sending device realizing the multi-frequency signal sending method according to the present invention. 9a, 9b... Selector, 10... Adder, 11... Multiplier, 12... Compressor, 13... Register, 14...Control circuit, 15.17...Selector, 16...
...Order memory, 18...Buffer memory,
19...Shift register.
Claims (1)
単周波信号のうちから、複数の信号を選択混合すること
によって多周波信号を作成し、指定されたタイムスロッ
トに該多周波信号を送出する多周波信号送出方式におい
て、あらかじめ考えられる多周波の組み合わせ数だけの
ワード数を有するメモリを用意し、送出すべきタイムス
ロットとは非同期に、サンプリング周期ごとに該メモリ
の該当するアドレスに多周波の混合信号データを更新し
ておき、外部から指定されたタイムスロットに送出する
時点で外部から指定された多周波信号を上記あらかじめ
作成した多周波信号の中から選択・送出することを特徴
とする多周波信号送出方式。1. According to instructions from the outside, a multi-frequency signal is created by selectively mixing a plurality of digitalized single-frequency signals, and the multi-frequency signal is sent out in a designated time slot. In the frequency signal transmission method, a memory having the number of words equal to the number of possible combinations of multi-frequency signals is prepared, and the multi-frequency mixture is sent to the corresponding address of the memory every sampling period, asynchronously to the time slot to be sent. The multi-frequency signal is characterized in that the signal data is updated, and at the time of transmitting it to an externally designated time slot, an externally designated multifrequency signal is selected and transmitted from among the multifrequency signals created in advance. Signal transmission method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11575878A JPS5810036B2 (en) | 1978-09-22 | 1978-09-22 | Multi-frequency signal transmission method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11575878A JPS5810036B2 (en) | 1978-09-22 | 1978-09-22 | Multi-frequency signal transmission method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5542442A JPS5542442A (en) | 1980-03-25 |
| JPS5810036B2 true JPS5810036B2 (en) | 1983-02-23 |
Family
ID=14670315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11575878A Expired JPS5810036B2 (en) | 1978-09-22 | 1978-09-22 | Multi-frequency signal transmission method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5810036B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57106002A (en) * | 1980-12-23 | 1982-07-01 | Murata Manufacturing Co | Positive temperature coefficient thermistor |
| JP4888264B2 (en) * | 2006-07-28 | 2012-02-29 | Tdk株式会社 | Multilayer thermistor and manufacturing method thereof |
-
1978
- 1978-09-22 JP JP11575878A patent/JPS5810036B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5542442A (en) | 1980-03-25 |
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