JPS5810713B2 - Automatic clock signal switching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock signal switching device suitable for application to, for example, an electronic watch, and particularly to a clock signal switching device that is suitable for application to, for example, an electronic timepiece, and in particular, for example, in a clock that uses a commercial power supply frequency as a clock signal, the output of a built-in oscillator is switched to a clock signal in the event of a power outage. It is designed to detect the presence or absence of a commercial power supply signal to be used as a time signal, and automatically switch the clock signal based on the detected output.

Commercial power supplies have relatively high-precision frequencies (50Hz/60Hz).
Hz), and in electric watches, it is used not only as a power source but also as a fundamental frequency for forming a clock signal.

However, if the power stops temporarily due to an unexpected power outage, etc.,
It also has the drawback of displaying an incorrect time even after the power is restored.

Battery-powered watches are widely used as they do not have these drawbacks, but since all the power is provided by batteries, their lifespan is shortened, and they also require precision to always keep accurate time. This requires an oscillation circuit, such as a crystal oscillation circuit, which has a high frequency, which also has the disadvantage of increasing costs.

Therefore, if the clock is normally clocked by the commercial power supply, and if there is a temporary power outage, the clock is clocked by the built-in battery, the oscillation circuit only needs to be accurate enough to temporarily interpolate the frequency of the commercial power supply. Sometimes, you can extend the life of your battery by only keeping the clock and not displaying it.

The present invention is applied to such electronic watches, in which the presence or absence of a main time reference signal such as a commercial power source can be detected, and if the main time reference signal disappears, the main time reference signal is automatically detected. When the main clock reference signal is switched to output the secondary time reference signal and the main clock reference signal is supplied again, the switch returns to the state of outputting the main clock reference signal, and this switching can be done automatically. This is how it was done.

There are several possible methods for detecting the continuation of the main repetitive signal.

For example, by integrating the repeated signal and converting it into a direct current, it is possible to logically determine whether it is "0" or "1".

If the main signal is limited to the commercial power supply, it can be determined whether it is "0" or "1" depending on the presence or absence of the power supply voltage.

However, considering the use of IC circuits, these two methods lead to an increase in the number of input terminals, leading to an increase in cost.

In view of these points, the present invention aims to provide an automatic clock signal switching device that does not require an increase in the number of input terminals even when integrated into an IC, and can operate reliably.

An embodiment of the present invention will be described in detail below.

FIG. 1 shows one embodiment of the present invention, and 1 is a main clock signal input terminal, that is, in this example, an input terminal to which an electric signal obtained by shaping the commercial power frequency into a rectangular wave is supplied, and 2 is an auxiliary clock signal input terminal. A clock signal input terminal, that is, an oscillator signal input terminal; 3 is a negative circuit; 4 is a set priority type flip-flop circuit; 4a is a set input terminal of this flip-flop circuit 4; 4b is a reset input terminal; 5 is an AND gate circuit , 6 is an OR gate circuit, 7 is a monostable multi-by-break that generates a predetermined delayed output, and 8 is a clock pulse output terminal.

In the present invention, a clock pulse based on the commercial power signal supplied to the input terminal 1 is normally sent from the output terminal 8, and when the commercial power signal cannot be obtained due to a power outage or other reasons, A clock pulse based on the oscillator signal is sent to the output terminal 8.

The operation will be explained below using the waveform diagram in FIG.

FIG. 3A shows a commercial power supply signal supplied to the input terminal 1 as a signal Pa shaped into a rectangular wave in advance, and sets the flip-flop circuit 4 at the rising edge of the signal Pa.

On the other hand, the input terminal 2 is supplied with the output signal Pc of the oscillator (not shown) shown in FIG. The flip-flop circuit 4 is reset at .

In this case, the flip-flop circuit 4 operates as a set-priority flip-flop circuit that is reset at the rising edge of signal Pa only in the period in which the signal Pa is "0", that is, in the period in which Pa is "1".

In this way, the output terminals 4c and 4d of the flip-flop circuit 4
The output Pe shown in FIGS. 3E and F.

(2) is obtained, the output page is supplied to one input terminal of the AND gate circuit 5, and the other input terminal is supplied with the signal P from the oscillator.
supply c.

In this way, when the signal ■ from the inverted output 4d of the flip-flop circuit 4 is in the state of "1", the signal Pc from the oscillator is supplied to one terminal of the OR gate circuit 6, and the signal Pc is supplied to the other input terminal of the OR gate circuit 6. supplies the commercial power signal Pa supplied to the input terminal 1.

Therefore, while the commercial power supply is present, no signal is obtained at the output of the AND gate circuit 5, and therefore the commercial power supply signal Pa is supplied to the monostable multi-by-break 7 as the signal Pg through the OR gate circuit 6, and at the rising edge of the signal Pa. A pulse Ph delayed by a certain time (τ) is obtained at the output terminal 8.

On the other hand, during a power outage (see Figure 3C), the commercial power signal Pa is
However, since the auxiliary clock signal Pc is supplied to the input terminal 2, the flip-flop circuit 4 is reset and the output signal ■ of the inverting output terminal 4d becomes "1". The oscillator signal Pc is obtained at the output,
Since this AND output is supplied to the OR circuit 6, a continuous signal Pg is supplied to the monostable multi-bi break 7 not only while the commercial power supply signal Pa is present, but also during the power outage period T, and therefore, the monostable multi-bi break 7 outputs a continuous signal Pg. terminal 8
The pulse ph can be obtained regardless of the presence or absence of the commercial power supply signal Pa, and by counting this output pulse Ph as a clock pulse, the clock operation can be performed even during a power outage.

Incidentally, FIG. 2 shows a case where the inverting circuit 3 is inserted into a commercial power supply signal, etc., and in this case as well, the same effect as described above is achieved.

Incidentally, in the above description, the frequency relationship between the main signal Pa and the auxiliary signal Pc was not particularly described, but they may have the same frequency or may have a different frequency relationship.

In this case, the auxiliary signal Pc is supplied to the terminal 4b from the "0" section TAO (see FIG. 3C) of the main signal Pa (or Pa) supplied to the main signal input terminal 1 of the flip-flop circuit 4. It is sufficient that the interval TBO (see FIG. 3C) of "0" of (or Pc) is a dog, that is, the condition (TAO<TBO) is satisfied, for example, the frequency of the main signal Pa is the same as the auxiliary signal Pc.
If the frequency is much higher, as shown in FIG. 4, a frequency divider 9 may be inserted into the main signal system to convert it into a main signal having the same frequency as or slightly higher than that of the auxiliary signal.

In FIG. 4, SW indicates the entire signal switching circuit shown in FIGS. 1 and 2, and 10 is a frequency dividing circuit of 1150 and 1/60.

That is, the frequency dividing circuit 10 is supplied with the output of the output terminal 4c of the flip-flop circuit 4, and the rlJ, rOJ of this output terminal
The frequency dividing circuit is switched according to the frequency difference between the main signal Pa and the auxiliary signal Pc (1150 and 1/
60 switching) and the main signal and auxiliary signal frequencies are different, or when the main signal is 50Hz and 60Hz.
Even in this case, a predetermined timing operation is performed.

If the frequency of the auxiliary signal Pc is much higher than the frequency of the main signal Pa, a frequency divider circuit 9 may be inserted into the auxiliary signal system as shown in FIG.

In this case, the input frequency of the auxiliary signal to the board is 31.5 kHz.
z, and if the main signal is used for both 50 Hz and 60 Hz, if the frequency division ratio of the frequency divider circuit 9 is set to 1/630, the input frequency to the flip-flop circuit 4 can be divided to 50 Hz.

Therefore, if the frequency of the main signal supplied to the main signal input terminal 1 is 50Hz, the output terminal 8 of the signal switching circuit SW has a frequency of 50Hz.
When a clock pulse of 0 Hz is obtained, the frequency divider circuit 10 is operated as a 1150 frequency divider circuit, and the output terminal of the frequency divider circuit 10 is connected to I.
If the main signal Pa to the input terminal 1 has a frequency of 60 Hz, the frequency dividing circuit 10
The circuit is operated as a 1/60 frequency dividing circuit, and thus a clock pulse of IHz is obtained at the output terminal.

This switching is performed based on the combination of the output signal C of the output terminal 4c of the flip-flop circuit 4 and the input CM for switching the count mode.

If both the main signal and the auxiliary signal have high frequencies, insert frequency divider circuits 9 and 9' in both signal systems as shown in Figure 6 so that both signals satisfy the condition TAo<TB. good.

On the other hand, it is convenient to combine the signal switching circuit of the present invention with a power supply switching circuit.

FIG. 1 shows an example of this, in which a main power supply, in this case a commercial power supply P1, and an auxiliary power supply, for example, a battery power supply P2, are connected to an instantaneous power supply switching circuit SWP, and the output of this switching circuit SWP is supplied to the circuit section 11. I will do it to you.

In this way, if the commercial power supply P1 is immediately switched to battery power when there is a power outage, by combining it with the automatic signal switching circuit SW, it will operate accurately even during a power outage. It is also convenient in practical use because it can provide an electric clock that does not malfunction.

[Brief explanation of the drawing]

Fig. 1 is a system diagram showing one embodiment of the present invention, Fig. 2 is a system diagram showing another embodiment of the invention, Fig. 3 is a waveform diagram for explaining the operation of the circuit of the present invention, and Fig. 4 is a system diagram showing an embodiment of the present invention. 7 to 7 are system diagrams showing application examples of the circuit of the present invention. 1 is a main signal input terminal, 2 is an auxiliary signal input terminal, 4 is a set priority type flip-flop circuit, 5 is an AND gate circuit, 6 is an OR gate circuit, and 7 is a monostable multi-by-break.

Claims (1)

[Claims] 1 A first input terminal to which the main time reference signal is supplied, a second input terminal to which the secondary time reference signal is supplied, and the first
and a digital detection circuit connected to the second input terminal and detecting the presence or absence of the main clock reference signal, and a detection output of this detection circuit supplies the main clock reference signal to the first input terminal. When the supply of the main time reference signal is interrupted, the secondary time reference signal is sent out, and when the supply of the main time reference signal is restored. and a switching circuit for selectively sending out the main clock reference signal again when the main clock reference signal is interrupted.