JPS5810799B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory devices, and more particularly to advanced high speed circuits for N-channel MO8 memory devices employing one transistor memory cells.

MOS random access memory (RAM) devices are widely used in the construction of digital devices, especially minicomputers.

The capabilities and cost advantages of this type of storage device have steadily increased over the past few years.

In the industry, the price per bit of memory using MOS RAM decreases as the number of bits per implementation or the number of memory cells increases.
RAMs with progressively larger capacities, 1024 bits and then 4096 bits, are becoming standard.

For example, U.S. Pat.
No. 7 states.

At present, semiconductor device manufacturers are listed in the February 19, 1976 issue of the English magazine "Electronics", page 116.
-121 and 16.384 bits or "
They have started manufacturing 16Kj RAM.

As the number of bits in one semiconductor chip increases,
As the size of the cells decreases, the amount of storage capacity in each cell necessarily decreases.

- At the same time, the number of cells on one digit line in the cell array also increases, thus increasing the capacitance of this line.

Because of these factors, the magnitude of the data signal present on the data line decreases, i.e., the amplitude of the logic level "1"
The potential difference between and “0” is probably 1 in these devices.
However, the selected one is either 0 volts or 12 volts.
The potential difference between a ``1'' and a ``0'' for data coupled from a transistor cell to a digit line in a storage array will likely be on the order of 0.1 to 0.2 volts.

Various circuits have been proposed to detect such low-level signals.

For example, U.S. Pat. No. 3,940,747 mentioned above and U.S. Pat. No. 19 P116-
121 and IEEE Society Solid State Circuit Journal 1972
Sense amplifiers are introduced in Stein's article in October issue P336.

When used in memory devices that require high density packaging, high speed, and low power consumption, such as RAMs in 16th grade, previously proposed sense amplifiers have drawbacks.

Some exhibit high power consumption and too long charging times for digit lines.

Still others require instantaneous large currents and tight clock timing.

In one embodiment of the invention, a circuit is shown that avoids many of the undesirable features of conventional sense amplifiers.

This circuit uses a booting capacitor and a shunt transistor to control the load transistor in a bistable sense amplifier.

However, this circuit requires an independent clock source with an intermediate voltage level to control the gates of the shunt transistors.

This need for an independent clock is avoided in another embodiment of the invention.

In conventional dynamic RAMs, data output is typically taken from one side of a column line, and data input is provided on the same side even if the addressed cell is on the opposite side.

In a high-density device such as No. 16, the capacitance of the column line or sense line is large, so a delay occurs due to the time required for that line to charge and discharge the entire ring width.

Therefore, it is preferable to detect the column line logic level on each side of the sense amplifier and to generate a high level output by an intermediate output buffer.

Memory read and write times are usually quoted to express the operating speed of a memory.

Read time refers to the time interval required to access data from the memory, and write time refers to the time interval required to write data into the memory.

The speed at which these operations are performed is critical.

That is, the trend over the past 10 years in digital devices using these storage devices has been to continually require higher speed operation.

Therefore, much effort in the semiconductor industry has been focused on developing faster memory speeds.

The read time of a semiconductor chip is determined by several factors.

Until now, one factor has been the time delay between stabilizing a sense amplifier within a memory chip and sending the output of that sense amplifier to the data output leads on the chip.

This time delay was intentionally inserted to ensure that the sense amplifier stabilized before delivering its output.

The sense amplifier capacitive load is delicately balanced during read operations.

If the sense amplifier sends an output before it has stabilized, this balance will be disrupted and a read error will result.

This time delay was typically built in by the R-C's read clock generator.

It: uses one capacitor and two transistors A and B to act as an RC timing circuit.

Transistor A has a source connected to power supply Vdd' and a drain connected to node N.

Transistor B has a source connected to node N and a drain connected to ground potential.

A capacitor is also connected between node N and ground.

Prior to a read operation, transistor A is turned on, thereby charging the capacitor.

During a read operation, transistor B turns on and thus the capacitor discharges.

This discharge time is designed to be longer than the time required for the sense amplifier to stabilize, and the sense amplifier is delivered after this discharge is complete.

One problem with this RC read clock generator is that the RC time constant needs to be set much longer than equal to the sense amplifier stabilization time.

The reason for this is that the time constants of the RC circuit and the sense amplifier cannot be precisely matched due to the structural differences between the two circuits.

A sense amplifier is essentially a differential voltage sensing device and is different from a simple RC discharge circuit.

This structural difference also results in a difference in the behavior of the two circuits as the time constants change with temperature.

As a result, the read time of the memory chip becomes undesirably long.

Typically, a semiconductor RAM receives a multi-bit address from an external circuit, and that address has the function of selecting a specific cell in the FtAM to which data is to be written or read. It occurs somewhere else, away from RAM.

Thus, one requirement for a RAM circuit is that the timing and voltage levels of the address signals to which it must respond are compatible with the rest of the system.

The voltage level of the input address to the memory is often MO
It is a low bipolar voltage level such as TTL rather than a high voltage level such as S.

And low voltage input address signals will pose input address buffer design problems.

This is because such a low voltage signal does not completely turn on the MOS logic gate and is difficult to detect.

Nevertheless, detection of such signals must be accurate and rapid in order to make the storage system reliable and fast.

Traditionally, input address buffers have been designed to operate with low voltage address signals.

An example of an address buffer is U.S. Patent Application 5N624 filed October 22, 1975 by Redwine and Kitagawa and assigned to Texas Instruments.
, No. 813.

This buffer circuit is an advance in speed, low power, and noise level.

As memory density increases, constant advances in these factors are required.

In semiconductor storage systems, a fundamental RF lock voltage is applied to storage devices such as FtAM, which internally generate various additional RF lock and other control voltages in response to a fundamental clock.

For this storage system to have fast speed or access time, the RAM must respond quickly to its basic clock.

English magazine “Electronics J February 19, 1976 issue P
In current 4- or 16-bit RAMs of the type shown in P. 116-121 and P. 81-86 of May 13, the basic clock is the "row address strobe" or RAS signal.

In addition to the function of multiplexing row addresses, the RAS also functions as a basic clock of this system.

The speed at which the memory chip detects the rising edge (positive with respect to ground) of this RAS signal is one constraint on the speed or access time of this storage device.

The portion of the signal that is important to the timing of the device is the rising or negative-going side, which typically drives the input transistors, which act as two inverters.

The output of this inverter must be rapidly charged to a full logic level in order to start multiple circuits elsewhere in the device.

However, the capacitance of the input transistor itself prevents charging of this output terminal.

A semiconductor RAM receives a multi-bit address from an external circuit.

This address is the RA to which data should be written or read.
It has the function of selecting a specific cell in M.

This address occurs elsewhere in the system, away from RAM.

One requirement for this RAM circuit is that it be able to respond to voltage or logic levels and timing in the address signals in a manner that is compatible with the rest of the system.

The logic level of the system is often the bipolar or TTL operating voltage rather than that of an MO8 device.

The address input to the RAM must impose a longitudinal current load on the external circuitry.

The address signal detection circuit should also generate as little noise or undesirable voltage fluctuations as possible.

The address buffer circuit should be responsive to address signals only during short time windows during the operating cycle of the digital device.

This is because the address signals may change in preparation for the next access cycle before the current cycle is complete.

An address buffer circuit suitably serving these purposes is shown in the English journal "Electronics" already mentioned.

Nevertheless, continuous improvements in these factors, especially speed, are needed as computer cycle time demands increase.

Accordingly, one principal object of the present invention is to provide an improved high speed circuit for MO8RAM, and in particular, in one embodiment, to provide an improved and simple sense amplifier with low power consumption, high speed operation, and high sensitivity. It is.

Another object of the present invention is to provide an improved semiconductor memory device that operates at high speed or with shorter access or read times.

Another object is to provide an intermediate output buffer that speeds up data transfer from the memory cell array to the output terminal.

It is an object of one embodiment of the present invention to provide a memory with improved readout times, to provide an improved memory readout clock generator, and to provide an improved memory readout clock generator with a differential voltage sensing structure. The present invention is to provide a clock generator.

The purpose of this embodiment of the invention is to provide a read clock generator that generates an output signal within a few nanoseconds when the sense amplifier is stable.

Another purpose of this embodiment is to provide a read clock generator having timing parameters with temperature variation customization similar to the sense amplifier timing parameters.

It is an object of the invention in another embodiment to provide an improved circuit for detecting memory address signals.

It is also an object to provide an input address buffer with relatively fast operating characteristics, and a further object is to provide an input address buffer that accurately detects input signals at low voltage levels.

An object of one embodiment of the present invention is to provide an MO8 with advanced high speed input circuitry for logic or timing signals.
The purpose is to provide a RAM, and also to provide a circuit that separates the capacity between the output section and the output section so that the output node can be quickly charged.
The purpose is to provide a clock signal input to the O8/LSI device.

In yet another embodiment, the object is to provide a semiconductor MO8,
It is an object of the present invention to provide an advanced circuit for detecting address signals and other logic levels within the RAMO8, and more particularly, to provide improved circuitry for detecting address signals and other logic levels within the RAMO8, and more particularly, to provide improved circuitry for detecting address signals and other logic levels within the RAMO8. The objective is to provide a high-speed circuit that can balance both level and load.

According to a first embodiment of the invention, a MO8RAM using a one-transistor cell includes a pair of drive transistors located in the center of each column line of the memory array and cross-connected to form a bistable circuit. A type of sense amplifier is used.

The load transistor for this pair of drive transistors is clocked on by the control circuit for only a portion of the operating cycle.

The drive transistor is connected to ground through two different paths provided by two transistors that are clocked at different times.

During the initial sensing period, the current through the drive transistor is held low and then there is a period when it is allowed to go high, during which the full logic level width output is generated.

The load transistor is clocked on by the booting capacitor during the period after the initial sense period.

The gate of the load transistor is connected to the digit line by a shunt transistor.

Each shunt transistor has its gate connected directly to the digit line on the opposite side of the sense amplifier.

The role of the shunt transistor is to turn off the load transistor on the zero side of the sense amplifier, thereby saving power and allowing faster operation.

According to a second embodiment of the present invention, a one-transistor cell MO8RAM has one transistor cross-connected in the center of each column line in the memory array to form a bistable circuit.
It employs a type of sense amplifier that includes a pair of drive transistors.

The load transistor for this pair of drive transistors is clocked on for only a portion of the operating cycle.

By this time the cell has been addressed.

The drive transistor is connected to ground by two different paths provided by two transistors that are clocked on at different times.

During the initial sense period, the current through the drive transistor is held low and then allowed to increase to a high level, thereby producing a full logic level width output.

The load transistor is clocked on by the booting capacitor after the initial sense period, ie during the latter period mentioned above.

The gate of the load transistor is coupled to the digit line by a shunt transistor having a selected voltage level on its gate.

The role of these shunt transistors is to turn off the load transistor on the null side of the sense amplifier.

According to a third embodiment of the present invention, a one-transistor cell MOS FtAM employs a bistable sense amplifier located in the center of each column line.

An intermediate output buffer has inputs connected to both sides of the sense amplifier through a column decoder.

This intermediate output buffer includes a pair of drive transistors cross-coupled to form a bistable circuit, similar to the second embodiment.

The precharge/load transistor for the sense node, which is the drain of a pair of drive transistors, is clocked on by the control circuit for only a portion of the operating cycle.

The drive transistors are connected to ground by two different paths, either one-sidedly grounded by a single element, or provided by two transistors that are clocked on at different times.

In this regard, U.S. patent application S.N. 682,6, filed May 3, 1976, by Kitagawa and McAlexander and assigned to Texas Instruments, Inc.
It is stated in No. 85.

The sense clause is connected to the column line at the beginning of the initial sense period.

One side of the column line changes to low level and the other side remains at high level.

During this initial sensing period, the current through the drive transistor is held low and allowed to go high during subsequent periods, thereby producing a full logic level width output.

The precharge/load transistor is clocked on by the booting capacitor after this initial sense period, ie during the latter period.

The gate of the precharge/load transistor is connected to the source of the drive transistor by a shunt transistor.

The shunt transistors each have their gates connected directly to the opposite sense node of the bistable circuit.

The role of the shunt transistor is to turn off the precharge/load transistor on the zero side of the bistable circuit, thereby saving power and allowing faster operation.

According to a fourth embodiment of the invention, a bistable amplifier is coupled to the differential voltage sensing transistor.

This bistable amplifier has a similar structure to the memory sense amplifiers of the second and third embodiments.

These two circuits thus have similar timing characteristics.

This bistable amplifier is driven by a clock signal at the same moment that the memory sense amplifier is driven.

Therefore, both circuits become stable at the same time.

The differential voltage sensing transistor senses when the bistable circuit is stable and provides an output indicating that the bistable circuit is stable.

According to a fifth embodiment of the invention, a pair of cross-coupled transistors is employed with set and reset nodes initially precharged to a predetermined level.

The set and reset nodes are coupled to a pair of load transistors.

Each load transistor has a control node that is initially precharged to one other level.

The input address signal is detected by further charging (or discharging) the precharged voltages of the set and reset nodes at two different rates.

These speeds reflect the state of the input address signals.

A current synchro path senses this different charging (or discharging) rate.

In response, the current sink circuit selectively absorbs pre-charge from the set or reset node and from the corresponding load transistor control node.

The state of the input address signal is therefore latched onto the load transistor control box.

According to a sixth embodiment of the present invention, a clock input circuit for an MO8/LSI device employs an input transistor having a +■ rise with respect to ground for a clock input applied to its gate.

The input transistor is connected in series with a second transistor whose drain is connected to the output node.

The middle node of the drain of the input transistor is coupled to a control transistor, the drain of which is coupled to the gate of a second transistor.

According to this circuit configuration, the second transistor is cut off when the intermediate node reaches a voltage sufficient to turn on the control transistor.

When the second transistor is cut off, its output node is disconnected from the input capacitance, so it can charge faster.

The output node is tied to the supply voltage through a bootstrap load transistor.

The gate of the second transistor is precharged in time before the rising edge of the input.

In a seventh embodiment of the invention, a semiconductor memory is provided with an address buffer by a pair of cross-coupled MO8 drive transistors that function as a differential detector.

One of the transistors is larger than the other and is unbalanced.

The address input is coupled to one side of the differential pair by a transistor device.

The output nodes of the differential pair are precharged to a high level prior to the address input, and immediately after the address input, the same amount of charge is applied to them by a pair of capacitors, resulting in a ``1'' level. This prevents the discharge of that node, which should remain at that point.

The state of the output nodes of the cross-coupled pair is detected and an address signal is asserted and latched, immediately after which the same amount of charge is applied and the address inputs are subsequently changed without affecting the internal address signals.

This cross-coupled drive transistor has two transistors connected to ground that are turned on at different times.

The novel features believed to be characteristic of the invention are set forth in the claims.

The invention itself, however, may best be understood by reading the following detailed description of specific embodiments, taken in conjunction with the drawings.

Referring to FIG. 1, an MO8 storage device incorporating various embodiments of the present invention is shown.

Although this device can be of various sizes, in the present invention, 16,
We are considering implementing very high density storage devices, such as those containing 384 cells.

The device includes an array 10 of 16,384 memory cells, which is typically divided into 128 rows and 128 columns.

Each cell was published in the English magazine "Electronics J, 1976, 5
The so-called 1 as shown on pages 81-86 of the 13th issue of the month
It is a transistor cell type.

The row decoder 11 selects one of the 128 row lines according to the 80 or X addresses contained in the 7-bit row address buffer or latch 12.

Further, the column decoder 13 selects one of 128 column lines determined by the column or Y address contained in the 7-bit column address buffer 14.

These addresses are provided to the chip by seven address lines 15 in a time-sharing manner.

RAS or row address strobe input 16 (fourth
g) allows the row address buffer 12 to receive a row address when it is at zero volts.

The row address includes bits AO to A6.

Similarly, CAS or column address strows input 1
7 (see Figure 4h) also enables the column address buffer to receive the column address (bits A7 to A13) from line 15 when at zero volts.

This row and column address must be valid on pin 15 for the time shown in Figure 4f.

14 address bits are required to uniquely specify 1 bit out of 16,384 cells (
214 = 16.384).

An input/output control circuit 18 is coupled to the array 10 through a column decoder 13 and under the control of various internally generated clocks and logic voltages and read/write (R/W) inputs 22.
Under the control of the data input pin 20, data is supplied onto the column line, and data on the column line is detected and supplied to the data output pin 21.

This device requires some supply and input voltage on pin 23.

In addition to ground or Vss, they have Vbb and Vcc.
, Vdd supply voltages are included.

Of course, there are also circuits designed to operate with one or two supply voltages instead of three.

Typically Vdd=12v, Vbb=-5v, Vcc=
+5v.

As seen in FIG. 2, the device of FIG. 1 consists of a silicon chip 2 mounted in a package 25 having 16 pins corresponding to 16 input lines as described above.
It is in the shape of a 4.

Thin gold wire connects the bonding butts on silicon chip 24 to internal terminals for pins 26.

Although not shown, a lid would seal the device.

This package 25 has a length of about 20 mm and a width of about 8 mm.
Therefore, a large number of such packages can be mounted on standard size circuit boards.

For example, a minicomputer will have a total of 32 or 64 words (16 bits per word) of memory on one small circuit board.

The conventionally designed decoder 11 selects one of the 64 row lines 29-1 on the left side or selects one of the 64 row lines 29-1 on the right side.
It has the function of selecting one from 9-2.

A row line is a metal line that runs almost the entire width of the chip and drives the gates of the 128 MOS transistors in the 128 memory cells for that row.

Seven address bits AO to 86 in the row decoder 11 drive one of the 128 row lines 29 to a high level, leaving the remaining 127 lines at a low level.

The row address (X in FIGS. 4b and 5) exists on the selected line 29 for a period of πAS, as shown in FIG. 4g.

A6 bit selects left or right side, i.e. line 29-
1. Select which line 29-2 to drive.

Next, 6 bits A5 is selected from the 6 bits AO.
Choose one of the four lines.

A6 also determines the excitation of the dummy cell on the non-selected side through the dummy cell address line 27 during RAS as before.

In accordance with a first embodiment of the invention, the storage device of FIG. 1 includes an advanced sense amplifier 30 in the center of each column line.

The role of the sense amplifier is to detect the small signal that occurs on the selected column line when a cell is addressed and convert this small signal into a full logic level wide signal.

Referring to FIG. 3, a sense amplifier 30 according to this embodiment of the invention is shown in a portion of an array.

The sense amplifier 30 basically consists of a flip-flop or bistable circuit comprising two cross-connected drive transistors 31 and 32 with associated load transistors 33 and 34.

A pair of nodes 35 and 36 are connected to corresponding halves 37 and 38 of the column line.

These nodes 35 and 36 are connected to the gates of opposite transistors 31, 32 to form a cross-connect structure.

Line 37, one half of the column line, has 64 cells 40 connected to it, and line 3, the other half, has 64 cells 40 connected to it.
The same applies to 8.

Each cell includes a transistor 41 and a capacitor 42.

The gate of each transistor 41 is controlled by a row line 29-1 or 29-2 (a row line is also called a word line or an X line).

Each row line is connected to 128 gates of the same transistor as transistor 41.

Since the array 10 in this example has 64 row lines on each side of the sense amplifier 30, and of course there are 128 sense amplifiers, only a small portion of the array 10 is shown in FIG. be.

Each sense amplifier has two dummy cells 44, one on each side, which are connected to column line 37.3B.
is connected to.

Like the memory cell 40, each dummy cell includes a transistor 45 and a capacitor 46.

The function of line 27 is to select transistor 4 in the row of dummy cells on the opposite side of the sense amplifier from the selected cell 40 as specified by the A6 bit of the row address.
5 is to be turned on.

At this time, the memory cell 40 selected at the same time is also addressed.

Each column line 37 or 38 is connected to a reference voltage line 48 through a transistor 49.

The gate of this transistor is driven by Z.

This causes lines 37 and 38 to charge in the same manner from a reference voltage level chosen to be at or slightly below Vdd.

For example, if Vdd is +12v and ■ is approximately 1v,
The reference voltage ref will be approximately 10 or 12V.

However, Vdd is used for simplicity of construction.

Load transistors 33 and 34 are tied to Vdd and are controlled by the advanced circuitry of the present invention as described below.

The flip-flop circuit including transistors 31 and 32 starts working when the node connected to the drain of the transistor is connected to ground, before transistors 33 and 34 become conductive.

Node 50 is connected to ground through a separate path comprising two transistors 51 and 52, in this case controlled by clocks φ1 and φ2.

Transistors 51 and 52 are of different sizes, so that the magnitude of the current flowing through these transistors from node 50 to ground or Vss is different.

That is, the voltage on node 50 changes differently depending on which of transistors 51 and 52 is conductive.

Transistor 51 is smaller than transistor 52, with a device ratio, ie, channel width to length ratio, of about half.

Since all 128 sense amplifiers 30 in array 10 use the same pair of transistors 51 and 52, one line connects all sense amplifier nodes 50 together with three clocks φ1 (FIG. 4c). ) becomes positive, the sensing operation starts and the flip-flop moves toward a stable state.

In a stable state, transistor 31 conducts and transistor 3
2 is non-conducting or vice versa.

The direction of switching depends on the potential difference between lines 37 and 38, which in turn depends on whether a "1" or a "0" was stored in the selected cell 40.

Since either line 37 or 38 is at a slightly higher potential than the other, the gate potential of either transistor 31 or 32 is at a slightly higher potential than the other, and when φ1 becomes positive, one one transistor will conduct slightly more current than the other.

The voltage at node 50 tends to increase as the device ratio of transistor 51 decreases, and the sensitivity of amplifier 30 increases during the initial period 50, for a given threshold voltage and digit line voltage, at node 50. directly related to the voltage of

As previously mentioned, the circuit of FIG. However, since φ2 tends to remain at a high level for a period before reaching a high level, high-speed operation can be performed.

In other words, the sense amplifier in FIG.
'' level is not discharged to a low voltage during the initial sense operation, providing a minimum charging time to refresh the ``1'' level on digit line 37 or 38.

Referring to FIG. 5, the voltages on digit lines 37 and 38 are shown enlarged as a function of time when clock φ1 is turned on.

During time 53, before the address excites low lines 11-1 or 11-2 and before D1 goes high, the voltage on digit lines 37 and 38 is reduced by charging from line 48. That is, approximately Vdd
is equalized to the potential of

At time 54, one of lines 29-1 and 29-2 goes high, causing the voltages on lines 37 and 38 to be very slightly different from each other.

This is due to the size difference between the storage capacitor 42 connected to one side and the dummy cell capacitor 46 (which is smaller than capacitor 42) connected to the other side, which may be approximately 50 to 100 millivolts. .

At time 55, φ1 goes high and line 37
and 38 begin discharging toward the rOJ level during period 58, while the other discharges only slightly and reaches approximately 0.
．． Not more than 3v.

This situation is illustrated by curves 56 and 57.

If a "1" is stored during the time interval 58, that is, until time 59 when φ2 is turned on, the transistor 31 or 32 facing the selected cell will be more conductive than the one facing the dummy cell. Will.

If ``0'' is stored, the opposite will occur.

According to a key feature of this embodiment of the invention, sense amplifier 30 of FIG. 3 includes special circuitry for conductance control of load transistors 33 and 34.

Nodes 61 and 62 of the gates of load transistors, 33 and 34
is the clock φ2 through the gated capacitors 63 and 64.
source and also to digit lines 37 and 38 through transistors 5 and 66.

In contrast to the circuit of the White et al application already discussed, these transistors 65 and 66 have their gates connected to line 6.
7 and 68 to the opposing digit lines 37 and 38.

While the White et al. application described above required a separate clock that varied between Vdd and an intermediate voltage approximately 8 volts below ref, this is not necessary with the present invention.

As can be seen from FIGS. 5 and 4d, φ2 also turns on transistor 52.

Capacitors 63 and 64 act as "booting" or bootstrap capacitors, producing high drive voltages on the gates of load transistors 33 and 34.

This allows for rapid charging of the digit line back to the "1" level as shown by curve 56 in FIG.
1'' level voltage recovery is also speeded up.

Transistors 65 and 66 discharge the drive voltage at node 61 or 62 at the gate of the load transistor on the zero side of the sense amplifier.

This saves power consumption and improves operating speed of the sense amplifier.

As seen in Figures 4a and 5, the line 37 between φ
and 38 (nodes 35 and 36) are precharged to level 70, while X, φ1. φ2 is zero.

During this period nodes 61 and 62 are charged to level 72 through transistors 65 and 66.

Level 72 and level 70 differ by the voltage drop across transistor 65 or 66.

Nodes 61 and 62 are of course opened by a transistor 73 connected between these parts.

group is applied to the gate of this transistor.

When φ becomes zero at time 71, digit lines 37 and 38
is isolated from ref, and at the same time nodes 61 and 62 are isolated from each other as transistor 73 is cut off.

Transistors 65 and 66 driven by opposing digit lines now provide a discharge path (a) on the booting capacitor 63 or 64 connected to the "1" side of the sense amplifier and on node 61 or 62; The charge does not discharge during the sense period, and (b) the charge on the part on the booting capacitor connected to the other side at zero discharges as the voltage on the digit line falls.

Since the voltage difference between digit lines 37 and 38 is determined by the charge distribution between dummy cell capacitor 46 and memory cell capacitor 42, and the selected X line 29-
1 or 29-2 goes high and the dummy cell select line 27 goes high, so the operation is the same as already described with respect to period 58 of FIG.

At time 55, φ1 becomes high level and amplification of the voltage difference begins.

The initial level 72 of the voltage on the "1" side of nodes 61 and 62 is held until time 59 in FIG. begins to decay.

This is because the voltages on portions 35 and 36 during time interval 58 vary as shown by curves 56 and 57.

As long as the voltage difference is below V, transistors 65 and 66 are not turned on, but when the voltage difference reaches ■t at time 77, one is turned on.

Then, at time 59, φ2 goes high, which boots the gate voltage of loads 33 and 34 (curve 72) through capacitors 63 and 64, and turns on transistor 52, as shown by curve 57 in FIG. As shown above, the discharge speed on the zero side is sped up.

The sensing operation is completed at time 77 when the digit line voltage on the zero side falls by Vl below the instantaneous level on the one side, one of transistors 65 and 66 turns on, and on this side the booting capacitor 63 is turned on. or 64 begins to discharge, turning off the corresponding load 33 or 34.

In this case, the voltages on nodes 61 and 62 are shown in FIG. 5 by curves 74 and 75.

For example, if node 35 is on the zero side (either the selected cell on digit line 37 stores a zero, or the selected cell on digit line 38 stores a "1"), then When X goes high, at time 54 the voltage on node 35 reaches a level slightly lower than the voltage on node 36, i.e., node 36 is shown by curve 56 in FIG. This is shown by curve 57.

Starting at time 55 when φ1 goes high, the voltage difference between nodes 35 and 36 is amplified during the initial portion of period 58.

However, node 35 does not reach a potential below the voltage at node 36 until time 77.

When φ2 goes high at time 59, the amplification of the potential difference between curves 56 and 57 increases, and node 36 begins to rapidly charge towards Vdd through transistor 34, while node 35 charges through transistors 31, 51 . 52 towards Vss more rapidly.

At time 77, node 35 reaches a level ■ lower than node 36, transistor 65 is turned on, and node 61 becomes curve 75.
As seen in , it rapidly discharges towards Vs s.

The configuration of the invention does not reduce the sensitivity of this circuit.

This is because the voltage at nodes 61 and 62 remains stuck at level 72 until a Vl difference occurs between the digit lines and the sensing operation is complete.

Note that there may be periods of cessation, albeit very short periods of time.

That is, if time 77 occurs after time 59, the load transistor 33 on the zero side and the transistors 51 and 52 connected to ground are simultaneously conductive.

The period between this time 59 and 77 will be insignificant.

Transistor 52 and booting capacitors 63 and 64
There is a speed-versus-power trade-off in choosing the timing of the clocks provided to the system.

When φ2 is given to booting capacitors 63 and 64.

If it lags slightly behind that applied to transistor 52, i.e. on the zero side, digit line voltage 57 is more than ■1 below level 56, so the load on that digit line cannot be turned on; Power is only consumed by discharging the energy stored in the digit line capacitor.

However, the delayed φ2 to capacitors 63 and 64 results in increased device access time.

No delay in φ2 is the fastest access case, but as mentioned earlier the zero side load may be turned on for a short period of time, so the power consumption may increase negligibly.

If a transistor with a small device ratio is used as the transistor 51, the amplification on the zero side will be insufficient.1 Since the digit line 37 or 38, which is supposed to be at a low level, has a good zero level, the transistor 52 will have a higher amplification. It is for this reason that noise from other circuits is picked up during a read or write operation, so good logic levels on lines 37 and 38 are required to ensure reliable operation. It must be done.

A transfer gate 80 conducts to the selected Y line 38, and this line is connected to a bus 181 leading to an output buffer or input buffer in the input/output circuit 18.

These will add capacity and noise.

Therefore, it is necessary to provide a high logic level with a larger transistor 52.

According to the main features of the second embodiment of the invention, the sense amplifier 30 of FIG. 6 includes a special circuit for controlling the conductance of the load transistors 33 and 34 when φ2 goes high. I'm here.

The circuit of FIG. 6 is the same as the circuit of FIG. 3 except as will now be described.

Nodes 61 and 62 at the gates of load transistors 33 and 34 receive clock φ2 through gated capacitors 63 and 64.
digit lines 37 and 38 through transistors 65 and 66 connected to the source and clocked at φ3.
(see figure 4).

Clock φ3 does not switch from Vdd to Vss, and is approximately 8 times lower than (Vaa-¥1) and Vref.
(2) (When Vad is +12v) Varies between a low intermediate voltage.

As can be seen from FIGS. 7 and 4d, z2 also turns on transistor 52.

Capacitors 63 and 64 act as "booting" or bootstrap capacitors, producing high, drive voltages at the gates of load transistors 33 and 34.

This allows for rapid charging of the digit line to be returned to the "1" level, as seen from curve 56 in FIG. It also speeds up recovery.

Transistors 65 and 66 are at the intermediate level 6 of the φ3 clock.
7, the drive voltage of one of the nodes 61 and 62 of the gate of the load transistor on the zero side of the sense amplifier is discharged.

This significantly reduces sense amplifier power consumption.

As shown in FIG. 4a, lines 37 and 38 are precharged during 7 while φ1 and φ2 are zero and φ3 is high.

This time 61 and 62 are approximately (Vaa-2V□) or φ
Nodes 35 and 36 are charged to Vref.

When the column is zero, digit lines 37 and 38 are at Vref.
At the same time, φ3 becomes level 67, ie, an intermediate voltage.

This level 67 is set so that (a) the charge on the booting capacitor 63 or 64 connected to the "1" side of the sense amplifier does not discharge during the sense operation (b
) The charge on the booting capacitor connected to the other zero side was chosen to discharge as the voltage on the digit line decays during the sensing operation.

Since the voltage difference between digit lines 37 and 38 is determined by the charge distribution between dummy cell capacitor 46 and memory cell capacitor 42, and the selected X line 29-
1 or 29-2 goes high and dummy cell select line 27 goes high, the operation is the same as described above for period 58 of FIG.

Since φ1 becomes high level at time 55, amplification of the potential difference starts.

Then, at time 59, φ2 goes high, which boots the gate voltages of loads 33 and 34 and turns on transistor 52, causing the zero side discharge to rise as shown by curve 57 in FIG. will be sped up.

When the zero side digit line voltage force φ3 drops to a level Vt below the level 67, transistor 65 or 66 turns on and begins discharging the voltage on that side's booting capacitor 63 or 64, causing the load 33 or 34 is turned off.

For example, in FIG. 6, if node 35 is on the zero side (the selected cell on digit line 37 stores zero,
(the selected cell on digit line 38 is storing a ``1''), when X goes high, the voltage at node 35 changes to node 36.
The voltage will be slightly lower than that of .

Node 36 is represented by curve 56 in FIG. 5, and node 35 is represented by curve 57.

When φ goes high at time 55, the potential difference between nodes 35 and 36 is amplified for a period 58.

node 35 is lower than the gate level 67 of transistor 65 by V
When the voltage at node 61 drops by l, the voltage at node 61 begins to discharge.

When φ2 goes high at time 59, the amplification of the potential difference between curves 56 and 57 increases and node 36 begins to rapidly charge toward Vdd.

If node 35 falls to a level well below the level 67 of φ3 before φ2 turns on, node 61 cannot be booted and transistor 33 will not turn on.

If node 35 has not fallen sufficiently low when φ2 goes high, node 61 will be booted by φ2 until node 35 has fallen sufficiently to discharge node 61.

This results in a very short period of shutdown, i.e. the load transistor 33 and the transistor 51 connected to ground.
．． It happens that 52 become conductive at the same time.

There is a speed vs. power trade-off in choosing the timing of zl and z2.

If φ2 is slightly delayed when applied to booting capacitors 63 and 64 compared to that applied to transistor 52, and the digit line voltage on the zero side is at a level more than ■ below the level 67 of z3. Since the load on that digit line does not turn on, power is only dissipated by discharging the energy stored in the digit line capacitor.

However, the delayed φ2 to capacitors 63 and 64 increases device access time.

The fastest access is obtained when φ2 has no delay, but the power consumption increases slightly since the load on the zero side is turned on for a short period of time.

As already mentioned, fourthly, φ3 in the figure has a high level 68 and a low level 67 less than Vdd but greater than Vss.
This is a signal with two levels.

The high level 68 portion speeds up the voltage equalization of nodes 61 and 62.

If φ3 is replaced with a constant voltage of level 67, equalization becomes slower.

The third embodiment is a buffer using the concept of the embodiments described above.

The circuit of FIG. 7 passes through lines 91 and 92 to node 3 of FIG.
It is connected to 5 and 36.

In FIG. 7, an intermediate output buffer circuit 19 according to a third embodiment of the invention is shown.

This circuit consists of a pair of precharge and load transistors 83
a pair of drive transistors 81 connected in series with and 84;
and 82.

Sense nodes 85 and 86 between the drive and precharge/load transistors connect input transistors 87 and 8.
8, Y selection transistors 89 and 90, lines 91 and 92
3 to the bit line or column line halves 37 and 38 in FIG. 3 for the selected column.

Input transistors 87 and 88 are connected to ground through transistors 93 and 94 gated at φ1.

The gates of precharge/load transistors 83 and 84 are at node 9.
5 and 96, which are connected to transistor 97
and 98 from +Vdd and equalized by transistor 99.

All of these are gated with Z.

Nodes 95 and 96 connect capacitor 63 in sense amplifier 30.
A pair of gated capacitors 103 and 104 corresponding to and 64 boots to a higher level during operation of this circuit.

The lower parts of these capacitors are connected to beam 2Y.

Nodes 95 and 96 are shunt transistors 105 and 106 (corresponding to sense amplifier transistors 65 and 66).
to node 100 of the ground circuit.

Node 100 is connected through a pair of transistors 101 and 102 of different sizes and having a similar function to transistors 51 and 52 already described with respect to the sense amplifier.
The sources of drive transistors 81 and 82 are connected to ground.

Thus nodes 95 and 96 are connected to transistors 105 and 106.
Similarly, node 100 is used to ground the drive transistor.

Transistor 107 connects the gates of transistors 81 and 82 by 7 and connects nodes 85 and 86.

In the operation of intermediate output buffer 19 of FIG. 7, the initial conditions are established when RAS is high and φ is high.

This turns on transistors 97, 98, 99, and 107, charging nodes 95 and 96 to (Vdd-Vt) and equalizing them.

Precharge/load transistors 83 and 84 are turned on by precharging their gates.

Therefore, at this time nodes 85 and 86 are precharged to (Vdd-2V,).

These nodes are then equalized by transistor 107.

The voltage at nodes 95 and 96 is determined by curve 165 in FIG.
The voltage at nodes 85 and 86 is also represented by curve 166.

At time 71, nodes 85, 86, 95, and 96 are isolated because the column goes low and all precharged and equalized transistors are cut off.

Node 100 is isolated from ground because transistors 101 and 102 are turned off.

Transistors 105 and 106 therefore do not discharge nodes 95 and 96 even though their gates are held high by nodes 85 and 86.

In FIG. 9, when φ1Y goes high at time 117, node 100 goes to ground through small transistor 101.

Transistors 93 and 94 are then turned on, and the column lines applied to input transistors 87 and 88 are enabled.

For the addressed column line, transistors 87 and 90 are turned on by the Y signal from column decoder 13, and voltage 56 on lines 37 and 38
and 57 are applied to the gates of transistors 87 and 88.

This occurs before time 77 in FIG.

Since one of voltages 56 and 57 is higher than the other, node 8
One of 5 and 86 discharges faster through transistors 87 and 93 or 88 and 94.

In FIG. 9, the voltages at nodes 85 and 86 are at curves 118 and 1.
19 and the voltages at nodes 95 and 96 are represented by curves 120 and 121.

At time 122, nodes 95, 96, 85, 86°10
A voltage of zero is such that transistor 105 or 106 turns on and discharges node 95 or 96 on the zero side.

Starting at time 122 and before time 123, when φ2Y goes to a high level, curves 118 and 119 and curves 120 and 1
21, node 85 or 86 on the "1" side is charged from Vdd through transistor 83 or 84, and becomes "0".
As the side nodes are discharged through the drive transistors 81 or 82, they separate more rapidly.

At time 123 in FIG. 9, φ2Y goes high and the large transistor 102 begins to conduct, causing the "0" side transistor 81 or 82 to rapidly discharge toward Vss as shown by curve 124. .

For the "0" side and as shown by curve 125, transistor 105 or 106 rapidly discharges towards Vss.

The gate of transistor 105 or 106 on the "0" side is held high by a cross-connect to the opposite node 85 or 86, while the gate of transistor 106 on the "1" side
The gate of 05 or 106, since it is connected to node 85 or 86, and transistor 81 or 82 on the "0" side is clearly conducting by this point,
It will be at a level within ■1 of the potential at node 100.

The φ2Y clock also has the function of booting by connecting the level of node 95 or 96 of “1” through capacitors 103 and 104.

Charge is also coupled to the "O" side, but transistor 1 is already highly conducting through transistor 102.
It is discharged to ground through 05 or 106.

The output of intermediate output buffer circuit 19 is taken from nodes 95 and 96 in the embodiment of FIG.

Lines 110 and 111 connect these nodes to drive transistor 108 and ground transistor 10 clocked by φ2Y.
9 to produce data and daily output on lines 112 and 113.

Output pin 21 is driven by a pair of transistors 114 and 115 to provide a tristate output.

The input to this array from pin 20 is R/R on pin 22.
, a pair of transistors 116 that are turned on by a write signal derived from a command.

FIG. 10 shows another configuration of the third actual case of the present invention.

In this case nodes 85 and 86 are connected to input transistors 87 and 8
8, but directly to the column line halves 37 and 38 of FIG. 3 by lines 91 and 92 and transistors 89 and 90.

Thus, one of nodes 85 and 86 begins to discharge toward the zero side of the column line at the same time as Yr turns on, as shown by curve 167 in FIG.

The circuit of FIG. 10 also does not use ground transistor 102, but instead uses transistor 101, which is turned on at Oty at time 168, and is thick enough to provide a full logic level width output.

Since gated capacitors 103 and 104 provide φ1Y to nodes 95 and 96 at time 168, a clock corresponding to the φ2Y voltage is not required.

One other modification of this circuit is that the i load transistor 8
3 and 84 to precharge nodes 85 and 86.

This forces nodes 85 and 86 to reach level 119, which is the same level (Vdd Vl) at which nodes 95 and 96 are precharged.
is pre-charged.

Referring to FIG. 12, a detailed block diagram of the data and clock paths used during a memory read operation according to a fourth embodiment of the present invention in the storage device of FIG. 1 is shown.

A read operation is initiated externally by a specific signal sequence on the RAS, CAS, R/W lines.

This sequence excites clock generator 218, which sequentially outputs clocks φ4 and φ14 into a state signifying operation.

Signals φ4 and φ14 are received by sense amplifier 216 and differential read clock generator 219.

Sense amplifier 216 detects the information stored in the cells of the addressed row.
It also responds to signals φ4 and φ14 by placing this information on column line YO-Y127.

This special sense amplifier circuit is, for example, that of FIG.

Clock generator 219 responds to signals z4 and φ14 by initiating a clock generation operation.

Generator 219 has an output lead 265 that connects to column decoder 215.

Decoder 215 detects output voltage V65 on lead 265 and responds by gating the memory cell information on the selected column line onto signal line 226.

The signal on line 226 is then latched by input/output buffer 217 and detected externally on line 227.

The timing relationship between stabilizing sense amplifier 216 and gating the selected column line onto line 226 during the read operation described above is delicate.

If the selected column line is gated out onto line 226 before sense amplifier 216 has stabilized, an error will occur.

This is because the lead 265 has a large specific capacitance (
(all connected to the column line gate transistors), this capacitance can unbalance the sense amplifier and cause improper stabilization.

On the other hand, if the selected column line were to be gated out onto line 226 long after sense amplifier 216 had stabilized, the access time of storage device 210 would be unnecessarily increased.

The objective is therefore to provide a signal on lead 265 indicating the moment when sense amplifier 216 is stable, and to use this signal to immediately gate the selected column line onto line 265.

The function of generator 219 is to provide such a signal.

Referring to FIG. 13, differential read clock generator 21
A circuit diagram of nine specific embodiments is shown.

Generator 219 basically includes a bistable amplifier 250 and a differential voltage detector 260.

The purpose of bistable amplifier 250 is to provide a circuit with timing customizations very similar to that of sense amplifier 216, and the purpose of differential voltage detector 260 is to determine when amplifier 250 has reached steady state. It is to provide an output signal V65 to inform.

The amplifier 250 basically includes a set transistor 251,
Reset transistors 252.1 include a pair of load transistors 253, 254.1 pairs of precharge transistors 255 and 256, and a discharge transistor 257.

Set and reset transistors 251 and 252 are cross-connected to form set and reset nodes 258 and 259, respectively.

Nodes 258 and 259 are intentionally unbalanced by the choice of device ratio (channel length to width ratio).

Or if the cent clause 258 is reset clause 25
The capacity is slightly smaller than that of 9.

Alternatively, both of these imbalance techniques may be used.

Set node 258 is further coupled to load transistor 253 and precharge transistor 255; similarly, reset node 259 is further coupled to load transistor 254 and precharge transistor 256.

This configuration is exactly the same as that of a sense amplifier, and this similarity ensures that these two circuits have very similar timing characteristics.Differential voltage detector 260 is essentially a differential voltage detector. It includes a detection transistor 261 and a pre-charging transistor 262.

The drain 263 of the transistor 261 is connected to the set node 258
The '7'-to 264 is connected to the reset node 259.

Output lead 265 connects source 266 of transistor 261
to the drain 267 of the pre-charging transistor 262.
connected to.

The operating mode of the clock generator 219 is clock φ4 and φ.
14.

Clock φ4 is pre-charged transistors 255, 256,
262 and its function is to enable or disable the pre-charging operation.

Clock φ14 is transistors 253, 254, 257
connected to the gate of the clock generator 21 whose function is
9 and thereby generate the output clock signal V65.

Details of the sequence of clocks φ4 and φ14 and the voltages developed within clock generator 219 are shown in FIG.

During the initial time interval 270, clock φ4 is a logic “1”
state, and clock φ14 is in a logic "0" state.

The logic “1” state of clock φ14 is the transistor 256
is turned on, raising voltage V59 on node 259 to a level lower than the voltage of signal φ4 by a threshold voltage (Vt).

Similarly, voltage V58 on node 258 and voltage V65 on lead 265 are raised to a potential lower than the voltage level of clock φ4 by the threshold voltage.

During the second time interval 71, clocks φ4 and φ14 are both in a logic "0" state.

Therefore transistor 253.254.255.256
, 257° 261.262 are turned off and the precharged voltage V58 t V2Ot VO2 remains at the value obtained in the time interval 270.

During the third time interval 272, clock φ14 is at logic “1”.
” state, and the clock φ4 remains in the logic “0” state.

This initiates a memory cell sensing operation in sense amplifier 216.

This is because the clock φ4 is connected to the load transistor of the sense amplifier 216, and the clock φ4 also starts the clock generation operation in the clock generator 219 at the same time.

The details of this clock generation operation are as follows.

The logic "1" state of signal φ4 turns on discharge transistor 257, thus turning on set node 258 and reset node 25.
A discharge path is provided for 9.

Set node 258 discharges through transistors 257 and 251, while reset node 259 simultaneously discharges through transistors 257 and 251.
Discharge through 57 and 252.

However, as already pointed out, node 258 has a smaller capacity than node 259.

Therefore, the discharge rate of node 258 is faster than that of node 259.

When the voltage on node 258 falls to a level that is a threshold voltage above ground, transistor 252 turns off and node 252 ceases discharging.

During time interval 213, node 259 connects load transistor 25
Node 258 continues to discharge through transistors 257 and 251.

The potential difference between nodes 258 and 259 thus increases and soon reaches the threshold voltage.

During time interval 274, the potential difference between nodes 258 and 259 is greater than the threshold voltage, so differential voltage sensing transistor 261 turns on.

Therefore, the precharge on lead 265 is
．． 251.257, the voltage 65 drops almost to the ground potential level.

A negative change in V65 occurs within a few nanoseconds of the moment sense amplifier 216 latches up.

This fine time correlation is obtained because 1) the clock signal φ14 is connected to the clock generator 219 and the sense amplifier 216;
2) Both circuits employ bistable amplifiers of similar construction and therefore similar timing parameters.

3) When voltage V59 becomes larger than V58 by ■1, bistable amplifier 250 latches, 4) Bistable amplifier 25
This is because when 0 is latched, the differential voltage detection transistor 261 switches.

Lead 265 remains at a low voltage level until clock φ4 goes to a logic "1" state and clock φ14 goes to a logic "0" state.

When this occurs, time interval 275 is entered, in which the precharge voltage from time interval 270 is restored.

A fifth embodiment is an address buffer or latch circuit, such as row or column address latch 12 or 14 of FIG. 1, where seven row address buffers and seven column address buffers may be used. .

Referring to FIG. 15, a circuit diagram of an address buffer including a fifth embodiment of the present invention is shown. The basic elements of this embodiment are a set transistor 340, a reset transistor 345, a first clock a load transistor 350 receiving a second clock, a load transistor 355 receiving a second clock, an address input transistor 360, an equalization transistor 3TO1 precharging circuit 380, a pair of booting capacitors 390 and 391, a current sink circuit 400
, an output circuit 430.

Set transistor 340 and reset transistor 34
5 are cross-connected to set node 341 and reset node 346
form.

This cross-connected pair includes transistors 340 and 345.
or reset clause 3 by changing the size of
This can be done by making the capacitance of set node 346 slightly smaller than the capacitance of set node 341, or both.

The load transistor 350 receiving the first clock is connected to the set node 3 through a source 351 connected to the clock signal φ12 and a drain 352 connected to the set node 341.
Charge 41.

Similarly, a load transistor 35 receiving a second clock
5 charges the reset node 346 through a source 356 connected to clock signal φ12 and a drain 357 connected to the reset node 346.

The conductivity of the load transistor 350 is determined by the set control node 35.
3 by changing the voltage V53 on the voltage V53.

Node 353 is connected to the gate of transistor 350.

The voltage 53 is varied by a pre-charging circuit 380, a stepping capacitor 390, and a current sink device 400.

All three of these are connected to node 353.

Similarly, the conductivity of load transistor 355 is varied by varying voltage V58 on reset control node 358.

Node 358 is connected to the gate of transistor 355.

Voltage V58 is varied by pre-charging circuit 380, stepping capacitor 391, current sink device 400, and address input transistor 360.

Voltages V53 and V58 control the state of output circuit 430.

Output circuit 430 includes an output load transistor 431 having its gate coupled to node 353 and an output drive transistor 432 having its gate coupled to node 358.

Output signal Q is formed on lead 435 connecting the drain of transistor 431 to the source of transistor 432.

Similarly, output circuit 430 also includes an output load transistor 433 having its gate coupled to node 358 and an output load transistor 433 having its gate coupled to node 358.
and an output drive transistor 434 coupled to 53.

An output signal point is formed on a lead 436 connecting the drain of transistor 433 to the source of transistor 434.

The details of how the elements of the invention described above relate to each other are best understood by referring to the timing diagram of FIG. 16 in conjunction with the circuit diagram of FIG. 15.

During a first time interval 410, the circuit is initialized to a predetermined state from which a low level (typically T'!L) address signal IAD is continuously detected and converted to the MO8 voltage level. and latched.

Time interval 410 begins by raising clock signal φ2 to a high MO8 voltage level (typically about +12v) and lowering clock signals φ,2 and φ2□ to a low voltage level near ground.

Clock signal φ1□ is applied to load transistors 350 and 355
connected to the source.

Therefore, when signal φ12 is at a low voltage, load transistors 350 and 355 are connected to set node 341 and reset node 34.
No charge is supplied to 6.

Clock signal φ22 connects both booting capacitors 390
and 391 to one side.

Therefore, when signal φ22 is at a low voltage level, the voltages on set control node 353 and reset control tube 358 are at ground potential.

Clock signal φ2 is applied to gate 3 of equalization transistor 370.
It is connected to 73.

Transistor 370 has a source 371 connected to a set node 341 and a drain 372 connected to an IJ set node 346.

Therefore, the high MOS voltage level of clock signal φ2 turns transistor 370 on.

This equalizes the voltages on nodes 341 and 346.

Due to the operation of the current sink circuit 400, the magnitude of this equalized voltage is approximately near ground level.

This is because set node 341 is connected to the gate 406 of sink transistor 401, so whenever the voltage on set node 341 is greater than the threshold voltage, both transistors 401 and 345 turn on and reset This is because current is absorbed from the node 346.

Similarly, reset node 346 is connected to sink transistor 402
Therefore, the set node 346 is connected to the gate 407 of
Whenever the voltage above is greater than the threshold voltage, both transistors 402 and 340 turn on and sink current from set node 341.

Clock signal φ2 is also coupled to the gates of three transistors 381 in precharge circuit 380.

All three transistors are turned on in response to the high voltage level of signal φ2.

This operation is performed by the set control node 353 and the reset control node 35.
8 is precharged to a voltage level lower than the voltage level of signal φ2 by a threshold voltage.

This precharge level causes both load transistors to conduct slightly.

This charge is generated because the gates of transistors 403 and 404 are coupled to set node 341 and reset node 346, respectively, and the voltages on those nodes are near ground level, as previously discussed.

It is not absorbed by sink transistors 403 and 404.

The circuit is therefore stable such that nodes 353 and 358 have a precharge potential and nodes 341 and 346 are at a shear level.

The precharge potential on nodes 353 and 358 drives output signals Q and Q to low voltage levels.

Voltage V53 turns on transistor 434, thereby connecting lead 436 to ground.

Similarly, voltage V58 turns on transistor 432, thereby connecting lead 435 to ground.

During the second time interval 411, clock signal φ2 is at a low voltage level near ground.

In response, equalization transistor 370 turns off and precharge transistor 381 also turns off.

This circuit thus connects the low level address signal IAD
conditioned to start detecting.

The actual detection starts when the clock signal φ12 reaches a high MOS voltage level.

Typically, the actual detection begins as soon as clock signal φ2 goes low.

A third time interval 412 begins when clock signal φ1o goes to a high voltage level.

During this time interval 412, both load transistors 350 and 355 are slightly conductive.

The actual conductivity is determined by the precharge voltage on the set control node 353 and the reset control tube 358, as described above.

Conduction between load transistors 350 and 355 sets node 34
1 and reset node 346.

But the voltage on one part rises faster than the voltage on the other part.

If address signal AD is at a high voltage level of T0n, transistor 360 will remove a smaller amount of charge from reset node 346 and therefore the voltage on set node 341 will rise faster.

On the other hand, if address signal IAD is at a low voltage level, transistor 360 is turned off and therefore the voltage on reset node 346 rises faster.

As already mentioned, this means that the capacity of node 346 is
This is because it is smaller than that of .

During time interval 412, the voltages on nodes 341 and 346 continue to rise at different rates.

And eventually the voltage at one of those nodes is at node 405
reaches a threshold level higher than the voltage of .

When this occurs, time interval 412 ends and time interval 41
3 begins.

Typically, time interval 412 lasts approximately 10 ns.

During time interval 413, only one of nodes 341 and 346 continues to charge while the other node discharges.

If set node 341 exhibits a faster voltage rise during time interval 412, it will reach the threshold level described above, causing node 346 to discharge through transistors 345 and 401, and node 358 to discharge through transistors 403 and 401.
discharge through.

On the other hand, if portion 346 during time interval 412 exhibits a faster voltage rise, it reaches the threshold level mentioned above, causing node 341 to discharge through transistors 340 and 402 and node 353 to discharge transistors 404 and 402. Let it discharge.

Output signals Q and Q are responsive to the voltage levels on nodes 353 and 358, thereby indicating the state of human input signal IAD.

If node 353 discharges during time interval 413, transistors 431 and 434 are turned off, signal Q goes to a high voltage level, and signal Q remains at a low voltage level.

On the other hand, if node 358 discharges during time interval 413, then
Transistors 432 and 433 turn off, signal Q goes to a high voltage level, and signal Q remains at a low voltage level.

FIG. 16 shows this latter case.

At the beginning of time interval 413, the voltage difference between set node 341 and reset node 346 is very small.

Typically it is only around 500 mv.

However, this potential difference increases rapidly during time interval 413.

This is because the current sink circuit 400 rapidly sinks current from one node to ground, while the other node is connected to the booting capacitor 390.
The clock signal φ3 on the and 391 is applied to the load transistor 35.
0 and 355, thereby rapidly charging the other node.

When this voltage difference becomes large enough, the manual address signal IAD
Time interval 413 ends when is allowed to change state without having an adverse effect on the latching operation.

Typically time interval 413 only lasts approximately 15 ns.

During the fifth time interval 414, input signal IAD is free to change states.

However, the voltage on nodes 353 and 358 remains unchanged.

This means that - when node 353 or node 358 is discharged,
This is because it remains in the discharged state until the precharge potential is applied again.

Thus, nodes 353 and 358 reflect the latched input address signal IAD translated to the MO8 voltage level.

During the sixth time interval 415, clock signal φ2 is at a high voltage level and clock signals φ12 and φ22 are at low voltage levels.

This means that the pre-charging circuit 380 and the equalizing transistor 37
Excite 0.

Therefore, the voltage already latched on nodes 353 and 358 is dissipated, creating a precharge voltage for time interval 410.

The circuit then returns to its original state and is ready to perform other latching operations.

Referring to FIG. 17, a second configuration of the fifth embodiment of the present invention is shown.

The structure of this embodiment is the same as that of FIG. 15 with the following exceptions.

The source 382 of precharge transistor 381 is connected to clock signal φ2 instead of constant voltage source Vdd.

Gate 407 of sink transistor 402 is connected to clock signal φ22 instead of reset node 346.

The gate 466 of the sink transistor 401 is connected to the set node 3.
It is connected to the clock signal φ12 instead of the clock signal φ12.

A second address input transistor 365 is connected in series with input transistor 360.

The node 341 has a slightly smaller capacity than the node 346.

The operation of the circuit of FIG. 17 is illustrated in the timing diagram of FIG.

During time interval 426, precharge circuit 380 is energized by clock signal φ2.

This precharges nodes 353 and 358 to a level a threshold voltage below the voltage level of clock φ2.

Further, nodes 341 and 346 are precharged from the voltage level of clock φ2 to a level twice the threshold voltage.

The reason for precharging nodes 341 and 346 rather than discharging to ground in the first embodiment is that the clock signal φ12
turns off sink transistor 406 and clock signal φ22 turns off sink transistor 402, thereby opening the discharge path.

During this time interval, signals Q and Q both remain at low voltage levels due to the precharge voltages on nodes 341 and 346.

During time interval 421, the clock signal G, goes to a low voltage level, thereby terminating the precharge operation.

During time interval 422, clock signal φ1□ goes to a high voltage level, thereby initiating a sensing operation.

The sensing operation is performed by discharge nodes 341 and 346 of different rates.

This is the charging node 341 with different speeds like the first embodiment.
and 346 are the opposite.

If input address signal IAD is at a high T2L voltage level, transistor 360 turns off slightly and node 346 discharges faster than node 341.

If input address signal IAD is at a low voltage level, transistor 360 turns off and node 341
discharges faster than node 346 due to its smaller capacity.

When the voltage between the faster discharging node and node 405 becomes less than the threshold voltage, time interval 422 ends and time interval 423 begins.

During time interval @423, nodes 341 and 353 charge while nodes 346 and 358 discharge, or vice versa.

If node 341 is a faster discharge node, then node 341
and 353 are discharged, and signal Q goes to a high voltage level.

If node 346 is the faster discharge node, transistors 340 and 404 are turned off, nodes 341 and 353 are charged, nodes 346 and 358 are discharged, and signal Q is at a high voltage level.

FIG. 18 shows this latter case.

Charging occurs quickly. This is because the high voltage level of clock signal φ22 increases the conductivity of transistors 350 and 355.

Discharge also occurs rapidly.

This is because the high voltage level of clock signal φ22 turns on sink transistor 402.

Time interval 423 ends when the voltage difference between nodes 341 and 346, 353 and 358 becomes large enough to allow input address signal IAD to change state without adversely affecting the latching operation.

During time interval 424, input signal JAD changes state.

However, the voltages on nodes 353 and 358 are latched and signals Q and Q do not change.

During time interval 425, a pre-charging operation begins and the circuit returns to its initial state.

Referring to FIG. 19, a circuit according to a sixth embodiment of the present invention is shown.

Input terminal 510 is connected to the gate of a transistor 511 having a source-drain path connected between node 512 and ground or Vss (terminal 510 has a multiplexed address as shown in FIG. 1). (may be the RAS signal input 16 of the semiconductor storage device)
.

Node 512 is coupled to output node 514 through the source-drain path of transistor 513.

The purpose of this circuit is to detect the transition of the voltage on input terminal 510 from ``l'' to ``0'', or from a positive voltage to one ground potential for N-channel devices.

The voltage level of input terminal 510 is TTL level (approximately 2v
) or all MO8 logic levels (approximately +10 or +
12■).

When terminal 510 changes from +V to ground, output node 514
should change from ground potential to an MO8 logic level of approximately +Vdd or +10 to +12V as quickly as possible.

A "bootstrap" type load circuit is connected between node 514 and +Vdd line 515.

This load circuit includes a transistor 516 with a source-drain path connected between supply line 515 and node 514, a gated capacitor 517 connected from node 518 to node 514, and a transistor 519 with the gate connected directly to the drain. include.

This is a conventional boot load circuit, in which when node 514 becomes a positive potential, gated capacitor 517 acts to increase Vdd.
Since a voltage greater than 1 is applied to the gate of transistor 516, node 514 will reach +Vdd.

Node 512 is connected to the gate of transistor 520, which has a source-drain path connected between node 521 and Vss.

Since node 521 is connected to the gate of transistor 513, transistor 513 is turned off when transistor 520 conducts, and turned on when node 521 becomes threshold voltage Vt higher than node 512 and transistor 520 is sufficiently cut off.

Node 521 is precharged by transistor 522 connected to Vdd supply line 515.

A clock source 523 for the φP clock is coupled to the gate of transistor 522.

During operation of the circuit of FIG. 19, nodes 512 and 514 are already at a potential near ground prior to time 525 when FAS signal 526 on input 510 changes from positive to zero as shown in FIG. .

That is, during time interval 527, the gate of transistor 511 is pulled up by signal 526 and transistor 511 becomes fully conductive.

Transistor 513 is also held fully conductive by the precharge voltage applied to node 521 by φP voltage 528 (see FIG. 20) at gate 523 of transistor 522.

OP is at ground potential by time 525, and therefore transistor 522 is at ground potential before or from this time.
becomes non-conducting.

When the voltage 526 at input 510 drops near Vt, the 20th
Voltage 52 at node 512, as shown by curve 529 in the figure.
6 starts to increase.

At time 520, the voltage at node 512 reaches Vt and transistor 520 begins to turn on, thereby increasing node 52.
1 voltage 531 decreases and attempts to cut off transistor 513.

When the voltage between nodes 521 and 512 reaches Vt, transistor 513 is cut off.

At this point, node 514 begins to charge faster toward Vdd, as shown by curve 532 in FIG.

This is because the capacitance associated with node 512 no longer needs to be charged.

Without the speed-up circuit of the present invention, node 514 would charge like curve 533 and reach Vdd much later.

The operation of the bootstrap circuit associated with load transistor 516 is conventional.

Node 518 is pulled down by transistor 519 to approximately (Vdd
-Vt), so that transistor 516 is conducting (when node 514 is low), and gated capacitor 517 is in its opposite, high capacitance state.

When transistors 511 and 513 turn off and node 514 begins to go high, a positive voltage is coupled by gated capacitor 517 to node 518, driving this node to a potential level higher than Vdd, thus increasing node 51.
4 is charged to Vdd through transistor 516.

In FIG. 1, a sense amplifier and an address decoder,
The address latch and input/output control circuit are shown in Figures 4a to 4.
φ, φ, φ1. Multiple clock voltages such as φ2 are used.

- These clocks are initiated and timed by the RAS.

Therefore, the device must respond quickly to RAS1.

The clock multi-generator emits various clock signals and for this purpose, the RAS signal is output from pin 516 through a capacitor isolation circuit, which is the circuit of FIG. 19 according to a sixth embodiment of the present invention. Receive.

The clock generator responds to the positive or falling edge of RAS or Spring in a conventional manner since the timing is not critical.

That is, the source-drain path is connected to node 514 in FIG.
A transistor (but isolated from the circuit during positive-to-ground potential transitions) whose gate is connected between the input node 510 and ground performs this function.

The circuit of Figure 19 may also be used as an "edge trigger".

That is, the circuit produces an output in response to a positive to ground transition of the input signal and is not responsive to a ground to positive transition.

When the input signal goes positive, turning on input transistor 511, output node 51 will turn on unless node 521 precharges transistor 513 to turn on.
4 is not grounded.

In this way, φP can occur after the input becomes positive, resulting in an edge trigger circuit.

Referring to FIG. 21, an address buffer circuit according to the present invention is shown.

This sense circuit 614 includes a pair of drive transistors 631
and 632, the drains of which are connected through a pair of precharge transistors 633 and 634, typically about +l.
lv DC voltage Vdd supply line 635.

The sources of transistors 631 and 632 are connected together at node 636, which is connected to ground or Vss by two transistors 637 and 638, which are turned on at different times.

Transistor 637 is much smaller than transistor 638 and is turned on at φ.

On the other hand, the turn-on of transistor 638 takes place at ψa (the reason for this has already been explained with respect to transistors 51 and 52 in FIG. 3).

During period 640, as shown in FIG. 22a, transistors 633 and 634 are turned on by φh while transistor 639 shunts the sources of the two precharge transistors together.

Thus, a pair of sense nodes 641 and 642 are precharged to a high level during clock voltage φh.

Since this voltage φh is much higher than Vdd, the voltage drop across transistors 633 and 634 is very small.

Thus between φh or period 640 nodes 641 and 64
2 is charged to Vdd.

Small depletion mode devices 643 and 644 (approximately one-tenth the size of the precharge transistor) shunt transistors 633 and 634.

This is only to guarantee the operation of the first cycle, and the clause is for element 6.
It is charged very slowly from Vdd through 43 and 644, so this circuit can operate on the first φ pulse without the preceding φh.

Nodes 641 and 642 are transistors 632 and 63, respectively.
1 gate to provide a cross-connect for flip-flop or bistable operation.

Node 641 is connected to ground through a pair of input quadrant transistors 45 and 646 to provide an address signal input, and transistor 646 is turned on at φ, so the buffer does not respond until φ becomes positive.

The address signal from input terminal 612 is coupled to the gate of transistor 645 through series transistor 646, which is turned on by charging gate node 647 during φ and turned off after the address level is generated, as described below.

Thus, there is a time window in which this circuit accepts addresses.

The same gated capacitor elements 651 and 652 are connected to the node 64
1 and 642, and applies charge thereto when the delayed clock φd is generated.

To equalize the transient disturbances from the input signal AO,
A capacitor 648 connects the input line to node 642.

This capacitor has a capacitance comparable to the gate-drain capacitance of the transistor 645.

During period 640 of FIG. 22a, φh is high and φ and φd are low.

Transistors 637 and 638 are turned off by φ and φd, so drive transistors 631 and 632 cannot conduct.

Transistors 633, 634, and 639 are fully conductive with φh at a much higher level than Vdd.

So nodes 641 and 642 are charged to Vdd and curve 6
54.

Since transistor 646 is in the off state, this sense circuit does not respond to addresses.

The gates of gated transistors 651 and 652 are at a high potential, so the silicon under the gates is inverted;
Capacitors have large capacitance.

A sense period begins at time 655, where φh begins to fall and φ begins to rise.

When φh reaches Vdd, transistors 633°634
．． 639 is turned off.

When φ reaches Vt, transistor 637 begins to turn on.

This transistor is small and allows a small current to flow to initiate the sensing operation.

Nodes 641 and 642 begin to discharge through transistors 631 and 632 and discharge through node 636 and transistor 637 to ground.

As long as nodes 641 and 642 are high, both transistors 631 and 632 are on, and because one is larger, it conducts more current.

Therefore, if the address input is a logic "0" or Vss, this flip-flop will always rise in one direction.

In one embodiment, transistor 631 has a channel width-to-length ratio that is one quarter smaller than transistor 632, so that the latter conducts more current at quiescent input.

In this case, for a logic "0" input, transistor 63
2 conducts more current, so the final steady state the flip-flop reaches is transistor 632 conducting, transistor 631 cut off, node 641 at high potential and node 642 at low potential.

However, if input 612 is a logic "1", then φ
When Vt reaches Vt, both transistors 645 and 646 begin to conduct, causing node 641 to discharge faster than node 642 due to the path to ground through them.

And for an "l" input, the voltages at nodes 641 and 642 will resemble curves 656 and 657 in Figure 22b.

Node 641 falls faster than node 642, thereby lowering the gate voltage of transistor 632 and reducing its conduction.
Node 642 is held at a higher potential.

When φd reaches approximately Vt, transistor 638 begins to conduct, thus providing a lower resistance path to ground, thus causing one of transistors 631 and 632 to conduct a larger current, to the side that is zero. On the other hand, it creates a clearer zero level.

However, the sensing operation is facilitated by having only the higher resistance transistor 637 conductive during the initial portion of the sensing operation.

Also, when 93ct goes high, a charge pulse is connected through capacitors 651 and 652, which causes r
lJ-'[0! I is held at a high potential.

Transistor 631, or the null side, on the other hand, simply conducts this added charge to ground since it has become highly conductive by this point.

The operation of capacitors 651 and 652 and the crofter d prevent the voltage on the rlJ side from decaying to a very low level before being recharged at time 658.

As shown by dotted line 659, without this feature this voltage would have decayed to a very low level by this point and it would take time to recharge it.

Capacitors 651 and 652 therefore speed up the operation of this circuit.

The voltage at node 642 settles to a value Vtff1 less than Vdd and slowly charges back to Vdd due to depletion mode device 644.

The voltage at node 641 discharges towards Vss, approximately 50 n
This value is reached in s.

Nodes 641 and 642 with voltages shown by curves 656 and 657 in FIG.
It is connected to the gates of a pair of output ranges 61 and 662 in 16.

Each of the output transistors is shunted by a transistor 663 or 664 that is turned on and off at φ.

When φ is high, the output address on output nodes 665 and 666 is at Vss.

When Z is low, transistors 663 and 664 are off and the gates of transistors 661 and 662 are connected to nodes 641 and 642, so the state of node 665 or 666 is determined by nodes 641 and 642.

Line 615 is also loaded by transistors 667 and 668 to node 669 at the gates of transistors 671 and 672.
and 670.

The purpose of this circuit is to ramp up the voltage on one of nodes 669 and 670 to a voltage level much higher than Vdd, thereby forcing the address output, which should be "I", to a high level.

The drains of transistors 671 and 672 are tied to the φA clock, which goes high (Vdd) after dad as shown in FIG. 22c.

Nodes 665 and 666 are coupled through lines 675 and 676 to the gates of a pair of transistors 673 and 674, and these nodes are also output lines 617 where XO and XO are generated.

The outputs of transistors 673 and 674 are applied to node 647, which is the gate of input series transistor 646.

This node 647 is precharged through transistor 677 during φ.

A gated capacitor 678 connected to the φ clock adds charge to the time 647 when φ goes high, ensuring that transistor 646 is fully on at the beginning of the sense period. and 6
64 is on and the readdress outputs XO and XO are at Vss, nodes 665 and 666 are at Vss, so transistors 673 and 674 are in the cutoff state.

Node 647 is connected through transistor 677 (Vdd-Vt
) is charged.

During time interval 679 of FIG. 22c, before φ goes low and φA goes high, transistor 6
There is also no supply voltage for 71 and 672 i.e. φ
Since A is still zero, nodes 665 and 666 do not change.

Therefore, the voltage on line 615 is high enough to turn on transistors 661 and 662, but no current flows.

At this point the voltage at nodes 669 and 670 is the line 6 between φ
15 and charging from nodes 641 and 642 through transistors 667 and 668 to approximately (Vdd - Vt).

Transistors 667 and 668 have their gates tied to Vdd.
, so it works as a separation element.

By the time φA heads to the high 1 novel, nodes 641 and 64
2 have completed the sensing operation and have almost reached their final separation state as shown by curves 656 and 657.

For nodes 641 or 642 on the zero side, the corresponding nodes 669 or 670 are curved 681 in FIG. 22b.
The voltage is discharged to Vss through the transistor 667 or 668 as shown in FIG.

For example 642, the corresponding clause 669
does not discharge through transistor 667.

As shown by the curve 682 in the replacement sister 22d diagram, φA
When goes to a high level, it is lifted to a high level by the capacitor of transistor 671.

Transistors 671 and 672 are built with fairly large capacitances, and their gates are at a high level and their sources and drains are at a low level during the time up to φA, so these devices are acts as a capacitor.

For the "l" side, transistor 667 remains off, node 669 remains at the high l level, and the capacitance of transistor 671 also remains at a high value.

For the side that is "0", the Nidorandistaro 68 conducts, causing the charge at the node 670 to flow, and the transistor 6
The source-drain to gate capacitance of 72 is small, and very little charge is lifted to node 670 by φA.

The timing of the clock is set at the node on the zero side (for example, node 6).
70) should be such that φA discharges to about Vt as shown by curve 681 before turning on.

Otherwise, a noise pulse will be generated at the output node 665 of the XO.

One of the XO and XO double signals present at nodes 665 and 666 will go high upon the raising of the "l" node at either node 669 or 670.

When one of these is high, one of transistors 673 and 674 turns on, discharging node 647, turning off transistor 646, and the sense circuit no longer responds to addresses on line 612 until the next cycle. Do it like this.

As seen in Figure 23a, the "chip excitation" clock φ is a repeating clock with a cycle time of approximately l 50 ns.

As can be seen from Figure 23b, the address signal is
should be valid for.

The at 1/s force on pins 612 and 613 should be effective when φ goes to high 17 bells, and then only for a short time.

For reading, the manual data on pin 623 is
As shown in Figures 3c and 23d, the data output of one read operation should be valid for a short time after φ, as the R input on pin 625 should be.
It will be valid for the period shown in Figure 3e.

The circuit described herein can also be used without depletion mode elements 643 and 644, as storage system designs often do not rely on first cycle operation.

Capacitor 678 is not critical and can be flushed.

The two main features of this circuit are the capacitor 651
timing charging by and 652, and transistor 671
The operation of φA in and 672 and its effect on nodes 669 and 670 can also be used independently of each other.

That is, one is useful without the other.

The features of the present invention can be used not only for input circuits other than the AT1/S input, but also for cell array sense amplifiers and intermediate output buffers.

For example, data input to high-speed microcomputers requires circuits with such capabilities.

Various control and logic inputs to any type of MO8/LSI chip may also employ the present invention.

In a first embodiment, an MO8 integrated circuit type random circuit employing one-transistor memory cells arranged in rows and columns, with a bistable sense amplifier circuit in the center of each column. An access storage device is provided.

The load transistors in each bistable circuit have their gates applied with a clock voltage after the initial sensing period, and the initial sensing operation is performed with no load to the bistable circuit.

After this initial period, the load transistor is turned on by the booting capacitor.

The transistor that shunts the gate of the load element to the digit line has the function of turning off the load element on the side having a logic level that is zero.

The gates of the shunt transistors are each controlled by the voltage on the digit line on the opposite side of the sense amplifier.

In a second embodiment, instead of controlling the gate voltage, a fixed biased transistor that shunts the gate of the load element to the digit line turns off the load element on the side that has a logic level that is zero. Has a function.

A third embodiment employs an array of one-transistor memory cells in rows and columns, with sense amplifiers located in the center of each column, and an intermediate array with inputs connected to both sides of the column lines. A MO8 integrated circuit type random access storage device using an output buffer is provided.

The intermediate output buffer is a bistable circuit using the concepts of the first and second embodiments, in which the load transistor has a clock voltage applied to its gate after an initial sense period, and the column The initial sensing of data on the line is intended to occur without any load.

After this initial period, the load transistor is turned on by the booting capacitor.

The transistor that shunts the gate of the load element to the sense node has the function of turning off the load element on the side having a logic level of zero.

The gates of each of these shunt transistors are controlled by the voltage on the sense portion on the opposite side of the bistable circuit.

In a fourth embodiment, a read clock generator is provided for use in a semiconductor memory device.

This read clock generator uses the concepts of the first, second and third embodiments and includes a bistable amplifier and a differential voltage detector.

The bistable amplifier is driven open during the read cycle.

And it is similar to the transient operation of multiple sense amplifiers that detect binary information stored directly in memory.

The differential voltage detector is connected to a bistable amplifier and provides an output signal when the bistable amplifier is stable.

In the fifth embodiment, an address buffer circuit for use in a semiconductor memory device is provided.

This buffer circuit uses the concept of the first to fourth embodiments and includes a pair of cross-connected nodes having a set node and a reset node that are precharged to a predetermined level before detecting an input address signal. Contains transistors.

The set and reset nodes are connected to a pair of load transistors that are also precharged prior to the sense operation.

Actual detection occurs by further charging or discharging this set and reset node at a rate that reflects the state of the input address signal.

A current sink circuit detects this charging or discharging rate difference and selectively sinks the precharge on one load transistor thereby latching the state of the input address signal.

In a sixth embodiment, a circuit for isolating the input node from the output node includes two input transistors connected in series between ground and the output node.

The gate of the first of these is the input node, and the gate of this transistor is connected to the gate of a control transistor whose drain is connected to the gate of the second one of the input transistors. It is precharged before the time of going from logic "I" to logic "0".

When the first input transistor turns off due to an input signal going low, the control transistor turns off the second input transistor, isolating the output node and allowing more rapid charging.

In the seventh embodiment, MO8/LSI semiconductor RAM
A high speed address buffer circuit is provided for use in a storage device or similar device.

A pair of unbalanced, dynamically cross-coupled MO8 drive transistors is used to sense the address input during a short time window, and an internal address signal is generated from the state of the sense circuit.

The sense node has been precharged and equalized prior to that time window, and the node that should remain at a logic "L" level is the state of the sense circuit held high by a booting capacitor to which a delayed clock signal is applied. is sampled at some time after the delayed clock and high level address occur.

Although the invention has been described with respect to particular embodiments, this description is not intended to limit the invention.

Various modifications of the embodiments provided, as well as other embodiments of the invention, will occur to those skilled in the art upon reference to the description of the invention.

It is therefore intended that the following claims cover such modifications and other embodiments as fall within the scope of the invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor memory device using various embodiments of the present invention. FIG. 2 is an external view of an implementation of the apparatus shown in FIG. 1. FIG. 3 is an electrical diagram of the memory cell arrangement of the system of FIG. 1 employing the sense amplifier of the first embodiment of the present invention. Figures 4a-4 show the waveforms of the voltages present at each point in the systems of Figures 1 and 3 as a function of time. FIG. 5 is a detailed diagram of voltage on the digit lines versus time in the circuit of FIG. FIG. 6 is an electrical diagram of the memory cell arrangement of the system of FIG. 1 employing a second embodiment of the present invention. FIG. 7 is an electrical diagram of the memory cell arrangement of the system of FIG. 1 with an intermediate output buffer according to a third embodiment of the present invention. Figures 8a through 8i show waveforms displaying the voltage present at each point in the system of this embodiment of the invention as a function of time. FIG. 9 is a detailed diagram of voltage versus time at nodes in the intermediate output buffer of FIG. FIG. 10 and FIG. 11 show another example of the third embodiment of the present invention.
1 is an electrical circuit diagram of an intermediate output buffer according to two shapes and voltage versus time waveforms therein. FIG. 12 is a block diagram showing the connection of a differential read clock generator according to a fourth embodiment of the present invention used in the MOS, RAM device of FIG. FIG. 13 is a circuit diagram of a particular embodiment of the differential read clock generator of FIG. 12. FIG. 14 is a time waveform of the voltage applied to each node in the circuit of FIG. 13. FIG. 15 is a circuit diagram of a fifth embodiment of the present invention. FIG. 16 shows the voltage waveforms present at selected nodes in the circuit of FIG. FIG. 17 is a circuit diagram of another form of the fifth embodiment of the present invention. FIG. 18 shows the voltage waveforms present at selected nodes in the circuit of FIG. FIG. 19 is an electrical circuit diagram of a sixth embodiment of the present invention. FIG. 20 shows the voltage waveforms present in the circuit of FIG. 19. FIG. 21 is an electrical circuit diagram of a seventh embodiment of the present invention. 22a to 22c are voltage waveforms appearing at each point in the circuit of FIG. 21. FIGS. 23a to 23e show voltage-time waveforms appearing at various points in a memory system such as that shown in FIG. 1 employing the circuit shown in FIG. 21. Reference number, 10... Cell arrangement, 15... Address line, 23... Voltage supply pin, 24... Silicon chip, 25... Package, 26... Pin, 27...
...Dummy cell address line, 63...Gated capacitor, 64...Gated capacitor, 216
... sense amplifier, 218 ... clock generator, 2
19... Differential read clock generator, 390... Boot capacitor, 391... Boot capacitor, 52
3... Clock source (gate), 614... Sense circuit, 643... Depletion mode transistor.

Claims (1)

[Claims] 1. An array of memory cells arranged in rows and columns, a pair of cross-connected insulated gate drive transistors connected between half the column lines, and each A semiconductor storage device having a sense amplifier having an insulated gate load transistor for a drive transistor and a predetermined amount of supply voltage to the storage device, the semiconductor storage device comprising: (a) a switch connected to discharge the gate of the load transistor; The source-drain path of each of the switch devices is connected between a gate of the load transistor and a column line for that load transistor, the gates of the switch devices are connected together, (b) a capacitor for applying a voltage pulse to the gate of the load transistor, thereby causing one of the load transistors to be activated; A semiconductor memory device characterized in that it includes a supply means for turning on the other load transistors and having a voltage shunted to the column line so that the other load transistors do not turn on.