JPS5810874B2 - Hand Thai Hatsukousoshi - Google Patents
Hand Thai HatsukousoshiInfo
- Publication number
- JPS5810874B2 JPS5810874B2 JP49057583A JP5758374A JPS5810874B2 JP S5810874 B2 JPS5810874 B2 JP S5810874B2 JP 49057583 A JP49057583 A JP 49057583A JP 5758374 A JP5758374 A JP 5758374A JP S5810874 B2 JPS5810874 B2 JP S5810874B2
- Authority
- JP
- Japan
- Prior art keywords
- width
- crystal
- groove
- layer
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Description
【発明の詳細な説明】
この発明は、きわめて狭い電流集中領域幅を有する半導
体発光素子の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor light emitting device having an extremely narrow current concentration region width.
従来、直線上に狭い領域に電流を集中させる発光素子の
代表的例は、半導体レーザ素子である。Conventionally, a semiconductor laser device is a typical example of a light emitting device that concentrates current in a narrow area on a straight line.
このような半導体レーザの従来型を図で示すと第1図a
〜eのようになる。The conventional type of such a semiconductor laser is shown in Figure 1a.
It becomes like ~e.
第1図aは電極ストライプあるいは5i02ストライプ
と称されるもので、11は狭い幅で設けられた電極であ
り、電流集中は電極11の幅を狭める事によって達成し
ようとするものである。FIG. 1A shows what is called an electrode stripe or 5i02 stripe, in which 11 is an electrode provided with a narrow width, and current concentration is attempted to be achieved by narrowing the width of the electrode 11.
第1図すはいわゆるプレーナストライプと称する構造で
、最終層12aの電気伝導型をその直下の層と異なる型
とし、狭い必要部12b上のみ拡散法等により最終層1
2aと異なる電気伝導型とし、動作時には不要部はp−
n接合の逆バイアス状態とし、必要部12bに電流集中
をさせるようにしたものである。Figure 1 shows a so-called planar stripe structure, in which the electrical conductivity type of the final layer 12a is made different from that of the layer directly below it, and the final layer 12a is formed by a diffusion method or the like only on a narrow necessary portion 12b.
The electrical conduction type is different from 2a, and unnecessary parts are p- during operation.
The n-junction is placed in a reverse bias state, and current is concentrated in the necessary portion 12b.
実際には接合部附近における電流の流れている幅は、第
1図aにおいては電極11の幅より大きく、また第1図
すにおいては電流流入領域として働く必要部12bの幅
より大きくなり、いずれも10μm以下に制限すること
は困難である。In reality, the width through which the current flows in the vicinity of the junction is larger than the width of the electrode 11 in FIG. It is also difficult to limit the thickness to 10 μm or less.
これらを改善するためになされたのが第1図C〜eに示
すものである。What has been done to improve these problems is shown in FIGS. 1C to 1E.
すなわち第1図Cは電流集中に対し不要部13をイオン
打込み法で高抵抗としたプロトンボンバードメントスト
ライプであり、第1図dは同じく不要部14を化学的に
取り除いたメサストライプであり、さらに第1図eは不
要部15に拡散を行い、電気伝導型を変えたジャンクシ
ョンストライプと呼ばれるものである。That is, Fig. 1C shows a proton bombardment stripe in which the unnecessary part 13 is made to have high resistance against current concentration by ion implantation, and Fig. 1D shows a mesa stripe in which the unnecessary part 14 is chemically removed. FIG. 1e shows what is called a junction stripe in which the electrical conduction type is changed by diffusing into the unnecessary portion 15.
上記第1図c〜eのものは、それぞれ所望の電流制限領
域幅を得るために、不要部をイオン打込み法、化学的に
除去する法、まだは電気伝導型を変える法を行っている
。In the cases shown in FIGS. 1c to 1e above, in order to obtain the desired width of the current limiting region, an ion implantation method, a method of chemically removing unnecessary portions, and a method of changing the electrical conductivity type are used.
この場合、電流集中領域の幅の広さのうち、狭い側の限
界は、イオン打込み時の金属線太さ等のマスク幅、ある
いは写真製版法による場合はレジスト線の幅等で決まり
、通常5μm程度より幅を狭くする事は著しく困難であ
る。In this case, the narrower limit of the width of the current concentration region is determined by the mask width such as the thickness of the metal line during ion implantation, or the width of the resist line in the case of photolithography, and is usually 5 μm. It is extremely difficult to make the width narrower than the width.
この発明は上述の点にかんがみなされたもので、従来の
写真製版法により得られる幅のマスクを用いて化学研磨
等によって溝を作り、この際結晶の面方位を適切に選ん
でこの溝の断面を逆台形とし溝表面における幅より底面
における幅が狭くなるようにし、この底面を発光に寄与
する接合面に近接させ、一様に拡散法等によって低抵抗
層を形成し、溝底面に電流が集中することを利用するこ
とによって、従来の電流集中領域幅より著しく狭い電流
集中領域幅を得るようにしたものである。This invention was developed in view of the above-mentioned points. Grooves are created by chemical polishing, etc. using a mask having a width obtained by conventional photolithography, and the cross-section of the grooves is created by appropriately selecting the plane orientation of the crystal. The groove is made into an inverted trapezoid shape so that the width at the bottom is narrower than the width at the groove surface, and this bottom is brought close to the bonding surface that contributes to light emission. A low resistance layer is uniformly formed by a diffusion method, etc., and a current is applied to the bottom of the groove. By utilizing the concentration, it is possible to obtain a current concentration region width that is significantly narrower than a conventional current concentration region width.
以下図面によってこの発明を説明する。The present invention will be explained below with reference to the drawings.
第2図はこの発明を通常のGaAS−GaAlASヘテ
ロ接合レーザに適用した場合の実施例を示すもので、2
1は光学的活性層としてのp−GaAS薄層、22は前
記PGaAs薄層21への担体と光の閉じ込め効果を得
るだめのp−GaAlAS層、23は電極への低抵抗接
触を行うだめのp−GaA3層である。FIG. 2 shows an example in which the present invention is applied to a normal GaAS-GaAlAS heterojunction laser.
1 is a p-GaAS thin layer as an optically active layer, 22 is a p-GaAlAS layer for confining carrier and light to the PGaAs thin layer 21, and 23 is for low resistance contact to the electrode. It is a p-GaA three layer.
このような多層結晶はn−GaA3を基板として、スラ
イド式液相成長法により得られる。Such a multilayer crystal is obtained by sliding liquid phase growth using n-GaA3 as a substrate.
この結晶の表面に幅W、なる溝24を設ける。A groove 24 having a width W is provided on the surface of this crystal.
この場合、結晶表面に(001)を用いていれば、適当
な化学研磨液を用いることによって、結晶面指数〔11
1〕および(111)を得ることができる。In this case, if (001) is used for the crystal surface, the crystal plane index [11
1] and (111) can be obtained.
そして同図中θは約54°となり、結晶表面における溝
幅W1より底面幅W2を狭くする事が可能である。In the figure, θ is about 54°, which makes it possible to make the bottom width W2 narrower than the groove width W1 on the crystal surface.
この後、化学研磨用マスクを除去し、全面にZn(亜鉛
)等のp型となる不純物を熱拡散あるいはイオン打込み
法等により添加し、図中に斜線を施した低抵抗層25を
形成する。After that, the chemical polishing mask is removed, and a p-type impurity such as Zn (zinc) is added to the entire surface by thermal diffusion or ion implantation, thereby forming a low resistance layer 25 shown with diagonal lines in the figure. .
その後、電極26および27を設け、適当なヒートシン
ク等の上に組立て半導体発光素子を構成する。Thereafter, electrodes 26 and 27 are provided, and the semiconductor light emitting device is assembled on a suitable heat sink or the like.
動作状態では電流は溝24の底面における低抵抗幅Wに
はソ相当する光学的活性層、すなわちp−GaA3薄層
21の一部の領域28に電流が集中する。In the operating state, the current is concentrated in a region 28 of the optically active layer, that is, a part of the p-GaA3 thin layer 21, which corresponds to the low resistance width W at the bottom of the groove 24.
実験の結果によれば、W1=5μm。W2≒0とした場
合、1時間のZn拡散によりWを約1μmとすることが
できた。According to the experimental results, W1=5 μm. When W2≈0, W could be reduced to about 1 μm by Zn diffusion for 1 hour.
このような狭い領域に電流を集中させることにより、半
導体レーザのしきい値電流を著しく低減でき、表示用発
光ダイオードとはゞ同程度の数十mAの動作電流値とす
ることが可能となる。By concentrating the current in such a narrow region, the threshold current of the semiconductor laser can be significantly reduced, making it possible to achieve an operating current value of several tens of mA, which is about the same as that of a display light emitting diode.
そして、従来方式である第1図aおよびdの場合の様に
、電流密度が高く一番劣化し易い電流集中部分の直上に
電極を持つ必要がなく、さらに第1図dのように電流集
中部分側面が暴露されていないため、劣化が少なくなる
。Unlike the conventional method shown in Figures 1a and d, there is no need to place an electrode directly above the current concentration area where the current density is high and is most susceptible to deterioration. Deterioration is reduced because the partial sides are not exposed.
また、p−GaAs薄層21中における利得が一様にな
めらかに変化し、損失も一定のため、レーザ光の発振姿
勢が単一となり易いという特性をも有する。Furthermore, since the gain in the p-GaAs thin layer 21 changes uniformly and smoothly, and the loss is also constant, it also has the characteristic that the oscillation posture of the laser beam tends to be uniform.
なお、第2図の実施例においては、最上部層結晶として
p−GaA3層23全23全23これをn−GaAs層
とし、Znを拡散させた低抵抗層25の深さをこのn−
GaA3層より浅くすれば、より電流集中効果が犬とな
ることは、第1図すの特性を付加できることから明らか
である。In the embodiment shown in FIG. 2, the three p-GaA layers 23 (all 23) are used as the n-GaAs layer as the top layer crystal, and the depth of the low resistance layer 25 in which Zn is diffused is set to this n-GaAs layer.
It is clear that if the layer is made shallower than the three GaA layers, the current concentration effect becomes even stronger, since the characteristics shown in FIG. 1 can be added.
まだ、上記実施例はn−GaAlAS、p−GaAS、
p−GaAIAS、p(n)−GaAの4層よりなる半
導体レーザについてのものであったが、この他にn−G
aAS、p−GaAS。However, the above embodiments are based on n-GaAlAS, p-GaAS,
This was about a semiconductor laser consisting of four layers of p-GaAIAS and p(n)-GaA, but in addition to this, n-G
aAS, p-GaAS.
p−GaAlAS等の単一異種接合半導体レーザ等にも
同様に適用できる。The present invention can be similarly applied to a single heterojunction semiconductor laser such as p-GaAlAS.
さらに、溝に相当する部分の電極を除いて光を接合面に
垂直に取り出す構造とすれば、溝の形状および配列によ
り、記号あるいは文字を表示する発光表示素子にも適用
することかできる。Furthermore, if the structure is such that light is extracted perpendicularly to the bonding surface by excluding the electrodes in the portions corresponding to the grooves, it can also be applied to light-emitting display elements that display symbols or characters depending on the shape and arrangement of the grooves.
半導体発光素子材料としては、上述のようなGaAs、
あるいばGaAIAS系発光素子に限らず、GaP系、
あるいはInP系等他の結晶も用いうろこともちろんで
ある。As semiconductor light emitting device materials, GaAs as mentioned above,
In other words, it is not limited to GaAIAS-based light emitting devices, but also GaP-based,
Of course, other crystals such as InP-based crystals may also be used.
以上詳細に説明したように、この発明は多層結晶からな
る半導体発光素子において、結晶表面から結晶の面方位
選択性のエッチャントによりエツチングして、結晶表面
における幅よりも底面における幅が狭い少なくとも一本
の溝を形成し、この溝を含んで結晶表面より不純物を添
加して低抵抗層とし、前記溝の底面部を電流集中部分と
したので、前記溝の結晶表面における幅が、たとえ従来
技術による写真製版法による精度で一定以上におさえら
れたとしても、結晶の面方位選択性のエッチャントによ
るエツチングにより結晶の性質を利用して底面の幅を結
晶表面における幅より狭くすることができるから、電流
集中部分を従来よりも格段と狭くすることができ、した
がって、しきい値電流を低くすることができ、劣化も少
なくなる等の優れた特長を有する。As explained in detail above, the present invention provides a method for etching a semiconductor light emitting device made of a multilayer crystal by etching it from the surface of the crystal using an etchant selective to the plane orientation of the crystal, so that at least one layer having a width at the bottom surface is narrower than the width at the surface of the crystal is etched. A groove is formed, and an impurity is doped from the crystal surface including this groove to form a low resistance layer, and the bottom part of the groove is made into a current concentration area, so that the width of the groove at the crystal surface is Even if the accuracy of photolithography is kept above a certain level, the width of the bottom surface can be made narrower than the width of the crystal surface by etching with an etchant that is selective to the plane orientation of the crystal. It has excellent features such as being able to make the concentrated portion much narrower than in the past, thus lowering the threshold current and reducing deterioration.
【図面の簡単な説明】
第1図a〜eは電流集中効果を得るようにした従来の半
導体レーザをそれぞれ示す断面略図、第2図はこの発明
の一実施例を示す断面図である。
図中、21はpGaAs薄層、22はp−GaAlAS
層、23はp−GaAs層、24は溝、25は低抵抗層
である。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1E are schematic cross-sectional views showing conventional semiconductor lasers each having a current concentration effect, and FIG. 2 is a cross-sectional view showing an embodiment of the present invention. In the figure, 21 is a pGaAs thin layer, 22 is a p-GaAlAS
23 is a p-GaAs layer, 24 is a groove, and 25 is a low resistance layer.
Claims (1)
て、結晶表面から結晶の面方位選択性のあるエッチャン
トによりエツチングして結晶表面における幅よりも底面
における幅が狭い少なくとも一本の溝を形成する工程と
、前記溝を含めて結晶表面より不純物を添加して低抵抗
層を得る工程を有し、前記溝の底面部を電流集中部分と
したことを特徴とする半導体発光素子の製造方法。1. A method for manufacturing a semiconductor light emitting device made of a multilayer crystal, including the step of etching from the crystal surface with an etchant that is selective to the plane orientation of the crystal to form at least one groove whose width at the bottom surface is narrower than the width at the crystal surface. . A method for manufacturing a semiconductor light emitting device, comprising the step of adding impurities from the crystal surface including the groove to obtain a low resistance layer, the bottom part of the groove being a current concentration area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49057583A JPS5810874B2 (en) | 1974-05-21 | 1974-05-21 | Hand Thai Hatsukousoshi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49057583A JPS5810874B2 (en) | 1974-05-21 | 1974-05-21 | Hand Thai Hatsukousoshi |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS50150392A JPS50150392A (en) | 1975-12-02 |
| JPS5810874B2 true JPS5810874B2 (en) | 1983-02-28 |
Family
ID=13059862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49057583A Expired JPS5810874B2 (en) | 1974-05-21 | 1974-05-21 | Hand Thai Hatsukousoshi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5810874B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5330885A (en) * | 1976-09-03 | 1978-03-23 | Mitsubishi Electric Corp | Production of semiconductor light emitting element |
| DE2822146C2 (en) * | 1978-05-20 | 1982-11-25 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Heterostructure semiconductor laser diode and method for manufacturing a heterostructure semiconductor diode |
| JPS5846095Y2 (en) * | 1979-05-09 | 1983-10-20 | 日本精工株式会社 | Oil-impregnated sintered alloy parts |
| DE2933035A1 (en) * | 1979-08-16 | 1981-03-26 | Licentia Patent-Verwaltungs-Gmbh, 60596 Frankfurt | SEMICONDUCTOR LASER |
| JP3743718B2 (en) | 2002-11-14 | 2006-02-08 | 愛三工業株式会社 | Gas detector |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5622395B2 (en) * | 1973-10-17 | 1981-05-25 |
-
1974
- 1974-05-21 JP JP49057583A patent/JPS5810874B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS50150392A (en) | 1975-12-02 |
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