JPS5811137B2 - phase synchronized circuit - Google Patents

Description

Detailed Description of the Invention In so-called scanning Doppler unidirectional detection, a large number of omnidirectional antennas are placed on the circumference and sequentially scanned and received, and the arrival direction of radio waves is determined from the phase change of the received signal. Frequently, the intermediate frequency output is applied to a phase locked circuit to extract the orientation signal component.

In this case, if the phase change due to antenna switching is excessive or the output of a particular antenna becomes significantly small due to electric field disturbance of radio waves, the above phase locked loop (hereinafter referred to as PLL)
temporarily fails in synchronization, and the detected azimuth component has a significant amount of error.

The present invention provides a phase modulation detection circuit that maintains synchronization even in such a case and has little detection error.

Referring to FIG. 1, a shows the phase change pattern of the receiver output in the case of eight antennas.

Each time the receiving antenna is switched, the phase of the received signal changes stepwise.

However, in reality, due to bandwidth limitations in the receiver, the phase change of the receiver output requires some time, and the stepwise change usually has a slight slope.

If the PLL is synchronized to a signal with such a phase change, the phase of the vCO signal will follow the input, but there will be a slight delay, resulting in a phase difference with the input.
Correspondingly, a phase detector output like b is produced.

The PLL uses this voltage to control the frequency of vCO and causes its phase to follow the input.

The pulse height of b is normally proportional to the sine of the phase change of a.

Therefore, when the phase change is 90°, it is maximum, when it exceeds it, it decreases, and when it exceeds 180°, the polarity is reversed.

In this way, the phase detector output is not necessarily proportional to the phase step of the input, but as long as the PLL maintains synchronization, the phase of the vCO signal follows the input.
When the phase detector output becomes smaller, the pulse width increases to produce the necessary phase change.

However, if noise is superimposed on the receiver output, this may cause the phase step of the PLL input to exceed 180° or the output of the phase detector (hereinafter referred to as PD) to be negative when it should be positive. There is.

In such a case, vCO will be driven in a direction opposite to the normal one, resulting in a negative PD ratio output even though the phase step of the PLL input is positive.

The fundamental wave component of the signal b has azimuth information, but if the polarity of any of the pulses is reversed as shown above, the phase of the fundamental wave component will be significantly different, resulting in a significant azimuth error.

Additionally, if electric field disturbances are present at the antenna installation location, the output of a particular antenna may be significantly reduced.

In such a case, the PLL input corresponding to that antenna decreases significantly, so the PD ratio output becomes small, and the phase of vCO cannot be adjusted as much as necessary during the connection period of that antenna.

Therefore, when switching to the next antenna, the PLL input and V
The phase of CO becomes extremely large, exceeding 180°, and may produce an output with a polarity opposite to the normal PD ratio output.

In this case as well, the PD ratio output fundamental wave phase will be significantly different, resulting in a large azimuth error.

The above-mentioned noise effect occurs randomly and the direction fluctuates greatly, but it is averaged over a long period of time and it is possible to discover the true direction, but the latter electric field effect constantly occurs at a specific antenna. Therefore, it is impossible to discover the true direction by averaging.

In order to solve the above-mentioned difficulties, it is sufficient to predict the phase change of the input signal and change the phase of the PLL and VCO.

In such a case, the phase difference between the input and vCO is always kept at a small value, so it is rare for a PD ratio output of opposite polarity to occur, and even if the input signal is temporarily interrupted, vCO is still under predictive control, so the input signal is When it appears, the phase error is small and the above-mentioned problems can be solved.

FIG. 2 is a diagram showing the principle of the present invention.

It is well known that the phase of the input signal and the VCOl is compared with the PDl of the PLL1, and the VCOl is controlled so that the PD1 output becomes approximately 0, thereby achieving phase synchronization between the VCOl and the input signal.

At this time, as described with reference to Figure 1, a signal corresponding to the differential of the phase change of the input signal appears in the PD1 output, and this includes the fundamental wave component of the modulation component of the original signal. If this signal is added to the second PLL2 and the phase of the VCO2 is synchronized with it, this vCO2 signal will be almost in phase with the phase modulation component of the input signal, and even if the input signal is intermittent or changes in amplitude, the input signal will remain unchanged. A stable signal with phase changes can be obtained.

In the present invention, as shown by the dotted line in FIG. 2, a part of the signal of the VCO2 undergoes a phase shift of approximately 90 degrees and is superimposed on the control of vCOl.

Its operation is as follows.

Assume that PLL1 is synchronized with the input, and first consider the case where the input signal is unmodulated. Since the phase of vCOl must not change, the e
l appears.

Since e3 has a 90° phase difference with e2 of PLL2, elj
e2 also has a 90° phase difference, and the PD2 output is 0.

That is, adding 03 to vCOl does not affect the operation of PLL2.

When the input signal has phase modulation, a component corresponding to this is superimposed on el, and the output of PDl becomes as shown in FIG. 1C.

This addition causes PLL2 to perform a synchronous operation in the same way as without e3.

However, in this case, CO1 is predictively controlled by e3 in the same direction as the phase change of the input signal, so even if the input signal is cut off for a short time, when it reappears, the phase difference will be excessive and the phase synchronization will be lost. Confusion is rare.

The analysis of the above operation is as follows.

The sensitivity of PDl is Kd (v/rad), the sensitivity of VCol is K
o(rad15-V) and the phase of the input signal is φ(rad
), where S is the Laplace operator.

KdKo is the cutoff angle frequency of this PLL system, which is ωc(
rad/S) and the fundamental wave angular frequency of change in φ is ω. Since it is normally ω(ωC), the term in the denominator can be ignored.

That is, it can be seen that the output of PDl is the product of Kdφ multiplied by j- (differential) minus 03.

As mentioned above, since e3 has a 90° phase difference with e2 of PLL2, its operation is not affected, and PLL2 operates so that e2 and φ are in phase.

However, strictly speaking, due to the influence of the denominator term in equation (2), ω
/ωC is accompanied by a phase lag, so it is desirable to perform phase correction corresponding to this on e2 or e3.

This correction may be performed between PD1 and PD2 or between e2 and e3.

Figure 3 shows another embodiment of the present invention in which 90° phase correction is performed using PD1.
→ This is a case where it is performed between PD2.

If an integrator is used as a 90° phase shift circuit, the harmonic components of the PD1 output will be attenuated, so PD2 will operate more reliably, and even if the signal applied to PD2 from vCO2 contains some harmonic components, The influence is reduced and a highly accurate PLL system can be realized.

The circuit marked φ between VCO2 and vC01 is the PLL described above.
This is to correct the phase lag in 1, which is 9
It may be arranged in series with the 0° phase circuit or the phase of e2 of PD2 may be corrected.

The above has described the case where VCOl is superimposed and controlled using a part of the output of VC02, but the same effect can be expected by controlling the phase of the input signal of PDl, but it is slightly more complicated.

[Brief explanation of drawings]

The drawings show an embodiment, and FIG. 1 is a signal waveform diagram, and FIGS. 2 and 3 are block diagrams of the main components.

Claims (1)

[Claims] 1. In a circuit that obtains a signal that is phase-synchronized with the modulated component by synchronizing a first phase-locked circuit with a signal subjected to phase modulation and synchronizing a second phase-locked circuit with the output of the phase comparator, this output A phase synchronized circuit characterized in that a phase correction circuit is inserted so that a part of the signal is superimposed on the VCO signal of the first phase synchronized circuit so that the effects thereof are orthogonal to each other in a second phase detector.