JPS5811714B2 - Jiki Bubble Memory Souch - Google Patents

Description

[Detailed description of the invention] The present invention relates to a magnetic bubble memory device.

The above memory device has been developed to be used as a small file memory in digital computers, terminal equipment, and the like.

The characteristics of bubble memory devices for such applications are that they are faster than magnetic drums or disks, are cheaper than semiconductor IC memories, and are nonvolatile, which is difficult to achieve with semiconductor IC memories (the stored information remains intact even when the power is turned off). The objective is to show the characteristics that are retained.

However, in order to maintain the third characteristic of non-volatility, it is necessary not only to simply retain the stored information but also to memorize the relationship between the storage location and the storage address.

The conventional magnetic bubble memory device of the major liner loop type requires an extra expensive non-volatile memory to store the above-mentioned correspondence between storage locations and storage addresses.

For example, in the December 1973 issue of Monthly Computer,
Explanatory articles stored from pages 42 to 150 [In Figure 3 of Bubble Memo 1, which has already been used on a trial basis, a timing loop was provided in the bubble chip to memorize the above-mentioned correspondence; The cost was high because it required equipment and timing gates.

Therefore, there was a defect that made it difficult to achieve significant cost reduction.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that eliminates the above-mentioned defects and makes it possible to economically realize a magnetic bubble memory device.

FIG. 1 is a block diagram of a conventional magnetic bubble memory device having a major linear loop memory configuration.

The magnetic bubble material is placed in drive coils 2 and 2' on a substrate 10 sandwiched between two parallel permanent magnet plates 1.

The drive coils 2 and 2' are supplied with sinusoidal currents having phases different from each other by 90° from the sinusoidal current drive rotation 3.

This drives a rotating magnetic field into the magnetic bubble material.

A clock pulse generator 4 controls the operating speed of the sinusoidal current driven rotation 3 and generates one pulse per period of the rotating magnetic field.

A binary counter (semiconductor IC) 8 counts the pulses.

A comparator (semiconductor IC) 9 generates an output signal of '1' when the contents of the address register 7 and the contents of the binary counter 8 match.

A gate drive circuit 5, which controls the path of the magnetic bubble in the magnetic bubble material, is responsive to the output signal of the comparator 9.

Leads from substrate 10 to detection circuits 6-1 to 6-m lead to magnetic bubble material in drive coils 2 and 2'.

A detailed explanation of how the gate drive circuit 5 and the detection circuits 6-1 to 6-m act on the magnetic bubble material will be given after the explanation of FIG.

FIG. 2 shows m major liner loop memory blocks arranged on magnetic bubble material 11. FIG.

In the m-th memory block 11-m, one tie loop (magnetic bubble propagation path) 13-m and one liner loop (magnetic bubble propagation path) 12 are coupled via a gate line 14. .

A bubble generator G, an eraser A, and a magnetic bubble sensing element S for converting magnetic bubbles into electrical signals are placed on the trigger loop 13-m.

The sensing element S on the m-th trigger loop 13-m is connected to the external detection circuit 6- through the output terminal 17-m on the board 10.
is connected to m.

A gate line 14 that controls the transfer of magnetic bubbles between the liner loop 12 and the tie loops 13-1 to 13-m is connected to an external gate drive circuit 5 through an output terminal 15 on the substrate 10.

In each memory block of FIG. 2, digital information is stored in one liner loop 12 in the form of magnetic bubbles.

When the rotating magnetic field is driven, the magnetic bubbles on each liner loop 12 move simultaneously in the direction of the arrow.

At the same time, the magnetic bubbles on the tie loops 13-1 to 13-m also move.

At the time of writing, a magnetic bubble is generated from the generator G for write information of 1''.

Not generated for “0”.

An example of a bubble for the written information is m tabulator loops 13-1 to 13-m, which proceed to the right side of the gate line 14 according to the arrow.

When a current is supplied from the gate drive circuit 5 to the gate line 14, the bubble examples on the right side of the gate line 14 are transferred all at once to the liner loop 12 on the left side.

In many cases, the above transfer is performed twice for each set of write information.

Therefore, the magnetic bubbles for one set of write information are stored vertically arranged in two columns on all the liner loops 12.

If the bit length of the liner loop 12 is 2n, n sets of information can be stored.

When reading information, a magnetic bubble corresponding to the information of the requested page address receives a rotating magnetic field in one liner loop 12 in each block 11 and moves to the gate line 14.
When it comes to the immediate left side of the gate line 1 from the gate drive circuit 5
4, the magnetic bubbles are transferred all at once to the tie loops 13-1 to 13-m.

As in the case of writing, the information at each address is transferred twice for reading.

The array of magnetic bubbles once transferred to the titer loops 13-1 to 13-m is further applied with a rotating magnetic field, sent to the sensing element S, and converted into an electric signal.

When clearing information, the magnetic bubble string at the designated address is moved to m timer loops 13-1 to 13-m and then erased by eraser A.

From the above, it can be seen that it is possible to read and write page information in which m bit strings of 2 nobits are arranged in parallel.

However, in order to monitor where in the liner loop 12 the magnetic bubble corresponding to the requested page address information is located, the number of moving steps of the magnetic bubble in the liner loop 12 is counted, and the bit length of the liner loop 12 is calculated. Binary counter 8 (first
Figure) is required.

The contents of the binary counter 8 (binary code) and the address register 7 are used to control the time at which current is supplied from the gate drive circuit 5 to the gate line 14 when specifying a request address accompanied by a further read or write command. Comparison result with the contents of (only when there is a match)
A comparator circuit 9 that outputs σ') is also required.

The binary counter 8, address register 7, and comparison circuit 9 for such addressing can be realized with commercially available semiconductor ICs.

However, when the memory board 10 is attached and removed, when the memory block 11 instantly changes to another one due to the selective drive of the rotating magnetic field, when the correspondence between real addresses and virtual addresses for virtual memory is switched, If the power is cut off, the relationship between storage locations and storage addresses within the liner loop 12 is not immediately restored.

Therefore, in conventional magnetic bubble memory devices, a nonvolatile memory that separately stores the contents of the binary counter 8 and a timing loop with a separate sensing element S are prepared in the bubble chip for such cases. It was necessary to keep it.

However, this makes it difficult to significantly reduce device costs.

According to the present invention, as shown in FIG. 3, each tie loop 13 is connected via a gate line 14 to an inner loop 18 for addressing in addition to the small nano-dove 12 for storage information.

No separate sensing element S is required in the addressing inner loop 18.

Furthermore, as shown in FIG. 5, an initialization circuit 19 is provided which can set the address information read from the address inal loops 18-1 to 18-m to the binary counter 8.

FIG. 3 shows a major linear loop memory configuration used in the present invention.

The difference from FIG. 2 is that an inner loop 18 for addressing is provided for each major linear loop memory block, and its position is indicated by a star at the left end.

Page information A or general storage information is stored in the storage information liner loop 12 that does not have a star on the left end.3 Note that when the power is turned off or the storage medium is replaced, all page information is stored in the liner loops 12 and 18. It is better to put it back.

Further, it is preferable that the address inner loop 18 be placed closest to the sensing element S.

Other points may be the same as in FIG. 2.

FIG. 4 shows the address information stored in the address inner loops 1B-1 to 1B-m as an arrangement pattern of magnetic bubbles.

Liner loop 1 for each storage information when m=6, 2n=64
One bit of the 64 bits in 2 can be specified by address information obtained by one transfer (from the liner to the tier) from the inal loops 18-1 to 18-6, which use six addresses.

In loop 18-1, 1" and 0" alternate, and in loop 18-1
2 has two l' and 'O', and loop 18-3 has four
8 pieces each, loop 18-4, 8 pieces each, loop 18-5
In the loop 18-6, 16 pieces are arranged alternately, and in the loop 18-6, 32 pieces are arranged alternately.

This corresponds to an address pattern of 64 pages.

Generally, as the liner loop length 2n increases, it is necessary to increase m.

Inaloop 18 that uses one address for the customer memory block
When using 2n, it is convenient to select 2m.

When 2n is greater than 2m, the number of address inaloops 18 in each memory block may be two or more.

If 2n is smaller than 2m, use the address inaloop 1.
8 can be used partially.

FIG. 5 shows an embodiment of the device configuration of the present invention.

In this figure, only the first bit of m bit strings obtained from m memory blocks on the board 10 through terminals 17-1 to 17-m and detection ports 6-1 to 6-m is used as actual address information in the latch circuit. Captured by 23.

The timing circuit 24 uses the output signal of the comparison circuit 9 to control the latch circuit 23 to capture only the first m bits.

Initialization circuit 19 includes switch 21 and switch 2.
0-1 to 0-m are included, and a set button 22 for controlling them is included, and when the memory board 10 or memory block 10 is replaced or the power is cut off, the reset button 22 is pressed to restore the relationship between the storage location and storage address. can be done.

That is, normally the switches 20-1 to 20-m and the switch 21
is lying on the left side, but when the reset button 22 is pressed, the sine wave current drive circuit 3 operates together with the clock pulse generator 4', and the unknown contents of the binary counter 8 and the contents of the appropriately set address register 7 are activated. Comparison circuit 9 compares them.

When a match output signal is output from the comparison circuit 9, a gate current is supplied from the drive circuit 5 to the gate line 14, page information specified by some address is output from the detection circuits 6-1 to 6-m, and the first m bits are The signal is captured by the latch circuit 23.

At the same time, the switches 20-1 to 20-m and the switch 21 fall to the right (as shown).

Thereby, the contents of the binary counter 8 are changed until they match the contents of the latch circuit 23.

If they match, a match output signal from the comparison circuit 9 causes the switches 20-1 to 20-m and the switch 21 to return to the left side.

As a result, the address of the page information called by the timer loops 13-1 to 13-m is restored to the binary counter 8.

After that, release the reset button 22 and it will work.

However, the clock pulse generator 4' continues to operate until it receives a matching output signal from the comparison circuit 9 again, and transfers the magnetic bubbles in the timing loops 13-1 to 13-m to the liner loop 12 and the liner loops 18-1 to 18-m. The re-sinusoidal current drive circuit 3 is operated to return the current.

Thereafter, necessary page information can be obtained from the detection ports 6-1 to 6-m by specifying the address from the address register 7.

In addition, in this case, the loop length of Taija loop 13 is also 2n.
It is assumed that the magnetic bubble always returns to the original position of the mini-dob after one cycle of the titer loop 13.

As explained above, according to the present invention, a non-volatile memory (a timing loop is used as a bubble) that stores the relationship between storage locations and storage addresses necessary when the power is turned off or when selectively replacing the memory block 11, etc. There is no need to provide an extra sensing element (even if it is provided within the chip).

Use the initialization circuit and address instead of the initialization circuit 1.
8-1 to 8-m are required, but their cost is sufficiently small to be ignored compared to the installation of non-volatile memory.

In the above detailed description of the present invention, the initialization circuit 19 is arranged between the comparison circuit 9 and the latch circuit 23, but it may also be directly connected to the binary counter 8.
Further, the contents of the latch circuit 23 do not necessarily all need to be used by the initialization circuit 19, and the above description does not limit the scope of the present invention in any way.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional magnetic bubble memory device, FIG. 2 is an explanatory diagram of a tie liner loop memory block on the magnetic bubble material used in FIG. 1, and FIG. 3 is a tie liner loop memory block used in the present invention. An explanatory diagram of the loop memory block, Figure 4 is an example of magnetic bubble arrangement in the inner loop used for addressing,
FIG. 5 shows an embodiment of the device configuration of the present invention. In FIG. 1, 1 is a permanent magnet plate, 2 and 2' are drive coils, 10 is a memory board, 6-1 to 6-m are detection circuits, and 5 is a gate drive circuit. In FIG. 2, 12 is a liner loop for storage information; 13-
1 to m are tie loops, 11-1 to m are memory blocks, and in FIG. 3, 18-1 to m are inner loops for address use. In FIG. 5, 23 is a latch circuit, 7 is an address register, 19 is an initialization circuit, 8 is a binary counter, and 9 is a
1 is a comparison circuit, 1' is a clock pulse generator, and 3 is a sine wave current drive circuit.

Claims (1)

[Claims] 1. A plurality of measurer loops configured on a magnetic bubble material to which a vertical bias magnetic field and an in-plane rotational magnetic field are applied, and a plurality of storage information and address liners coupled to each measurer loop via a gate line. loop and
a binary counter placed outside the magnetic bubble material to count the number of movement steps of the magnetic bubble in the liner loop; and a binary counter connected to the binary counter, the contents of the binary counter being set to the requested address. A magnetic bubble memory device comprising a comparison rotation for supplying current to the gate line when a match occurs, and an initialization rotation for setting address information detected from a plurality of the address inner loops to the binary counter.