JPS5811720B2 - shift register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (Insu
rated Gate Field Effeet T
ran-sister (abbreviated as IGFET or MOS)
Although it is called FET, it will be abbreviated as FET hereafter.

) regarding a shift register configured using

Shift registers used in memory circuits or counters in electronic desktop calculators, etc., occupy a small area per bit within a semiconductor chip, but because they are used in large numbers in sequential cascade connection, the semiconductor chip becomes larger and there is always a need to improve yield. The issue was cost reduction.

Recent developments in integrated circuit technology have made it possible to miniaturize small electronic devices, but in the case of the shift register mentioned above, the number of FETs required to configure a 1-bit register (D-type flip-flop) is increasing. Since conventionally there have been many components, it is necessary to reduce the number of components per function in order to reduce the chip area and reduce costs.

FIG. 1 shows a conventional logic circuit which functions as a 1-bit D-type flip-flop of a shift register formed as a complementary circuit.

Before explaining this logic circuit, let me explain about FETs. P-channel type (hereinafter referred to as P-type) FETs also have
A channel-type (hereinafter referred to as N-type) FET is also an active three-terminal device that controls the conductivity of a current path (channel) inside or on the surface of a semiconductor using an electric field perpendicular to the current direction. On the other hand, in the latter case, current flows between the source and drain using electrons as carriers.

In general, the source and drain of an FET are bidirectional elements with almost no difference in terms of electrode structure, like the collector and emitter of a bipolar element (transistor), and the distinction between the source and drain is only apparent in circuit operation.

Since we will be dealing with a complementary symmetrical circuit with a P-type FET here, the output side will be the drain, and the bias power supply side (ground side) will be the source.

Then, VDD is set as a positive power supply and VSS is set as a negative power supply (grounded), and in order to explain the operation, VDD is set to a "1" level potential and vSS is set to a potential of the u0v level, so that so-called positive logic is used.

In the first time, a transfer gate 2 in which P-type and N-type FETs are connected in parallel is connected to input terminal 1, and each FET is connected to input terminal 1.
A clock pulse φ is applied to the gate of ET.

φ is supplied.

Reference numeral 3 denotes an inverter in which P-type and N-type FETs are connected in series between the power supplies VDD and VS2, and the output terminal of the transfer gate 2 and the gate of each FET of the inverter 3 are connected. A series circuit of a transfer gate 4 and an inverter 5 is connected between the input and output terminals (A-B group) as shown in the figure.

The input information IN supplied to the input terminal 1 is shifted by half a bit by these transfer gates 2, 4 and inverters 3, 5, and accordingly, the transfer gate 6.8 and inverter 7.9 similarly shift the input information IN by a half bit. By configuring this, an output signal OUT shifted by one bit can be obtained from the output terminal 10.

Note that each connection point A, B, C, DE, etc. in the figure has gate capacitance or diffusion capacitance CA.

CB, co, .

In order to configure a conventional 1-bit shift register in this way, a total of 1
Since eight FETs are required, the area occupied within the chip becomes considerably large, and the power consumption during operation also becomes large.

Next, the operation of this shift register will be briefly explained with reference to FIG.

In FIG. 2 a=i are clock pulses 1 and 1, respectively. φ, input information IN, voltage waveform at connection point A-E and output signal OU
It is T.

When input information IN is supplied from input terminal 1, transfer gates 2 and 8 become conductive (on) at the timing when clock pulse φ is at the "1" level, and transfer gates 4 and 6 become non-conductive (off). Therefore, for example, data D1 of input information IN is stored in the capacitor CB of the connection point A, and the data inverted by the inverter 3 is stored in the capacitor CB, further inverted by the inverter 5, and also stored in the capacitor co of the connection point C. be remembered.

Next, when φ=O (6=1), transfer gate 2
, 8 are turned off and 4 and 6 are turned on, so that the data on CB is transferred to the capacitor CD at the connection point, is inverted again by the inverter, and is read out to the output terminal 10.

At this time, Dl is inverted by the inverter 9 and stored in the capacitor C8 at the connection point E, and the data stored in the capacitor C6 is transferred from the transfer gate 4 to the capacitor CA at the connection point A.
will be rewritten.

That is, while the data D1 is being read out from the output terminal 10 as an output signal, a stable memory circuit is formed that connects the connection points A-B→C-A, and D1 is held.

Next, at the timing of clock pulse φ=L (I=0), transfer gates 2 and 8 are turned on and transfer gates 4 and 6 are turned off, and new data D2 is written from input terminal 1 to capacitor CA at connection point A, as described above. However, since the transfer gate 8 is on at this time, the old data D1 stored at the connection point is stored in a stable storage circuit that connects the connection point D → output terminal OUT, subsequent point → D. is maintained by the formation of

In this type of shift register, data is written when the clock pulse φ is at the "1" level, and data is read when the clock pulse φ is at the u1v level, and is used as a storage circuit by cascading the required number of stages. .

However, such a shift register uses clock pulses φ,
Since 18 constituent FET elements are required including the inverter 11 of V, the area occupied within the chip of the integrated circuit is large, which reduces the yield and makes it difficult to reduce the manufacturing cost.

Also, since the leakage current of each FET is about several pA = nA, the number of FETs that make up a shift register will affect the increase in power consumption, and if multiple stages are connected, the amount of power will become impossible to ignore. .

Therefore, it has been strongly desired to construct a shift register with an even smaller number of FETs.

The present invention has been made in view of the above points, and an object of the present invention is to provide an inexpensive shift register that has a minimum number of elements, occupies a small area within a chip, and is suitable for integrated circuits.

Hereinafter, one embodiment of the present invention will be explained by referring to Figures 3 to 5 as rare fish.

Figure 3 shows one bit of the shift register, where the power supply terminal 21 to which the positive power supply VDD is applied has a ground potential VSS.
An inverter circuit 24 formed by connecting a P-type FET 22 and an N-type FET 23 in series, and an inverter circuit 24 formed by connecting a P-type FET 22 and an N-type FET 23 in series;
An inverter circuit 12 is connected in series with a type FET 26.

And each inverter circuit input 4゜2T is FET2
The gate electrodes of FETs 2, 23 and FETs 25 and 26 are commonly connected to an input terminal 28 to which input information IN is supplied, and the FETs.
The gate electrodes 25 and 26 are connected to each other, and the connection point of the inverter circuit 24°2T is connected to a clock terminal 29 to which a clock pulse φ is supplied.

P-type FET 2 constituting the above inverter circuit 24.27
The substrates of 2 and 25 are directly connected to the positive power supply VDD side, that is, the source, and the N-type FETs 23 and 2
6, the substrate is directly connected to the ground side, that is, the source,
The output terminals of the inverter circuits 24 and 27, that is, each FET
The drains of 22, 23, 25, and 26 are not connected to the substrate, but diodes D0~D4 are parasitically interposed, and all diodes D0~D4 are connected between the power supply terminal 21 and the ground VSS. It is configured to have opposite polarity.

Furthermore, between the power supply terminal 21 and the output terminal of the inverter circuit 27, a P-type FET 3G and an N-type FET 31 are connected.
An inverter circuit 11 is provided in which the inverter circuit 11 is connected in series with the
The output terminal of the inverter circuit 24 is connected to the input terminal of the inverter circuit 32, and the connection point between the FETs 30 and 31, that is, the output terminal of the inverter circuit 32 is connected to the input terminal of the inverter circuit 24 to form a closed loop. are doing.

Also in this inverter circuit 32, FET30.31
The substrate is directly connected to the source, and the diode D, B6, which is parasitically interposed between the substrate and the drain, which is not directly connected, has a reverse polarity with respect to the power supply VDD, as in the case of the diodes D0 to D4 above. ing.

In addition, here, the connection point A to the inverter circuit 27 and lλ, the connection point between the inverter circuits 24 and 32 is B1, the connection point between the inverter circuits 32 and 24 is C, and each FET
The gate capacitance or the source/drain diffusion capacitance is shown by the broken line in the figure.

The output terminal of the inverter circuit 32, that is, the connection point C, is connected to the input terminal of an inverter circuit 44 formed by connecting a P-type FET 42 and an N-type FET 43 in series. N type F
It is connected in series with an inverter circuit 4T formed by connecting ET46 in series, and is arranged between the power supply terminal 21 and the ground potential VSS.

A connection point between these inverter circuits 44 and 47 is connected to the clock terminal 29.

Furthermore, an inverter circuit 52 formed by connecting a P-type FET 50 and an N-type FET 51 in series is provided between the output terminal of the inverter circuit 44 and the ground potential. 47 is connected, and the connection point between FETs 50 and 51, that is, the output terminal of the inverter circuit 52, is used as the output terminal 53 of the output signal and is connected to the input terminal of the inverter circuit 47 to form a closed loop.

In these inverter circuits 44, 47, and 52, the substrate of each FET is directly connected to the source, and the diodes D7 to D12 parasitically interposed between the substrate and the drain, which are not directly connected, are connected to the power supply VDD.
– Reverse polarity between grounds.

Further, the connection point between the inverter circuits 44 and 52 and the connection point between 4T and 52 are respectively designated as E, and the gate capacitance or the diffusion capacitance of the source and drain of each FET is shown by a broken line in the figure.

Figure 4 shows the shift register of the above embodiment in detail in 5OS.
FIG. 2 is a cross-sectional structural diagram of a MO8 type integrated circuit (silicon on sapphire).

In the figure, reference numeral 56 denotes a sapphire substrate, and by providing a thin silicon layer grown, for example, by heteroepitaxial growth on this substrate, and etching away the silicon in unstable areas, the FETs 22, 23, . . . 50° 51 are formed. Formed separately.

Note that the substrate 56 may be any insulating substrate, so for example, spinel or the like may be used, and it may be a normal MOS IC, 0MO8.
In contrast, individual transistors can be easily isolated within a small area, resulting in smaller circuits and lower power consumption.

A hatched portion 5T in the figure is a silicon oxide film, on which gate electrodes, source and drain electrodes, interconnections, etc. are formed using a metal layer such as aluminum.

Further, as shown by the broken lines in the figure, the diodes D1 to D12 are interposed between the substrate and the drain of each FET because the substrate and source regions are placed, for example, on the surface of the substrate 56 or on the side surface of the FET. This is because they are formed parasitically when connected using a conductor.

In addition, in this Figure 4, all FETs and terminals are connected to the third
The same reference numerals are used to correspond to the figures, and wiring relationships are also schematically shown.

FIGS. 5a and 5b are explanatory diagrams of the operation of the shift register of the above embodiment, where a is a logic symbol diagram and b is an operating voltage waveform diagram at each point.

The six inverter circuits in FIG.
The figure shows the clock pulse φ supplied to the clock terminal 29, the input information IN, the voltage waveform of each contact E, and the output signal OUT.

These Figures 5a. The operation of the shift register of the present invention will be explained with reference to FIG.

First, consider the case where the input terminal 28 has input information of "0" level.

At the timing when clock pulse φ is at “1” level, F
When ET25 is turned on, FET23 is turned off, and the potential of the output terminal of the inverter circuit 27, that is, the connection point A becomes "
1" and the connection point B becomes the "1" level regardless of the potential of the connection point C because the diode D2 is biased in the forward direction.

Note that since the second control terminal of the inverter circuit 2, that is, the connection point A, is at the ULV level, the potential at the connection point C is brought to the "1" level by the diode D6.

When the clock pulse φ reaches the “0” level, the FET23
is turned on, the output terminal of the inverter circuit 24, that is, the connection point B is inverted to the "0" level.

At the same time, the potential at the connection point A is also discharged by the diode D3, so that it is inverted from the "1" level to the "0" level.

Therefore, since FET 3G is turned on and FET 31 is turned off, inverter circuit 32 maintains the potential at connection point C at the "1" level, forming a safety memory circuit together with inverter circuit λA.

If the leakage clock pulse φ is "0", the input information IN
The potentials at connection points B and C are held regardless of the

Then, when the clock pulse φ reaches the u1v level again, each connection point A, B, and C is in its initial state, that is, "
Since the potential is at the "1" level, the connection point C is determined to be at the "1" level.

Now, considering the inverter circuits 44, 47, and 52, when the clock pulse is φ=0, the FET 43 is on;
The FET 42 is turned off, and the potential at the output terminal, ie, the connection point, of the inverter circuit 44 becomes the "0" level.

When the connection point is "0" and the clock pulse φ is also at "0" level, the output terminal of the inverter circuit 47.52, that is, the connection point E and the output terminal 53 are connected to the diode D.
Since they are discharged by 9tItt, both of them are set to the "0" level.

When the clock pulse φ reaches the "1" level, the diode D8 becomes forward biased and the connection point becomes "1" level.
1” level.

At the same time, the diode D of the inverter circuit 4T becomes reverse biased, but since there is a "0" level signal at the output terminal 53, the FET 45 turns on, so the inverter circuit 4
The potential at the output terminal 7, that is, the connection point E, is also inverted from the "0" level to the "L" level.

Therefore, the inverter circuit 52 turns off the FET 50 and
Since the ET51 is turned on, the potential of the output terminal 53 is kept at the "0" level.

In other words, when the input information IN is "0", the connection point C is "1"
If the level is maintained, the potential of the output terminal 53 is held regardless of the potential of the clock pulse φ.

Then, when the clock pulse φ reaches the 10'' level again, each connection point is connected.

E and the output terminal 53 are in the initial state, that is, each is "
However, if the potential at the connection point C changes, the potential at the connection point will remain at the "1" level, and therefore the output terminal 53 will have data "0" level.
1" will be transmitted as an output signal (timing of 16), but here we are considering up to the timing of 14 (or 1.), that is, when the input information is IN = 0, so the output terminal 53 is a clock pulse. rO despite φ
Maintain v level.

Next, a case where the input terminal 28 has input information of level "1" will be described.

At the timing when clock pulse φ is at “1” level, F
When ET25 is turned off, FET26 is turned on, and the potential of the output terminal of the inverter circuit 2T, that is, the connection point A, is at the "0" level regardless of the clock pulse φ, and the connection point B is at the "0" level regardless of the potential of the connection point C. By including a diode, the level becomes "1".

Therefore, the output terminal of the inverter circuit 32 has a FET
When FET 30 is turned off and FET 31 is turned on, a "0" level potential is obtained.

Thereafter, even when the clock pulse φ reaches the "0" level, the potential at the output terminal of the inverter circuit 2T, that is, the connection point A, is maintained at the "0" level, so the connection point C also reaches rOJ.
level is maintained, FET22 is turned on, and connection point B is also “1”.
' level.

Then, when the clock pulse φ reaches the rlJ level again, the connection point C holds the "0" level, so the inverter circuits 24 and 32 form a stable memory circuit in a closed loop.

When the connection point C maintains the "0" level, considering the inverter circuits 44, 47° 52, when the clock pulse is φ=0, the FET 42 is turned on and the FET 43 is turned off, and the connection point remains at the "1" level. Becomes electric potential.

In addition, in the inverter circuit 47, the diode D becomes the forward direction, and the connection point E becomes the "0" level, and as a result, the FET5
Since the FET 51 is turned on and the FET 51 is turned off, the output terminal 53 has a "1" level at the connection point.

When φ=1, the connection point is connected by diode D8.
Since the output terminal 53 is ulv, the FET 45 is turned off and the FET 46 is turned on, so that the connection point E becomes "1" level.
Therefore, the output terminal 53 also maintains "1".

In other words, the inverter circuits 47, 52 form a stable storage circuit.

By the way, considering the timing t4 when the input information IN changes from "0" to "1", the clock pulse φ is "1".
Since the connection point A is inverted to "0" level, the connection point B is also inverted to "0" as the FET 23 is turned on.

Therefore, diode D6 becomes reverse biased, but the FET
3Q is turned on and connection point C is kept at "1".

However, at the next timing t when the clock pulse becomes φ=1, the connection point A remains at "0", but the connection point B is inverted to "1" by the diode D2, and therefore the connection point C becomes "0". ”.

Therefore, the shift register composed of the inverter circuits 24, 27, and 32 receives the input information IN and the clock pulse φ.
, and obtains a delayed output signal by storing half a bit corresponding to a half cycle of the inverter circuit 44.
47. Even in the shift register configured in 52, a stable memory circuit is formed at the timing of t to t6, so at the time of At6, the above input information ("0" → "1j" input at t4) is delayed by 1 bit as an output signal. The signal is applied to the output terminal 53 as a signal.

In this way, each of the connection points A, B, and C in the previous stage transmits the input information IN to the connection point C when the clock pulse φ-1, and φ=
When the value is 0, data is held for a certain period of time by forming a stable circuit.

The connection point E and the output terminal 53 in the latter stage are φ=0.
When φ
When =1, this data is held for a certain period of time by forming a stable circuit.

Therefore, when φ-1, the human power information is stored in the stable storage circuit of the connection point B-C-H, and when φ=0, data is output from the output terminal 53, and the terminal 53→connection point E→terminal 53 Since it is stored in the stable memory circuit of 1
It can be seen that a bit shift register (so-called delay type flip-flop) is constructed.

The shift register of the above embodiment was realized as a 5O8-IC as shown in FIG. It is also realized as an integrated circuit.

However, if the substrate of all FETs is made common, then the diode D12sD13sD shown in Figure 6
Since 16°D18tD19jD21 is not necessarily formed parasitically, it is necessary to form it separately by selective diffusion.

Here, since FIG. 6 has almost the same configuration as FIG. 3, F
Drain of ET23, 25, 31, 43°45.51
Components other than the diode formed between the sources are designated by the same reference numerals, and their description will be omitted.

The embodiment of the present invention described above operates as a 1-bit shift register by combining 12 FETs and diodes parasitic to these or [C type diodes connected between drain and source]. Compared to the conventional shift register using FET2, the number of elements is reduced by 25%, and since only one clock pulse φ is used, there is no need for an inverter circuit to obtain 7 or the wiring for that purpose. - The area occupied per bit is significantly reduced.

Therefore, it is expected that power consumption will be reduced by reducing the number of elements, and cost of the integrated circuit will also be reduced by reducing the area.

FIG. Ta is a logical symbol diagram showing one bit of a shift register constructed similarly to the embodiment of FIG.

However, different clock pulses φ1 and <2 are supplied to the front half bit and the rear half bit so that the stable storage periods in the front stage and the rear stage are equal.

In other words, as shown in FIG. 7, which shows its operating waveform, clock pulses φ1 and φ2 have a phase difference of 180° and φ2.
v2, which is an inverted version of , is used.

FIGS. 8a and 8b show another embodiment, in which the half-bit shift register at the front stage and the half-bit shift register at the rear stage have exactly the same configuration, but the clock pulses supplied are φ and Oka.

9a and 9b have the same configuration as the one in FIG. 8, but the supplied clock pulse is φ1 in the first stage and φ1 in the second stage.
2 and are different from each other.

The embodiments shown in FIGS. 10a and 10b are shift registers in which the half-bit shift registers in the front and rear stages of the embodiment in FIG. 7 is used instead of the supplied clock pulse φ.

Figure 11a and b are the same as the shift register in Figure 10 above.
A 1-bit shift register is formed in the 1-bit shift register, and different clock pulses d1 and φ2 are supplied to the front stage and the rear stage.

FIGS. 12a and 12b are shift registers in which the front and rear stages have the same configuration, and a clock pulse φ is supplied to half the bits in the front stage, and φ is supplied to the rear stage.

Figures 13a and 13b have the same configuration as the one in Figure 12, but the supplied clock pulses are different from each other: φ1 for the first half bits and φ2 for the second half bits. Supplied.

FIG. 14a shows a 1-bit shift register similar to the shift register described above, and here, the first to third inverter circuits 4 are used as the shift register for the latter half bits.
In addition to the inverter circuits 4, 47, and 52, a fourth inverter circuit 58 is used.

This fourth inverter circuit 58 is located between the output terminal of the third inverter circuit 52 and the input terminal of the first inverter circuit 47, and inverts the output signals of the third inverter circuit 52 and others. In addition, in this case, the output signal O
The output terminal 53 of the UT is connected to the fourth inverter circuit 58, but the third inverter circuit 52
The inverted output signal OUT may be obtained from the output terminal of the output terminal.

15a and 15b show shift registers in which the half-bit shift registers at the front and rear stages in the embodiment of FIG. The clock pulse φ is supplied to the inverter circuit 44, and both the front and rear stages are operated using the clock pulse φ.

Figures 16a and 16b show the third, fourth, and second inverter circuits 52, 58, and 44 in the half-bit shift register at the subsequent stage.
are shift registers connected to form a closed loop, and it can be seen from the operational waveform diagram in the same figure that the input information IN is delayed by one bit and obtained as the output signal OUT, similarly to each of the embodiments described above.

The operations of each of the embodiments shown in FIGS. 7 to 16 can be easily understood from the embodiment described in FIG. 5, and explanations of operation waveform diagrams will be omitted.

FIGS. 17a to 17h collectively illustrate the configuration of the embodiment described above, and two types of clock pulses can be supplied to the clock terminal each time.

Of course, embodiments of the present invention are not limited to such combinations of one-bit shift registers.

FIG. 18a shows a modification of the shift register of the present invention, in which the reset terminal π is used in the embodiment of FIG.

This is the one with R added.

That is, the P-type FET 30' connected in parallel with the FET 30 (51) of the third inverter circuit 32 (and 52)
(51') gate electrode and the third inverter circuit 32
(52) and the second control terminal of the second inverter circuit 27 (
44) and the N-type FET 3σ' (
51) is the reset terminal π(R).
The 18th
The figure shows a logical symbol diagram, and Figure C shows an explanatory diagram of its operating waveforms.

FIG. 19 shows an N-bit shift register constructed by connecting the shift registers shown in FIG. 17 in N stages.

Of course, it can be constructed using any of the shift registers shown in FIG. 1T, and is applied to a memory circuit of an arithmetic device.

FIG. 20 similarly shows an N-bit shift register, but here a reset signal is supplied to each stage of the shift register, and it is possible to reset the output signal to "O".

Although not shown, a set signal can also be supplied to this shift register.

As described in detail above, according to the present invention, the Norishoiso FET6
Accordingly, an output signal delayed by half a bit can be obtained, and the shift register can be provided as an inexpensive integrated circuit with reduced power consumption.

It should be noted that the present invention is not limited to the embodiments described here, but may be implemented with various modifications without departing from the gist thereof.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one bit of a shift register using conventional FETs, Fig. 2 is an explanatory diagram of operating waveforms of the shift register of Fig. 1, and Fig. 3 shows an embodiment of the shift register of the present invention. Circuit diagram FIG. 4 is a cross-sectional explanatory diagram showing one configuration example of the same embodiment circuit, FIGS. 5 a and b are logic symbol diagrams and operation waveform diagrams of the same embodiment circuit, and FIG. A circuit diagram showing an example, FIGS. 7 to 16 are logic symbol diagrams and operation waveform diagrams of other embodiments of the present invention, FIGS. 17 a to h are logic symbol diagrams of each embodiment, and FIGS. 18 a, b and c are circuit diagrams, logic symbol diagrams and operational waveform diagrams showing still another embodiment of the present invention, and FIGS. 19 and 20 are logic symbol diagrams showing an n-bit shift register, respectively. 24.47...First inverter circuit, 2T. 44... Second inverter circuit, 32, 52...
...Third inverter circuit, 33.58...
...Fourth inverter circuit.

Claims (1)

[Claims] 1- conductivity type insulated gate field effect transistor (hereinafter referred to as
(abbreviated as "FET") is connected in series with a FET of the opposite conductivity type, and the source electrodes of each FET located at both ends of this series circuit are used as the first and second control terminals, respectively, and the gate electrodes of each FET are commonly connected. An inverter circuit is formed in which the connection point of each FET is used as an input terminal and the connection point of each FET is an output terminal, the first and second inverter circuits are connected in series so that the conductivity types of the FETs alternate, and the third inverter circuit is The first control terminal of is connected to the first control terminal of the first inverter circuit, the second control terminal is connected to the output terminal of the second inverter circuit, and the input terminal of the third inverter circuit is connected to the first control terminal of the first inverter circuit. Connected to the output terminal of the first inverter circuit, further supplies a clock pulse to the connection point between the first inverter circuit and the second inverter circuit, and inputs the clock pulse to the input terminal of the first or second inverter circuit. information, and connect the output terminal of the third inverter circuit directly to the input terminal of the inverter circuit to which the input information is not supplied among the first or second inverter circuits, or connect the output terminal of the third inverter circuit directly to the input terminal of the inverter circuit to which the input information is not supplied, or to the fourth inverter circuit. These first to third
The third inverter circuit uses diodes formed between each output terminal of the inverter circuit and the first or second control terminal
Alternatively, a shift register characterized in that an output signal obtained by delaying the input information by a half bit corresponding to a half cycle of the clock pulse is obtained from the output terminal of the fourth inverter circuit.