JPS5811769B2 - Periodic pulse check method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a periodic pulse check method, and more specifically to a periodic pulse check method constructed by sequentially reading out the contents of a memory at a constant period.

In recent years, it has become possible to store the contents in a memory such that the desired period and pulse ratio can be obtained, and access the contents sequentially in the order of the addresses in the memory using the output of an address counter that increments with basic pulses of a constant period. A pulse generation method has come to be used in which periodic pulses having a desired period and pulse ratio are obtained by reading out pulses into a register and from the output of this register.

The above pulse generation method can generate pulses with short or long cycles.

As a method for checking periodic pulses, a slow recovery relay that does not recover during the pulse rest time is activated by periodic pulses,
It is known to check the periodic pulse by restoring the relay when the next pulse is not input even after a scheduled time has elapsed, but with this conventional method, the stop or disappearance of the periodic pulse can be easily detected. It is difficult to check fluctuations in the period and pulse ratio, and in the case of short-period pulses, the relay operation cannot be restored, resulting in insufficient checking.

It is generally impossible to use this conventional method to check periodic pulses generated by the above pulse generation method.

It should be noted that no method is known that can sufficiently check the periodic pulses generated by the above pulse generation method, that is, check the stopping or extinction of the pulse, its period, pulse ratio, etc.

SUMMARY OF THE INVENTION An object of the present invention is to provide a periodic pulse check method that can sufficiently check periodic pulses generated by the above pulse generation method.

According to the present invention, this purpose is to write data corresponding to the periodic pulse to be obtained into the rows of a memory in which memory elements are arranged in a matrix, and to sequentially read out the contents of each column at a constant period so as to correspond to the rows. In a periodic pulse generation method that generates a desired periodic pulse, data for generating a periodic pulse for checking is stored in one row of the matrix, and data for parity check for each column is stored in another row. This is achieved by providing a circuit element that inverts the output when the next pulse is not detected even after the scheduled time has elapsed in the output section of the periodic pulse for writing and checking the above, and also providing the periodic parity check circuit described above. .

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a connection diagram of an embodiment of the present invention.

In the figure, ROM is a read-only memory, and its memory elements are B0 to B5, rows 1 and 2, and W0 to W
It is arranged in a matrix with 15 columns, and by addressing each of columns W0 and W1 to W15, the contents are written to rows B0 to B5.
, and registers R0 to R5 corresponding to 2.

Read to RKl and RK2.

AC is an address counter configured as a hexadecimal counter, and is incremented by a basic pulse CL of a constant period.

PC is a parity check circuit, and RM is a circuit that inverts its output when the next pulse is not detected even after a predetermined time has elapsed. For example, it can be configured with a retriggerable monostable multivibrator, and the OR is It is orgate.

Data for providing desired periods and pulse ratios are written in rows B0 to B5 of the read-only memory ROM, respectively.

In row 2, 010 as shown in the figure is used to generate short-cycle pulses to check the presence or absence of pulse output.
Data of 1... is written.

In row 1, parity data for columns W0 and W1 to W15 is written in correspondence with the state of data in the columns.

FIG. 2 is a diagram showing waveforms of periodic pulses in each part of FIG. 1, and the basic pulse CL has a constant period as shown in FIG. 2 PCL.

When this basic pulse CL is input to the address counter AC, an output is first generated at the output terminal 0 of the address counter AC, and the column W is output.

Address the negotiation data in rows B0 to B5, 1 in 2, 2 in rows B0 to B5.
The data is read to the registers R0-R5, RK1, and RK2 corresponding to the data.

The outputs of the registers Ro-R5, RK1, and RK2 become 0 and 1 (low and high) according to the read contents 0 and 1, respectively.

When the next pulse of the basic pulse CL is input after a certain period, the address counter AC steps forward and outputs an output to the output terminal 1.
Address the next column W1 and store negotiation data in registers R0 to R5 and RK1, respectively.

Read to RK2.

The output of the register changes depending on the contents read at this time.

In this way, the data up to column W15 are sequentially read out, and when the basic pulse CL is input next, the process returns to column W0.

For example, row B0 has the contents of 00110 as shown in the figure, so the period is four times the period of the basic pulse CL from the output of the register R0, and the pulse ratio is 50% in FIG. 2P.

A periodic pulse with the waveform shown is obtained. In this way, from registers R1 to R5, row B1 of the read-only memory ROM is
Periodic pulses P1 to P5 with waveforms corresponding to the contents written in B5 are obtained.

Note that the output of the resistor RK2 is led to, for example, a retriggerable monostable multivibrator RM.

As can be easily understood from the above, register RK2 is the second
As shown in Figure PK2, a pulse with a period twice the period of the basic pulse PCL is sent out.

If the predetermined period during which the multivibrator RM can be retriggered is selected as the period of the periodic pulse PK2 output from the register RK2, the multivibrator RM will always be in a triggered state if the pulse is sent out normally.

At this time, it is assumed that "0" is output as the output ER1.

However, for some reason, the periodic pulse P
If K2 is no longer sent out, the multivibrator RM
Since it is not triggered during the retriggerable period, it recovers and outputs "1" to its output ER1.

The outputs of registers R0 to R5, RK1, and RK2 are led to a parity check circuit PC to perform a parity check.

If validity is detected by this parity check, the output terminal E
Output “0” to R2.

If the contents of one memory element in the column addressed by the address counter AC is erroneously read, the parity check detects the error and outputs "1" to the output terminal ER2 of the parity check circuit PC.

The output terminals ER1 and ER2 are connected to the input terminal of the OR gate OR, and if an error is detected in either or both of them, "
When outputting ``1'', the output of the OR gate becomes ``1'', indicating an error.

The above is merely an example; for example, the structure of the read-only memory ROM is not limited to a matrix structure of 16×8 memory elements, and the number thereof can be changed as desired.

The circuit RM for confirming the presence of periodic pulses is not limited to the retriggerable monostable multivibrator described above, but other circuits that perform the same function, such as a combination circuit of a timer circuit and a flip-flop, may be used.

Since the present invention is configured as described above, it is possible to detect the stop or disappearance of the periodic pulse and also detect the deformation of the waveform of the periodic pulse to be outputted by the parity check. This has the effect of making it possible to sufficiently check the periodic pulses generated from.

[Brief explanation of drawings]

FIG. 1 is a connection diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing waveforms of periodic pulses at various parts in FIG. 1. ROM...Read only memory, AC...
・Address counter, R0 to R5, RKl, RK2・
...Register, PC...Parity check circuit, RM...Circuit for checking the presence of periodic pulses (retriggerable monostable multivibrator), OR
...OR gate, CL...basic pulse, PCL・°°...basic pulse waveform, P0~P5...
...Output pulse waveform.

Claims (1)

[Claims] 1 Data corresponding to the periodic pulse to be obtained is written in the rows of a memory in which memory elements are arranged in a matrix, and the contents of each column are sequentially read out at a constant period to generate the desired periodic pulse corresponding to the row. In the pulse generation method, data for generating a periodic pulse for checking is written in one row of the matrix, data for parity check for each column is written in another row, and data for generating a periodic pulse for checking is written in another row. The pulse output section is equipped with a circuit that inverts the output when the next pulse is not detected after the scheduled time has elapsed.
Further, a periodic pulse check method is provided, comprising a parity check circuit for checking the output of the periodic pulse generation method.