JPS5812605B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Description of the Technical Field The present invention relates to data transfer between devices, and to an improved data processing mirror capable of converting serial data to parallel data.

(b) Description of Prior Art FIG. 1 shows a typical conventional method of converting serial input data into parallel output data using a shift register with parallel outputs, and its operation is performed as follows.

That is, after inputting the CLEAR signal and setting all set/reset type flip-flops 1 to 4 to the reset state, C
When the INPUT signal is input in synchronization with the LOCK signal, the INPUT signal is shifted to the right every time the CLOCK signal is input.

When the output after shifting N times is read, N bits of serial data appear as parallel data in the outputs from QA to QN, and the serial data can be converted to parallel data.

However, in the conventional method using this shift register, it is necessary to shift N bits of serial data N times before it can be read as parallel data output.

For this reason, it has the drawback of requiring waiting time, for example, when reading it on a computer.

(c) Purpose of the Invention The object of the present invention is to provide a data processing device that uses a readable and writable memory element with a large storage capacity and can read out serial data as parallel data at any time, and that does not cause any shortage of data. shall be.

(d) Summary of the Invention FIG. 2 shows a known normal write/read storage device, and when writing to the storage section 12, address data is input to the Advice control circuit 11.

Then, when the address of the storage section 12 to be written is selected and the WRITE signal is input to the write control circuit 13, the write data is written to the storage section 12 specified by the address data.

Further, for reading, the contents of the storage section 12 specified by the address data are outputted to the read control circuit 14, as described above.
When the READ signal is input to the read control circuit 14, the contents of the storage section 12 are output as read data.

In this way, there is usually only one address control circuit, and the same address control circuit is used for writing and reading, so writing and reading cycles cannot be executed simultaneously.

Therefore, in the present invention, a write-only address control circuit and a read-only address control circuit are provided. and divides the memory into row and column addresses.

The write-only address control circuit specifies the row address, and the read-only address specifies the column address, so that writing and reading can be executed independently.
It also allows data conversion between write data and read data.

(e) Structure and operation of the invention Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 3 shows an embodiment of the present invention, and FIG. 3a shows a specific circuit configuration.

In the same figure. 21 is a column address control circuit that decodes a periodically generated write address and outputs a write signal WRI.
A write strobe signal for the memory circuit 22 is generated by the TE.

The memory circuit 22 is a D-type flip-flop that stores data on the data lines (D1, D2, . . . , Dn) using a write strobe signal, and is a memory circuit that can inhibit/enable output data using an external signal. be.

Reference numeral 24 denotes a row address control circuit, which decodes the read address and enables the output data of the storage circuit 22 in response to the read signal READ.

In addition, the selection circuits 1 to n (26, 27) receive a plurality of parallel input signals (all, a12, ..., aIJ).
...(ai1, ai2y..., aij)
is selected by the write address, and the serial data D1, D
This is a circuit that outputs as 2, . . . , Dn.

In this configuration, the input signal att~aIJ tail~
To explain how the state of aij is read out, the input signal . ”atj column) t
D2 (a21 t a22t"...", a2j column)
,...Dn(ai1,al2t""",a
ij column) and output to the input data line of the storage circuit 22.

On the other hand, the column address control circuit 21 also generates a column write strobe signal for the storage circuit 22 in synchronization with the write address in response to the write signal WRITE, and the data on the serial input data lines are sequentially stored.

Further, to read data from the memory circuit 22, a read address is specified by a computer or the like, the read address of the row address control circuit 24 is decoded by the read signal READ, the output data of the memory circuit 22 is enabled, and the specified read address is read. The contents are read data I1, ■2,...tIn
) and read by the computer.

In the present invention, the read address and the write address are asynchronous, and when a certain row is accessed by the read address, if a certain column is accessed by the write address, the previous column data will be written in this cycle. Is the new data written in the last column the old data written in the previous cycle? It is.

Here, one line (ait t al,...t a
tj), this method confuses the data and is impossible, but it is effective when each bit has a meaning as in this example.

This confusion can be avoided by periodically allowing reading when writing is completed.

FIG. 3b shows this method. At the time t when the write cycle is completed, it is checked whether there is a read or not. If not, the next second cycle write is executed, and at the time t when the write cycle is completed, a read request is issued. To check.

If requested, a read is executed, and after the read is completed, a rewrite cycle is executed.

In this way, since the serial data is read out when it is completely written, data confusion can be avoided.

FIG. 4 is an explanatory diagram of how serial data is converted into parallel data in the data processing device of the above embodiment.

In the same figure, the column address (write address) is from “0” to “7”.
It is assumed that the row address (read address) is accessed up to the number N of serial data lines.

First, when column address "0" is accessed in a write cycle, the write data at this time D1=0, D2=lSD3
-0...Dn=0 is stored at the column address "0" and is stored until the next column address "O" is accessed.

Thereafter, write data is similarly stored in the memory section accessed by the column address, and by periodically accessing column addresses 0 to 7, it is rewritten with new data each time.

By accessing the data written in this way using the row address (read address), each serial data D1
The information on the serial data up to the Dn line is read out as parallel data.

For example, when accessing the row address "1", ■, 1, 0
, 1, 0, 0, 0, 1 are read out.

FIG. 5 shows how column data is indexed and converted into row data in the data processing apparatus of the present invention.

The current column address 0=0000, 1=0 is stored in the storage section 22'.
Assuming that 000, 2=0011, 3=0 1 0 1 is written, reading this with the row address will result in O=00
00,1=0001,2=0010 ,3=OO1 1
It can be read as

In this state, if you write column address 1 = 1 1 1 1,
When reading by row address, the read data is o=o i o
o, 1=0101, 2=0110, 3=0111, and when reading the read data in hexadecimal, 0, 1,
This means that 2 and 3 have been converted to 4.5, 6, and 7, and data index conversion can be easily performed.

As is clear from the above description, unlike the conventional readable and writable storage devices that read written data as is, the present invention first stores written data using a row address control circuit. .

Then, the read data is passed through a column address control circuit, and the stored data is read out to convert the serial data into parallel data. Tono 2
It has two functions.

In this way, according to the present invention, it is possible to provide an effective data processing device that can read out serial data as parallel data at any time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional method of converting serial input data into parallel output data, FIG. 2 is an explanatory diagram of a known write/read storage device, and FIG. 3 is an embodiment of the present invention, and a is a circuit. Block diagram, b is an explanatory diagram of the writing and reading method, Fig. 4 is an explanatory diagram of how serial data is converted to parallel data, Fig. 5 is an explanatory diagram of the method of writing and reading.
The figure is an explanatory diagram of an application example used for index conversion of data. 1 to 4...Set, reset type flip-flop, 11...Address control circuit, 12, 22'
...Storage unit, 13...Write control circuit, 14...Read/write control circuit, 21...
・Column address control circuit, 22...Storage circuit, 2
4... Row address control circuit, 26, 27...
...Selection circuit.

Claims (1)

[Claims] 1. A selection circuit that receives a periodically generated write address signal, converts a plurality of input signals into serial data, and outputs the serial data.
a column address control circuit that receives the write address signal, inputs and decodes the write signal, and generates a column write strobe signal; and a memory divided into column addresses and row addresses that sequentially store the serial data according to the write strobe signal. and a row address control circuit that receives a periodically generated read address signal, inputs the read signal, decodes the read address, enables data output from the storage section, and reads the contents of the designated read address. A data processing device characterized in that it simultaneously executes writing and reading independently and converts serial data into parallel data.