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JPS5812671B2 - How to form a multilayer structure - Google Patents
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JPS5812671B2 - How to form a multilayer structure - Google Patents

How to form a multilayer structure

Info

Publication number
JPS5812671B2
JPS5812671B2 JP52153244A JP15324477A JPS5812671B2 JP S5812671 B2 JPS5812671 B2 JP S5812671B2 JP 52153244 A JP52153244 A JP 52153244A JP 15324477 A JP15324477 A JP 15324477A JP S5812671 B2 JPS5812671 B2 JP S5812671B2
Authority
JP
Japan
Prior art keywords
pattern
insulating film
thickness
magnetic
aluminum wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52153244A
Other languages
Japanese (ja)
Other versions
JPS5484932A (en
Inventor
瀬川幹雄
折原尚武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52153244A priority Critical patent/JPS5812671B2/en
Publication of JPS5484932A publication Critical patent/JPS5484932A/en
Publication of JPS5812671B2 publication Critical patent/JPS5812671B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は、磁気バブル素子など、徴細パターンを多層に
した構造を有する装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a device, such as a magnetic bubble element, having a structure in which fine patterns are multilayered.

磁気バブルメモリ素子のコンダクタ・ファスト(Con
ductor first)と呼ばれる層構成は、第1
図に示すように、ガドリニウム・ガリウム・ガーネット
(GGG)単結晶基板1上に磁性薄膜2をエピタキシャ
ル成長させ、さらにその上に二酸化シリコン(SiO2
)からなる絶縁膜3を被着した後、バブル発生器、ゲー
ト、リプリケータなどの制御用配線として使用されるア
ルミニウム配線パターン4を形成する。
Conductor Fast (Con), a magnetic bubble memory element
The layer structure called "ductor first" is
As shown in the figure, a magnetic thin film 2 is epitaxially grown on a gadolinium gallium garnet (GGG) single crystal substrate 1, and silicon dioxide (SiO2
) After depositing an insulating film 3 consisting of an aluminum wiring pattern 4, an aluminum wiring pattern 4 used as control wiring for a bubble generator, gate, replicator, etc. is formed.

次いで、全面に二酸化シリコンからなる絶縁膜5を被着
し、その上に転送路、ゲート、リプリケータ、検出器と
なるパーマロイパターン6を形成し、その上に二酸化シ
リコンの保護膜7を全面に被着した構造を有する。
Next, an insulating film 5 made of silicon dioxide is deposited on the entire surface, a permalloy pattern 6 that will serve as a transfer path, a gate, a replicator, and a detector is formed on the insulating film 5, and a protective film 7 made of silicon dioxide is coated on the entire surface. It has a built-in structure.

この構造においては、パーマロイパターン6と磁性薄膜
2との距離が短かいほどパーマロイパターン6からの磁
束が有効に生かされ、バブル動作マージンを拡げること
ができる。
In this structure, the shorter the distance between the permalloy pattern 6 and the magnetic thin film 2, the more effectively the magnetic flux from the permalloy pattern 6 is utilized, and the bubble operation margin can be expanded.

したがって、出来得る限りパーマロイパターン6を磁性
薄膜2に近づけたいのであるが、通常パターン設計上ア
ルミニウム配線パターン4とパーマロイパターン6が重
なり、しかもパーマロイパターン6によりアルミニウム
配線パターン4の一部が重ねられる個所が存在する。
Therefore, it is desired to bring the permalloy pattern 6 as close to the magnetic thin film 2 as possible, but due to the normal pattern design, the aluminum wiring pattern 4 and the permalloy pattern 6 overlap, and moreover, the permalloy pattern 6 overlaps a portion of the aluminum wiring pattern 4. exists.

そのためにどうしてもこれらの間に絶縁膜5を介在させ
なければならない。
Therefore, it is absolutely necessary to interpose the insulating film 5 between them.

絶縁膜5の厚さは、ほぼ2300〔Å〕〜2500〔Å
〕程度必要である。
The thickness of the insulating film 5 is approximately 2300 [Å] to 2500 [Å].
] degree is necessary.

しかしながら、平坦部でこの厚さの絶縁膜5を被着した
ときには、アルミニウム配線パターン4のパターンサイ
ドで段切れあるいは肉薄を生じ、この部分で十分な膜厚
を確保することができない。
However, when the insulating film 5 of this thickness is deposited on a flat part, a break or thinning occurs on the pattern side of the aluminum wiring pattern 4, and a sufficient film thickness cannot be secured in this part.

そこで、従来はバブル動作マージンを犠牲にして、アル
ミニウム配線パターン4の厚さが3000〔Å〕に対し
て絶縁膜5の厚さを平坦部において5000〔Å〕とし
、パターンサイドでその厚みが薄くなったとしても必要
最小限の2300〔Å〕の厚さを確保している。
Therefore, conventionally, at the expense of the bubble operation margin, the thickness of the insulating film 5 was set to 5000 [Å] on the flat part compared to the thickness of the aluminum wiring pattern 4 of 3000 [Å], and the thickness was made thinner on the pattern side. Even if the thickness is reduced, the required minimum thickness of 2300 Å is ensured.

本発明は上述の如き従来の欠点を改善する新しい発明で
あり、その目的は、パーマロイパターンとアルミニウム
配線パターンとの間の絶縁を十分確保しながら、パーマ
ロイパターンと磁性薄膜との距離を出来得る限り近ずけ
ることができるような新規な製法を提供することにある
The present invention is a new invention that improves the conventional drawbacks as described above, and its purpose is to minimize the distance between the permalloy pattern and the magnetic thin film while ensuring sufficient insulation between the permalloy pattern and the aluminum wiring pattern. The objective is to provide a new manufacturing method that can be approached.

その目的のために本発明の多層構造の形成方法は、基板
上に形成した第1のパターン上に絶縁膜を介して第2の
パターンを積層する多層構造の製法において、第1のパ
ターンが形成されていない部分の基板上に第1のパター
ンの厚さより薄い絶縁薄膜をあらかじめ被着した後、絶
縁膜を全面に被着し、絶縁膜上に第2のパターンを形成
することを特徴とするもので、以下実施例について詳細
に説明する。
For this purpose, the method for forming a multilayer structure of the present invention includes a method for forming a multilayer structure in which a second pattern is laminated on a first pattern formed on a substrate with an insulating film interposed therebetween. The method is characterized in that an insulating thin film thinner than the thickness of the first pattern is previously deposited on the parts of the substrate that are not covered by the pattern, and then an insulating film is deposited on the entire surface, and a second pattern is formed on the insulating film. Examples will be described in detail below.

アルミニウム配線パターンサイドでの段切れあるいは肉
薄の発生は、アルミニウム配線パターン4の表面から絶
縁膜3までの段差t1(すなわちアルミニウム配線パタ
ーンの厚さ)と該配線パターン4上に被着する絶縁膜5
の厚さt2との割合(t2/t1)(以後この割合をα
と表現する)が小さければ小さいほど生じる割合が大き
くなる。
The occurrence of step breakage or thinning on the side of the aluminum wiring pattern is caused by the step t1 from the surface of the aluminum wiring pattern 4 to the insulating film 3 (that is, the thickness of the aluminum wiring pattern) and the insulating film 5 deposited on the wiring pattern 4.
(t2/t1) (hereinafter, this ratio will be referred to as α
The smaller the ratio (expressed as), the greater the proportion.

ちなみにいえば、第1図に示す従来装置の割合αは16
7(5000/3000)である。
By the way, the ratio α of the conventional device shown in Figure 1 is 16
7 (5000/3000).

しかしながら、割合αを1.67よりも大きくしたとき
にはアルミニウム配線パターンサイドで段切れや肉薄は
なくなり、この部分の厚さも平坦部の膜厚とほぼ等しく
なる。
However, when the ratio α is made larger than 1.67, there is no breakage or thinning on the side of the aluminum wiring pattern, and the thickness of this part becomes almost equal to the film thickness of the flat part.

このようなことから段差t1を小さくすれば、上記割合
1.67を保つ限りアルミニウム配線パターンサイド部
分の絶縁膜の厚さを減少せしめることができる。
For this reason, by reducing the step t1, the thickness of the insulating film on the side portion of the aluminum wiring pattern can be reduced as long as the above ratio of 1.67 is maintained.

そこで、本発明においては、絶縁膜3の表面に第2図に
示したように、あらかじめ二酸化シリコン(SiO2)
などの絶縁膜8を積層し、実質的な段差t1′を減少せ
しめる。
Therefore, in the present invention, silicon dioxide (SiO2) is applied to the surface of the insulating film 3 in advance as shown in FIG.
An insulating film 8 such as the like is laminated to reduce the substantial step t1'.

このため、全面に被着する絶縁膜5の厚さt2を従来よ
りも薄く出来る。
Therefore, the thickness t2 of the insulating film 5 deposited on the entire surface can be made thinner than in the conventional case.

下記の表は、アルミニウム配線パターンの膜厚を300
0〔Å〕、割合α=1.67の条件で絶縁膜3の表面に
積層する絶縁膜8の厚さt4と段差t1と絶縁膜5の厚
さt2と絶縁膜3上に積層される絶縁膜の厚さ(t2+
t4)との関係を従来装置のものと比較して示したもの
であり、第3図はこれらの関係をグラフ化したものであ
る。
The table below shows the thickness of the aluminum wiring pattern at 300mm.
0 [Å], ratio α = 1.67, the thickness t4 of the insulating film 8 laminated on the surface of the insulating film 3, the step t1, the thickness t2 of the insulating film 5, and the insulation laminated on the insulating film 3. Film thickness (t2+
t4) in comparison with that of a conventional device, and FIG. 3 is a graph of these relationships.

なお、絶縁膜3上に絶縁膜8を積層する方法は種々考え
られているが、1つの方法として、アルミニウム配線パ
ターン4の上にレジスト層を被着した後、液状の二酸化
シリコンをスピンコートし、リフト・オフ法によりレジ
スト層を除去するとともに、その上に被着した二酸化シ
リコンを除去すればよい。
Various methods have been considered for laminating the insulating film 8 on the insulating film 3, but one method is to deposit a resist layer on the aluminum wiring pattern 4 and then spin-coat liquid silicon dioxide. The resist layer may be removed by a lift-off method, and the silicon dioxide deposited thereon may be removed.

以上詳細に説明したように、本発明は、アルミニウム配
線層以外の部分をたとえば該層の層厚の半分の厚さを有
する絶縁膜を積層して埋めたとすれば、段差t1は15
00〔Å〕となり従来のものと同様割合αを1.67と
すればアルミニウム配線パターン上に被着する絶縁膜5
′の厚さは2500〔Å〕となりしたがって、絶縁膜5
上に被着するパーマロイ層と絶縁膜3との間の厚さt2
+t4は4000〔Å〕となって従来の5000〔Å〕
に比べてその厚さを20〔%〕も減少せしめることがで
きる。
As explained in detail above, in the present invention, if the portion other than the aluminum wiring layer is filled with an insulating film having a thickness half that of the aluminum wiring layer, the step t1 is 15
00 [Å], and if the ratio α is set to 1.67 as in the conventional case, then the insulating film 5 deposited on the aluminum wiring pattern
The thickness of the insulating film 5 is 2500 [Å].
Thickness t2 between the permalloy layer deposited on top and the insulating film 3
+t4 is 4000 [Å] compared to the conventional 5000 [Å]
The thickness can be reduced by as much as 20% compared to the previous version.

このため、本発明によれば、従来のものに比べてバブル
動作マージンを大きくとることができるばかりか、配線
パターンとその上に被着するパーマロイとの間の絶縁は
十分保障出来る。
Therefore, according to the present invention, not only can a bubble operation margin be larger than that of the conventional method, but also sufficient insulation between the wiring pattern and the permalloy deposited thereon can be ensured.

前述の如く、磁気バブルメモリ素子のアルミニウム配線
パターン等の制御導体パターンとパーマロイパターン等
の磁性パターンとの多層構造を形成する場合に、磁性パ
ターンは磁性基板に近いことが磁気バブルの制御上望ま
しいものであり、又その磁性パターンは段差の少ない絶
縁膜上に形成することが望ましいものであるが、制御導
体パターンが形成されていない部分に薄い絶縁薄膜を被
着させた後、絶縁膜を被着し、その上に磁性パターンを
形成するものであるから、前述の磁気バブルメモリ素子
に要望される条件を満足させることができるものとなる
As mentioned above, when forming a multilayer structure of a control conductor pattern such as an aluminum wiring pattern of a magnetic bubble memory element and a magnetic pattern such as a permalloy pattern, it is desirable for the magnetic pattern to be close to the magnetic substrate for controlling magnetic bubbles. Although it is desirable to form the magnetic pattern on an insulating film with few steps, it is possible to apply a thin insulating film to the area where the control conductor pattern is not formed, and then apply the insulating film. However, since a magnetic pattern is formed thereon, the above-mentioned conditions required for the magnetic bubble memory element can be satisfied.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の磁気バブルメモリ素子の部分断面図、第
2図は本発明の一実施例を示す部分断面図、第3図は絶
縁膜8の積層厚を変えた場合の他の絶縁膜の変化の様子
を示す曲線図である。 図中、1はGGG単結晶基板、2は磁性薄膜、3,5,
7,8は絶縁膜、4はアルミニウム配線パターン、6は
パーマロイパターンである。
FIG. 1 is a partial sectional view of a conventional magnetic bubble memory element, FIG. 2 is a partial sectional view showing an embodiment of the present invention, and FIG. 3 is another insulating film when the laminated thickness of the insulating film 8 is changed. FIG. In the figure, 1 is a GGG single crystal substrate, 2 is a magnetic thin film, 3, 5,
7 and 8 are insulating films, 4 is an aluminum wiring pattern, and 6 is a permalloy pattern.

Claims (1)

【特許請求の範囲】[Claims] 1磁気バブルメモリ素子の磁性基板上に形成した制御導
体パターンに絶縁膜を介してパーマロイパターン等の磁
性パターンを形成する多層構造の形成方法において、前
記制御導体パターンが形成されていない前記磁性基板上
に該制御導体パターンの厚さより薄い絶縁薄膜を被着さ
せた後、絶縁膜を全面に被着し、該絶縁膜1に前記磁性
パターンを形成する工程を有することを特徴とする多層
構造の形成方法。
1. In a method for forming a multilayer structure in which a magnetic pattern such as a permalloy pattern is formed on a control conductor pattern formed on a magnetic substrate of a magnetic bubble memory element through an insulating film, the control conductor pattern is not formed on the magnetic substrate. Formation of a multilayer structure characterized by comprising the steps of: depositing an insulating thin film thinner than the thickness of the control conductor pattern, then depositing an insulating film over the entire surface, and forming the magnetic pattern on the insulating film 1. Method.
JP52153244A 1977-12-20 1977-12-20 How to form a multilayer structure Expired JPS5812671B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52153244A JPS5812671B2 (en) 1977-12-20 1977-12-20 How to form a multilayer structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52153244A JPS5812671B2 (en) 1977-12-20 1977-12-20 How to form a multilayer structure

Publications (2)

Publication Number Publication Date
JPS5484932A JPS5484932A (en) 1979-07-06
JPS5812671B2 true JPS5812671B2 (en) 1983-03-09

Family

ID=15558201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52153244A Expired JPS5812671B2 (en) 1977-12-20 1977-12-20 How to form a multilayer structure

Country Status (1)

Country Link
JP (1) JPS5812671B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6036770A (en) * 1983-08-09 1985-02-25 Kawasaki Heavy Ind Ltd Fuel injection control device for internal-combustion engine
JPS6075676U (en) * 1983-10-31 1985-05-27 いすゞ自動車株式会社 fuel injector

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56143585A (en) * 1980-04-09 1981-11-09 Nec Corp Magnetic bubble element
JPS58177585A (en) * 1982-04-09 1983-10-18 Hitachi Ltd Magnetic bubble memory element
JPS6074192A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Method for forming bubble memory

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4866783A (en) * 1971-12-16 1973-09-12
JPS5121753B2 (en) * 1972-02-09 1976-07-05
JPS5140872A (en) * 1974-10-04 1976-04-06 Hitachi Ltd BISAIPATA ANNOKEISEIHOHO

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6036770A (en) * 1983-08-09 1985-02-25 Kawasaki Heavy Ind Ltd Fuel injection control device for internal-combustion engine
JPS6075676U (en) * 1983-10-31 1985-05-27 いすゞ自動車株式会社 fuel injector

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Publication number Publication date
JPS5484932A (en) 1979-07-06

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