JPS5813930B2 - General information - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides an information processing device that is capable of performing not only a parity check on input information but also a parity check on information processed and stored based on this input information. Regarding.

[Technical background of the invention and its problems]

For example, information to be processed by a computer, etc. is usually composed of record information consisting of multiple word information, and this record information is stored and stored in an information storage unit consisting of a large number of drums, disks, tapes, etc. It is something.

When processing this information, the information is read from the information storage unit, for example, in units of record information, and word information necessary for information processing is selectively extracted and stored in the processing information storage unit. Various calculations are performed based on the information of
It performs information processing such as aggregation.

When performing such information processing operations, it is necessary to constantly check whether both input information and processing information are transmitted as accurate information.By confirming the accuracy of input information, This guarantees the accuracy of the extracted and transmitted processing information, and by making it possible to check the processing information thereafter, it is possible to guarantee the accuracy of information processing.

[Purpose of the invention]

This invention was made in view of the above points, and it not only checks whether the input information input record by record has been accurately transmitted or input, but also checks whether new information processed based on the input information. The present invention aims to provide an information processing device that adds new parity check information to information on a record basis, and ensures that not only input information is checked, but also new processed information is checked. be.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows its configuration, and the input storage device 11 stores record information that is a combination of a plurality of word information.

In other words, multiple m word information is word separated by word
The record information is arranged in series via kJ, and the record information is separated by record delimiter court BeJ. Following this record delimiter court BeJ, parity check information for the previous record information is inserted. has been done.

This input storage device 11 reads stored information serially in response to a read command, and the read information is coupled to an AND circuit 12, and a code detection circuit 13 generates a record delimiter code rBeJ and a word delimiter code MrWk.
A read of J is detected.

Court code BeJ, rWk from this code detection circuit 13
The detection signal of J is coupled to the readout selection circuit 14, and for example, the readout selection circuit 14 counts and detects the rank of the word to be extracted as processing information by performing step counting on the detection of the coat block BeJ and the detection of the reset record rWkJ. do.

Then, in response to the read input detection of the word information to be selected by the read selection circuit 14, a gate signal is applied to the AND circuit 12, and the word information to be selected is coupled to the processing information storage device 16 via the OR circuit 15. and write and memorize it.

Further, read information from the input storage device 11 is coupled to first and second check information creation circuits 17 and 18.

The first check information creation circuit 17 is controlled in response to the detection that the input storage device 11 is being read, and creates parity check information for the read information, and the second check information creation circuit 18 , read selection circuit 14
The parity check information of the word information coupled to the processing information storage device 16 is created.

These first and second check information creation circuits 17 and 18
is the record delimiter code lBe of the code detection circuit 13
It is output in response to the output signal of the delay circuit 19 to which the detection signal of J is combined and is reset at the same time.The output check information from the first check information creation circuit 17 is sent to the coincidence detection circuit 20. 2 Check information creation circuit 1
The output check information of 8 pieces is coupled to the OR circuit 15 via an AND circuit 21 whose gate m is opened by the output of the delay circuit 19, and is written into the processing information storage device 16.

The read information from the input storage device 11 is coupled to the coincidence detection circuit 20, a comparison command is given by the signal from the delay circuit 19, a gate signal is coupled to the AND circuit 22 by the coincidence output, and an AND circuit is coupled to the coincidence output by the AND circuit 22. A gate signal is given to the circuit 23, and at the same time, a command is given to the input storage device 11 to reread the record information that has been read so far.

Here, the processing information storage device 16 is an address counter 24.
The address counter 24 specifies an address in accordance with the count value of , and writes information from the OR circuit 15 . The count is incremented by the signal from.

Further, the count value of the address counter 24 is coupled to an AND circuit 22, and when a match is detected in the match detection circuit 20, the address count value of the address counter 24 at that time is written into the address memory 26.

The address memory 26 is also coupled to the address counter 24 as preset information via the AND circuit 23 when the coincidence detection circuit 20 detects a mismatch.

That is, in the apparatus configured as described above, record information consisting of a plurality of words is stored in the storage device 11 as described above, and following the record delimiter code MrBeJ that delimits the tail of the record information,
Parity check information corresponding to the record information content is stored.

In addition, in this device, in its initial state, the read selection circuit 14 is in the state before starting counting of the word delimiter code uWkv, that is, in the same state as when the code rBeJ was detected, and the read selection circuit 14 is in the same state as when the code rBeJ is detected, and the read selection circuit 14 is in the same state as when it detects the code rBeJ. The circuits 17 and 18 are in a reset state, and the count value of the address counter 24 at that time is stored in the address memory 26.

When a read command is given to the input storage device 11 in this state, the first record information stored in the storage device 11 is serially read out from the first word and the word delimiter code rWkJ is sent to the read selection circuit 14.
It will be counted and detected.

The read selection circuit 14 stores the order of words to be extracted, and the input storage device 1 of the words to be selected and extracted corresponds to the count of the word delimiter code rWkJ.
1, and when the word information to be extracted is being read, a gate signal is given to the AND circuit 12, and the information of the word to be selectively extracted is sent to the processing information storage device 16.
join to.

At this time, at the same time as a gate signal is given to the AND circuit 12, an increment command is given to the address counter 24 at the same time. Word information is written and stored in the processing information storage device 16.

In this way, information is read from the input storage device 11, and word information necessary for information processing is stored in the processing information storage device 11.
At the same time, the read information from the input storage device 11 is detected by the first check information creation circuit 17, and check information corresponding to the read information is created.

In addition, the second check information creation circuit 18 detects selected word information coupled to the processing information storage device 16 in response to a command from the readout selection circuit 14, and changes the information written into the storage device 16 to the selected word information. Create corresponding check information.

Information reading from the input storage device 11 progresses in this manner, and when reading of one record information is completed, the record delimiter code BeJ is output, and the code detection circuit 13 detects the code code BeJ.

When this code rBeJ is detected, the read selection circuit 14 is returned to its initial state, and the check information created by the first and second check information creation circuits 17 and 18 is outputted by the output of the delay circuit 19, respectively. be done.

At this time, a coincidence detection circuit comparison command is given at the same time, and the check information following the code 1,000BeJ is sent from the input storage device 11 to the coincidence detection circuit. It is coupled to the output circuit 20 and compares the check information created by the check information creation circuit 17 with the check information read from the input storage device 11.

Then, by obtaining a coincidence detection signal from the coincidence detection circuit 20, it is confirmed that the information read from the input storage device 11 is accurate.

Furthermore, the output of the delay circuit 19 opens the gate of the AND circuit 21 and increments the address counter 24, so the check information created by the second check information creation circuit 18 is
The processing information is written to the processing report storage device 16, and this storage device 16
be used to check the stored information.

Then, based on the coincidence output of the coincidence detection circuit 20, the count value of the address counter 24 at that time, that is, the address address of the processing information storage device 16 to be written next, is shifted to the address memory 26 via the AND circuit 22,
Make me remember.

Furthermore, if there is an error in the information 1 read from the input storage device 11, the coincidence detection circuit 20 will not obtain a coincidence output, but a mismatch output.

When this mismatch output is obtained, a gate signal is applied to the AND circuit 23 to shift the storage address of the address memory 26 to the address counter 24.

That is, since the record information read up to that point is not accurate and there is a possibility that the extracted word information written in the processing information storage device 16 also has an error, the information corresponding to the record information is written at the writing position Ia. The address designated address of the address counter 24 is returned to the previous address, and the written information up to that point is erased in response to the next information input.

At the same time, a reread command is given to the input storage device 11 based on the mismatch output, and record information in which an error has occurred in the read information is read out again, so that accurate processing information is extracted.

Here, the parity check information added to the record information stored in the input storage device 11 and written in the processing information storage device 16 can be of various kinds, but for example, it is configured as follows.

For example, as shown in A in Figure 2, bit information is transmitted serially, so bit information is detected every other bit as shown in B in Figure 2, and the detected bin information is transmitted serially. The number of bits in one state where the information is "1" or "0" is counted.

Then, 1-bit check information of "1" or "o" is created depending on whether the counting result is an odd number or an even number.

In addition, as shown in C, D, and E in Figure 2, the transmitted information is detected every 2 bits at a time, every 4 bits at every 4 bits, and every 8 bits at every 8 bits. , respectively, the detection bit is “1” or “
The bits in the "0" state are counted to create odd/even discrimination bit information as described above.

Then, bit information corresponding to the results of this odd/even discrimination is used as parity check information. In this way, when check information is created with 4 bits as shown in Figure 2, up to (16-1) bits It is possible to accurately check transmitted information. For example, if the check information is 16 bits, it is possible to perform a parity check on information of 60,000 bits or more.

Then, all bits of the transmission information are detected as shown in FIG. By using a combination of the check information created with the different pit synchronizations described above, a more reliable validity check can be performed.

FIG. 8 shows a specific configuration example of, for example, the first check information creation circuit 17 section for creating parity check information as described above, and shows a case where the check information is composed of n bits. ing.

That is, the information read out from the input storage device 11 is
It is supplied in parallel to n AND circuits 271, 272, 27n and a pinary counter 28x, and
The binary pinary counters 281, 282, . . . , 28n are driven to count by the output signals 71 to 27n, respectively.

Further, in response to a read command to the input storage device 11, a counter circuit 26 is provided which is driven in synchronization with bit reading.

This counter circuit 26 generates n counting outputs with a bit period that is sequentially doubled, and gives a gate signal to the AND circuits 271 to 27n, which sequentially double the output as shown in FIG. An input storage device 11 with a bit period of
The continuation bit information from is detected.

In the case of this figure, bits that become "1" are counted by binary pinary counters 281 to 28n, and the counting results, that is, counting output signals corresponding to odd and even numbers, are sent to AND circuits 291 and 292. ...binds to 29n.

Further, the reset output of the delay circuit 19 in FIG.

That is, the AND circuit 32 generates a one-shot output signal at the rising edge of the reset signal, and drives the n+2-base counter 33, which is also driven to count in synchronization with bit transmission.

Then, by this counter 33, the AND circuit 29X,
291 to 29n are sequentially given gate signals, the counting results of the pinary counters 28X and 281 to 28n are sequentially read out, and the OR circuit 34 obtains serial n+1 bit parity check information output. 28X, 281, and so on.

FIG. 4 shows a counter circuit 26, a pinary counter 281,
282... section is shown in more detail, and this figure shows the case (n=4).

That is, the read command is coupled to the AND circuit 35 as a gate signal, and a clock signal output during reading is obtained from the AND circuit 35. This clock signal drives the writing and reading of the flip-flop circuits 361-364.

AND circuits 371 to 374 are provided on the input side of the flip-flop circuits 361 to 3640, and gate signals are supplied to the AND circuits 371 to 374 from the inverter 38 to which the reset input is coupled, and the gate signal is supplied when there is no reset input. be able to do so.

The gates of AND circuits 271 to 274 are controlled by the output signals of inverters 391 to 394 coupled to the output terminals of flip-flop circuits 361 to 364. Combine clock signals.

The output of the inverter 391 is then coupled to the AND circuit 371, and the flip-flop circuit 361 obtains an output signal every other bit in synchronization with the transmission information, and the inverter 391 outputs the bits shown in B in FIG. Generates an output signal at regular intervals.

Also, AND circuits 402 to 404, OR circuits 412 to 4
14. By the circuits of inverters 422 to 424, inverters 392 to 394 output signals C, D, and E in FIG.
The output is generated at the bit period shown in , and the gates of the AND circuits 271 to 274 are controlled to detect the bit at the respective bit period, and when the bit that becomes 1-1 is detected, the pi This is to increment the number counters 281-284.

In the figure, the AND circuit 27x detects all the bits of the data input and drives the pinary counter 28X in response to the bit that becomes "1". It is something that does.

Although the above check information creation means has been explained as the first check information creation circuit 17, the second check information creation circuit 18 is also configured in the same manner and is stored in the input storage device 11. Parity check information added to record information is also created by the same means.

〔Effect of the invention〕

As described above, according to the present invention, not only parity check information is added to each record information unit of input information, but also a new Parity check information is also added to record information.

Therefore, for example, the information read from the information storage section is effectively checked, and at the same time, the processing information processed based on this read information is also stored and set with parity check information added. ,
In addition to improving the reliability of information processing, it has a great effect on improving the reliability of newly formed processing information during subsequent processing operations, and it can be applied to information processing systems such as various computer devices. The effect is remarkable.

As mentioned above, it goes without saying that the present invention is not limited to the matters described above, and can be applied in various ways without departing from the gist thereof.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating an information processing device according to an embodiment of the present invention, FIG. 2 is a diagram illustrating a means for configuring parity check information used in the information processing device, and FIG. FIG. 4 shows an example of the check information creation circuit of the embodiment.
The figure is a diagram illustrating a counter circuit section of the check information creation circuit. 11... Input storage device, 13... Code detection circuit, 14... Read selection circuit, 16
...Processing information storage circuit, 17, 18...
Check information creation circuit, 20... Match detection circuit, 24... Address counter, 26...
・Address memory.

Claims (1)

[Claims] 1 A plurality of record information, which is formed by arranging a plurality of word information in series, each separated by a word delimiter code, is arranged in series via a record delimiter code, and the parity check information for each record information is an input storage device for storing input information arranged in correspondence with record delimiter codes; a first check information creation means for creating parity check information for record information read from the input storage device; means for selecting specified word information in response to word delimiter code detection in record information that is sequentially read; a processing information storage device for storing the selected word information; and a word of the specified word information. a second check information creation means for creating parity check information corresponding to information controlled by delimiter code detection and written to the processing information storage device; and parity check information created by the second check information creation means. means for coupling and storing a record delimiter code in the processing information storage device in response to reading of a record delimiter code from the input storage device; and generating the first check information for parity check information for each record information read from the input storage device. An information processing device comprising means for performing a comparison check with parity check information created by the means.