JPS5814771B2 - analog to digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width modulation type analog-to-digital converter.

Generally, in a pulse width modulation analog-to-digital converter, a filter circuit converts a pulse width signal into an analog value, compares it with an analog human input signal, and controls the pulse width signal so that the two are equal.

For this reason, the time constant of the filter circuit must be increased to 3 to 4 times the period of the pulse width signal to convert the pulse width signal into an analog value with a small ripple, which has the disadvantage that the conversion time is extremely long. .

In the present invention, a filter circuit with a small time constant is used to convert a pulse width signal into an analog value with a large ripple value, which is compared with an analog input signal in a comparator, and the pulse width is adjusted so that the output duty ratio is 50%. By controlling the signal, a pulse width modulation type analog-to-digital converter with short conversion time is realized.

The converter of the present invention will be explained below using the drawings.

FIG. 1 is a block diagram showing one embodiment of the converter of the present invention.

In FIG. 1, 1 is an input terminal to which an analog input signal Ei is applied, 2 is an output terminal from which a digital output signal Do is generated, and 3 is an analog comparator, which outputs an input signal Ei and a feedback signal Ef.
The output a becomes I"H" level when Ei>Ef, and inverts to "L" level when Ei<Ef.

4 is an error detection section that detects the difference between Ei and Ef in the form of the number of pulses.

As the error detection section 4, a 10-bit reversible counter is used that adds clock pulses CP when the comparator output a is at "H" level and subtracts it when it is at "L" level.

5 is a scaler section which multiplies the error detection section output b by a coefficient 1/K.

As the scaler section 5, a frequency divider that divides the number of clock pulses corresponding to the error detection section output b according to a frequency division ratio K is suitable.

6 is a reversible counter, which outputs a pulse C from the scaler section 5.
Count.

7 is a pulse width signal generating section, and the count value d of the town counter count 6 is
is converted into a pulse width signal f.

The pulse width signal generator 7 includes a 10-bit counter 1 that counts clock pulses CP, and a digital comparator 72 that compares the count value d of the reverse counter 6 with the count value e of the counter 1.

The output f of the digital comparator 72 becomes "H" level when the counter 71 starts counting, and is inverted to "L" level when the count value e of the counter 71 exceeds the count value d of the town counter 6.

The "L" level state continues until counter 1 counts 1000 pulses and is reset.

Therefore, the output f becomes a pulse width signal whose pulse width t is determined by the product of the count value d of the reversible counter 6 and the clock pulse CP.

Note that the period T of the pulse width signal f is determined by the number of bits of the counter 71, and is constant at 1000 counts in this embodiment.

A switch circuit 8 is driven by a pulse width signal f to turn on and off the reference voltage Er.

9 is a filter circuit consisting of a capacitor C and a resistor R.
The voltage turned on and off by the switch 8 is smoothed and applied to the analog comparator 3 as a feedback signal Ef.

The time constant of the filter circuit 9 is selected to be relatively close to the period T of the pulse width signal f.

The operation of the present invention configured as described above will be explained below using FIG. 2.

The feedback voltage Ef obtained by driving the switch circuit 8 and turning the reference voltage Er on and off using the pulse width signal f (see Fig. 2 A) and smoothing it in the filter circuit 9 is determined by the time constant of the filter circuit 9 relative to the period T. Since the values are selected to be relatively close to each other, there is a large ripple component as shown in the opening of Figure 2.

A large voltage Ef corresponding to this ripple is applied to the analog comparator 3 and compared with the human input signal Ei.

As a result, the comparator output a becomes as shown in FIG. 2C, and the error detection section 4 adds or subtracts the clock pulse CP depending on the comparator output a.

Therefore, the output b of the error detection section 4 at the end of one cycle is E
The number of pulses is proportional to the difference between 1 and Ef.

The detected value b of the error detection unit 4 is given to the reversible counter 6 via the scaler unit 5 within the ΔT time at the end of each cycle,
The count value d of the town reverse counter 6 is corrected.

Here, if ΔT is made sufficiently smaller than the period T, the influence on the system can be ignored.

In this way, the pulse width signal generator 7→switch circuit 8→filter circuit 9→analog comparator 3→error detector 4
A loop consisting of →scaler section 5→reversible counter 6→pulse width signal generator 7 continues oscillation while changing the magnitude of the pulse width t every cycle.

The pulse width tn of a certain period is the previous pulse width tn-1
Then, it is determined by tn=tn-1+1/Kb.

Finally, the detection value b of the error detection section 4 at the end of one cycle is zero, that is, the duration ota/T of the output a of the analog comparator 3 (where ta is the time when a is at the "H" level) is When it reaches 50%, the pulse width t does not change in the next cycle and becomes stable.

When the input signal Ei changes stepwise, the pulse width t
Figure 3 shows how the changes.

Moreover, as shown in FIG. 4, the tracking speed of the pulse width t with respect to a step change in Ei becomes faster when the coefficient K of the scaler section 5 is made smaller, and becomes slower when it is made larger. The value of exists.

Then, the detection value b of the error detection unit 4 at the end of one cycle
In a stable state where is zero, the input signal Ei and the feedback signal Ef
The pulse width t, that is, the count value d of the counter 6 is proportional to the input signal Ei.

Therefore, by taking out the count value d of the reversible counter 6 to the output terminal 2, a digital signal Do proportional to the analog input signal Ei can be obtained.

By the way, in general, in an analog-to-digital converter that converts an analog quantity into a pulse number, the number of counts must be increased in order to improve the resolution.

However, since the frequency of the clock pulse is generally close to the hardware limit, it is difficult to increase the frequency of the clock pulse.

Therefore, the number of bits of the reversible counter must be increased.

Increasing the number of bits will slow down the conversion speed.

For example, in order to increase the resolution by one order of magnitude, the conversion speed will decrease by one order of magnitude.

Therefore, as shown in the embodiment shown in FIG.
The count value d of is digitally computed by the arithmetic processing circuit 10, and (
By generating the digital signal Do in the form of d±b) at the output terminal 2, the resolution can be increased without reducing the conversion speed.

Now, the ripple voltage of Ef, the reference voltage of Ep', and the number of pulses counted by the error detection section 4 during one cycle are set to 1000.
If it is a pulse, the resolution of the detected value b of the error detection unit 4 is:
(±1/1000·Ep/Er).

And Ep is relatively large, for example, if it is 1V, then Ep is
By choosing r to be 10V, the resolution of b is 0.01%.
becomes.

Furthermore, if it is desired to increase the follow-up speed for a step change in E1, the coefficient K of the scaler section 5 may be made small, but if K is made small, the loop gain will be increased and the stability of the system will deteriorate.

Therefore, in the embodiment shown in FIG. 6, the detection value b of the error detection section 4 is monitored, and when the detection value b exceeds a certain range, the scaler section 4
Means 1 for switching the value of the coefficient K from a large value to a small value
1 is provided to increase the tracking speed without sacrificing the stability of the system.In other words, when the detected value b is large, the value of the coefficient K is switched to a small value, and the value of the pulse width t is greatly modified. In this way, the system The tracking speed could be made about twice as fast as that of the embodiment shown in FIG. 1 without sacrificing stability.

Figure 4 shows this relationship.

Furthermore, with recent advances in daily circuit technology, processors such as microcomputers have become smaller and can be done manually at low cost. 1
The daisicle control section surrounded by chain lines in the figures, FIGS. 5 and 6 may be replaced by a processor.

In this case, there is an advantage that the digital signal Do can be further subjected to arithmetic processing such as square root, multiplication and division, and then outputted to the output terminal 2.

Note that the time required for these calculations is extremely short, several ms, so this does not pose a problem.

As explained above, in the present invention, a filter circuit with a small time constant is used to convert a pulse width signal into an analog value with a large ripple value, which is compared with an analog input signal by a comparator, and the duty ratio of the output is 50%. Since the pulse width signal is controlled so that

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the converter of the present invention;
FIGS. 2, 3, and 4 are operation explanatory diagrams, and FIGS. 5 and 6 are block diagrams showing other embodiments of the converter of the present invention. 3... Analog comparator, 4... Error detection section, 5... Scaler section, 6... Reversible counter, 7... Pulse Width signal generation section, 8...
...Switch circuit, 9...Filter circuit,
10... Arithmetic processing unit.

Claims (1)

[Claims] 1. An analog comparator that compares an analog input signal and an analog feedback signal, and a period during which the input signal is greater than the feedback signal and a period during which the input signal is greater than the feedback signal according to the output of the analog comparator. an error detection section that detects the difference in period that is smaller than the feedback signal by the number of pulses; a scaler section that multiplies the output of the error detection section by a coefficient; a reversible counter that counts the output of the scaler section; A pulse width signal generator that converts the counted value of the counter into a pulse width signal, a switch circuit that is driven by this pulse width signal and turns the reference voltage on and off, and a voltage that is turned on and off by this switch circuit into a large analog value corresponding to the ripple. The pulse width signal is controlled so that the output of the error detection section becomes zero, and the pulse width signal is controlled so that the output of the error detection section becomes zero. A pulse width modulation type analog-to-digital converter characterized in that a digital output is obtained from a reverse counter. 2. The analog-to-digital converter according to claim 1, wherein the digital value obtained by adding the output of the error detection section to the count value of the reversible counter is output as a digital signal. 3. Analog-to-daisicle conversion according to claims 1 and 2, characterized in that the output of the error detection section is monitored, and when the output exceeds a certain range, the coefficients of the scaler section are switched. vessel. 4. The analog system according to claims 1, 2, and 3, characterized in that the functions of the error detection section, scaler section, reversible counter, and pulse width signal generation section are performed by a processor. Digital converter.