JPS5815751B2 - densid cay - Google Patents
densid cayInfo
- Publication number
- JPS5815751B2 JPS5815751B2 JP49012355A JP1235574A JPS5815751B2 JP S5815751 B2 JPS5815751 B2 JP S5815751B2 JP 49012355 A JP49012355 A JP 49012355A JP 1235574 A JP1235574 A JP 1235574A JP S5815751 B2 JPS5815751 B2 JP S5815751B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- display element
- clock
- gate
- display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000010355 oscillation Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
Landscapes
- Electric Clocks (AREA)
Description
【発明の詳細な説明】
本発明は、電子時計の表示とその駆動回路に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece display and its driving circuit.
本発明の目的は、デジタル表示のもつ時刻の読みやすさ
と、アナログ表示のもつ連続的な動きとをかね供えた電
子時計である。An object of the present invention is to provide an electronic timepiece that provides both the ease of reading the time of a digital display and the continuous movement of an analog display.
時２分時刻をデジタル表示で表わし、秒時刻を振り子を
シュミレートしたアナログ表示で表わすことにより、電
子光学的表示のもつ現代的効果と振り子のもつ古典的効
果とを同時に表現でき、時計の商品価値を非常に高める
。By displaying the hour, 2 minutes, and minutes on a digital display, and the seconds on an analog display that simulates a pendulum, it is possible to simultaneously express the modern effect of an electro-optical display and the classical effect of a pendulum, which increases the commercial value of the watch. greatly enhances
次に本発明の実施例を図面により説明する。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の回路図である。FIG. 1 is a circuit diagram of the present invention.
１は発振・分周回路であり、１０Ｈ２のパルスを作る。1 is an oscillation/frequency dividing circuit, which generates a 10H2 pulse.
２は秒信号計数回路であり、発振・分周回路１からの送
られる１ＯＨｚのパルスを０〜９の出力から順に取り出
す動作と、１７１０分周をして１Ｈｚのパルスを作る動
作とを行う。Reference numeral 2 denotes a second signal counting circuit, which performs the operations of sequentially extracting the 1 OHZ pulse sent from the oscillation/frequency divider circuit 1 from the outputs 0 to 9, and the operation of dividing the frequency by 1710 to create a 1 Hz pulse.
３は時計回路であり、秒信号計数回路２から送られる１
Ｈｚのパルスを時・分時刻を７セグメントにデコードし
て送り出す。3 is a clock circuit, and 1 is sent from the second signal counting circuit 2.
The Hz pulse is decoded into 7 segments of hours and minutes and sent out.
４，５゜６．７．８は秒駆動回路を構成するＯＲゲート
であり、秒信号計数回路２から送られる０〜９までの出
力を組み合せて、表示回路に送り込む。Reference numeral 4, 5° 6.7.8 is an OR gate constituting the second drive circuit, which combines the outputs from 0 to 9 sent from the second signal counting circuit 2 and sends them to the display circuit.
９は秒時刻表示素子である。9 is a second time display element.
１０は時・分時刻表示素子である。10 is an hour/minute time display element.
又、９．１０は液晶２発光ダイオード等の電子光学的表
示素子を用いる。Further, 9.10 uses an electro-optical display element such as a liquid crystal dual light emitting diode.
初めに発振・分周回路１からの１０Ｈｚの信号を秒信号
計数回路２により１Ｈｚ信号にして時計回路３へ信号を
送ると同時に、ＯＲゲート４，５，６，７，８へ１０Ｈ
ｚのパルスを送り込む。First, the 10Hz signal from the oscillation/frequency dividing circuit 1 is converted into a 1Hz signal by the second signal counting circuit 2 and sent to the clock circuit 3, and at the same time, the 10Hz signal is sent to the OR gates 4, 5, 6, 7, and 8.
Send a pulse of z.
ＯＲゲート４は０番目と５番目の出力、ＯＲゲート５は
１番目と４番目の出力、ＯＲゲート６は２番目と３番目
の出力、ＯＲゲート７は６番目と９番目の出力、ＯＲゲ
ート８は７番目と８番目の出力が入るよう回路は配線さ
れているので、ＯＲゲートは、４，５，６，５゜４．７
，８，７，４の順でゲートを開き、１秒間に１往復する
。OR gate 4 has the 0th and 5th outputs, OR gate 5 has the 1st and 4th outputs, OR gate 6 has the 2nd and 3rd outputs, OR gate 7 has the 6th and 9th outputs, OR gate The circuit is wired so that the 7th and 8th outputs enter 8, so the OR gate is 4, 5, 6, 5° 4.7
, 8, 7, and 4, and make one round trip per second.
ＯＲゲートの出力は、秒時刻表示素子９に接続され、お
のおののＯＲゲート出力に接続された各表示素子はＯＲ
ゲートの開いている間、点灯する。The output of the OR gate is connected to the second time display element 9, and each display element connected to each OR gate output is connected to the second time display element 9.
Lights up while the gate is open.
時計回路３とその出力に接続された時・分時刻表示素子
は公知のものであるので、説明は省略する。Since the clock circuit 3 and the hour/minute time display element connected to its output are well known, their explanation will be omitted.
第２図は、本発明の表示部の配置図である。FIG. 2 is a layout diagram of the display section of the present invention.
４’。５’、６’、７’、８’は点で表わされた秒表示
素子で、第１図の秒時刻表示素子９を構成するものであ
り、前記ＯＲゲート４．５，６，７．８とそれぞれ接続
されている。4'. 5', 6', 7', 8' are second display elements represented by dots, which constitute the second time display element 9 in FIG. 1, and the OR gates 4.5, 6, 7. 8 are connected to each other.
１０Ｈｚの速さで、４’、５’、５’。６’、 ５’、
４’、 ７’、 ８’、 ８’、 ？’の順に１秒間
に１往復点灯され、かつ１０Ｈｚと比較的速いので連続
的に見える。4', 5', 5' at a rate of 10 Hz. 6', 5',
4', 7', 8', 8', ? The lights are lit back and forth once per second in the order of ', and the frequency is relatively fast at 10Hz, so it appears to be continuous.
又、６’、８’は５Ｈｚの速さになるので、−瞬止まっ
たかのごとく見える。Also, since the speeds of 6' and 8' are 5 Hz, it appears as if there was an instantaneous stop.
このように配置することにより、時計の振り子のごとく
シュミレートすることができる。By arranging it in this way, it is possible to simulate the pendulum of a clock.
１０’は時と分の時刻表示を示す。10' indicates a time display of hours and minutes.
以上、本発明の１実施例であり、振り子を往復させる時
間や点灯する表示素子の数を変えることも可能である。The above is one embodiment of the present invention, and it is also possible to change the time during which the pendulum moves back and forth and the number of display elements to be lit.
第１図は、本発明の回路図である。 第２図は第１図の表示装置の配置図である。 ４’〜８’・・・・・・秒表示素子。 FIG. 1 is a circuit diagram of the present invention. FIG. 2 is a layout diagram of the display device of FIG. 1. 4' to 8'...Second display element.
Claims (1)
電子光学的表示素子を有する電子時計に於いて、前記電
子光学的表示素子には複数の表示素子を配列してなる秒
表示素子を設けるとともに前記秒信号計数回路に接続さ
れた秒駆動回路を設け、該秒駆動回路は、秒信号計数回
路の出力信号に従って前記秒表示素子をその一端から他
端に向って順次点灯するとともに他端に於いて順次点灯
の方向を反転させることにより前記秒表示素子を時計の
振り千秋に駆動することを特徴とする電子時計。1 Oscillation circuit, frequency dividing circuit, second signal counting circuit, clock circuit,
In an electronic timepiece having an electro-optical display element, the electro-optical display element is provided with a second display element formed by arranging a plurality of display elements, and a second drive circuit connected to the second signal counting circuit. , the second drive circuit sequentially lights up the second display element from one end to the other end according to the output signal of the second signal counting circuit, and sequentially reverses the direction of lighting at the other end, thereby controlling the second display element. An electronic clock that is driven by the clock's movement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49012355A JPS5815751B2 (en) | 1974-01-30 | 1974-01-30 | densid cay |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49012355A JPS5815751B2 (en) | 1974-01-30 | 1974-01-30 | densid cay |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS50107971A JPS50107971A (en) | 1975-08-25 |
| JPS5815751B2 true JPS5815751B2 (en) | 1983-03-28 |
Family
ID=11802960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49012355A Expired JPS5815751B2 (en) | 1974-01-30 | 1974-01-30 | densid cay |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5815751B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5816585U (en) * | 1981-07-22 | 1983-02-01 | 株式会社東芝 | time notification device |
-
1974
- 1974-01-30 JP JP49012355A patent/JPS5815751B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS50107971A (en) | 1975-08-25 |
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