JPS5815808B2 - Digital Bibun Kaisekiki - Google Patents

Description

[Detailed description of the invention] The present invention relates to a digital differential analyzer.

The calculations of digital differential analyzers (hereinafter abbreviated as DDA), which have traditionally been used as a means of obtaining solutions to differential equations, are based on digital integrators, and numerical calculations are performed by connecting multiple digital integrators. urge

The integrator is described in detail in literature (for example, Computer Handbook, Volume 8, Chapter 3, edited by Information Processing Society of Japan), so it will be omitted here, but its basic operation is based on the piecewise quadrature method.

In a DDA that has a plurality of digital integrators (hereinafter abbreviated as integrators), if the number is relatively small, the integrators are connected in parallel and operated simultaneously, or the number of integrators is If there are many integrator calculation circuits, one
or multiple units (17 n units, n is an integer)
Conventionally, a method has been adopted in which the numerical values in each integrator are stored in a storage device and calculations are performed sequentially in a time-sharing manner.

The former is called a parallel type DDA, and the latter is called a serial type DDA, and the latter is generally put into practical use.

The serial type DDA will be described below.

This serial type DDA has fewer arithmetic circuits and control circuits and is economical, but it has the following drawbacks.

Now, the integrator B which performs the calculation in the i-th step will be explained with reference to FIG.

In Fig. 1, if the order of operations of the integrator is A, B, and C, the output △ZA of integrator A is the output at the i-th calculation step, but the output Zc of integrator C is i- This is the output in the i-th calculation step.

Here, Y is an integrand, R is its remainder, ΔZ is an integral value of the integrand, and ΔX is an integral independent variable.

Therefore, when performing an operation using data provided by integrator A, the operation is performed based on equation (1), and when performing an operation using data provided from integrator C, it is performed based on equation (2). It is necessary to perform calculations.

That is, when performing the same integration, there is a problem that the integration method must be changed depending on whether the input is taken from the preceding integrator or the succeeding integrator.

In actual arithmetic circuits, these inputs often coexist, as in integrator B, but it is up to the program to determine whether the data is from the preceding integrator or the following integrator and change the integration method. There are few examples in which this method is implemented due to the complexity and reduction in calculation speed, and in such cases, calculations are generally performed using equation (3), which is the average of equations (1) and (2).

This has led to problems such as an adverse effect on calculation accuracy.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide DI)A which uses a serial operation method using a storage device and performs operations similar to a parallel operation method.

This will be explained in detail below with reference to the drawings.

FIG. 2 is a block diagram of the DDA of the present invention.

In Figure 2, DM is a storage device that stores various numerical values necessary for DDA calculations, the part surrounded by broken lines is the part that performs calculations, and the part surrounded by dashed dotted lines is the part that performs control. It is.

FIG. 3 is a diagram showing a method of storing numerical values stored in the DM of FIG. 2.

To simplify the explanation, the capacity of DM is assumed to be 2n words.

The feature of the present invention lies in the method of storing and addressing this numerical value.

In other words, the input variable is the quadratic increment △Y and the integral value is 3.
The storage address of the next increment △Z is the starting address O of each DM.
Then, one word is defined as one word up to address 1-1 and from the final address N=2n-1 in the direction of the first address, and other numerical values Y, R, ΔXΣΔY are stored in the remaining part.

(l is an integer and changes depending on the calculation target.

) In FIG. 3, △Y is △Z of the preceding integrator, so △Y is represented by △Zi-1.

The numerical value stored at the address is determined as the read or write address as follows.

In this case, the address is expressed in binary code.

That is, in the phase of reading △Y from DM and the phase of writing △Z, the output read from the storage device CM in which the address of DM is stored (A□ in Fig. 4).
Each bit Ai of n bits consisting of -Am 1 is changed to each bit A4)i of the address shown by equation (4) via the control circuit CG.

(Tazoshi Σ represents a bit string.

) In (4), Rs and Ws are the read strobe and write strobe for the DM, respectively,
S is the output of a flip-flop whose state is inverted every time the calculations of all the arithmetic units complete one cycle, FR2FW represents the phase of reading △Y and the phase of writing △Z, ■ is the exclusive OR, and Logical sum, ・is logical product (
FOR each of the following.

(abbreviated as OR, AND).

Now, equation (4) will be explained using FIG. 5 below.

When the calculation is started and now S=0, equation (4) becomes equation (5)
This indicates that only when there is a write strobe in the write phase of △Z, the CM output, for example, Ai, is set to a negative value to determine the DM address and write △Z.

That is, in the case of S-0, △Z stored in one word from the first address in FIG. 3 is read out, and the first △Z is written into the address of one word from the last address.

Similarly, when all calculation units have completed a cycle of calculations, S=1 is set by the control circuit C in FIG.

This era (4) becomes equation (6). That is, only when there is a read strobe in the read phase of ΔY, the CM output, for example, Ai, is set to a negative value to determine the DM address and ΔY is read out.

Therefore, the read address in this case indicates the address Ai of △Zj that was previously written at S-0, so △Yj that is read is the value one calculation step ago.

Also, when writing △Zi, leave the CM output at a positive value.
Since the DM address is determined, the address at this time is ΔZi read out one calculation step ago, that is, the result of two calculation steps ago, and is unnecessary data.

Therefore, even if a new ΔZi is stored here, there will be no problem with the calculation.

In the same way, once the calculations have completed for all the arithmetic units, it becomes S-0 again and the address is specified using the same procedure.Since the DM address is specified as described above, the preceding integrator is Even when the outputs of the DDA and the subsequent integrator are mixed, the same processing as the parallel DDA can be performed.

In other words, when integrator B performs the i-th operation in FIG. i by the procedure described above from
By reading out the calculation results in the -1st step, calculations can be performed with high precision using the same integration method (2).

In Figure 3, the storage capacity of the DM was explained as 2n words, but most of the storage devices in practical use are 2n words, so there is no problem in practical use, but when the storage capacity is other than 2n words, the memory capacity is shown at the beginning as shown in Figure 6. One word from the address and one word from the 2n-1 address in the direction of the first address are taken as the storage address of ΔZ.

Here, 2n+K< 2 n'+ '-1.

In this case, the remaining addresses are Y, R as in the case of Figure 3.
, ΔX, etc.

The bits of the address to which Tazoshi formula (4) is applied are from the lower bit to n-1.

Furthermore, the DDA is composed of a plurality of serial operation type DDAs as shown in FIG.
Group A is called a module.

) A method for storing data in a serial-parallel DDA in which these modules perform operations simultaneously will be described.

The calculations in FIG. 5 are performed by a control circuit called a DDA controller DDAC, and each module m1 to mn
Data transfer between the two is performed by the DDAC via the pass line S for each calculation step.

In such a configuration, the calculations of each module are performed in parallel, and the results are the calculation results at the same time in any calculation step, so that the same processing as in the parallel type DDA can be performed.

That is, the connection between modules saves △Z from one calculation step ago, and △Z between modules is stored in the same area as Y, R, △XΣ△Y, and is read out as necessary.

The procedure for specifying the address of the DM in FIG. 2 using the method described above and executing the calculation according to FIG. 2 will be described below.

In FIG. 2), control signals in the portion surrounded by broken lines are omitted, but all these controls are performed by control signals from the control circuit C.

To simplify the explanation, the case where the i-th operation is performed is S-0.

shall be. First, all buffer registers BRn (n=1~
4) is cleared, and DM sets ΔZ (that is, ΔYi-1) in BF2 according to equation (5).

At this time, the address of DM is indicated by the positive value of the output A of the control memory IJcM specified by the control circuit C.

Next, BRl and BF2 are added by adder Σ□ and set in accumulator AC1.

If △Yi-1 further exists, the content of ACl is B
Another ΔYi-1 set in Rl and read out from DM according to equation (5) is set in BF2 and the same process is performed.

When all △Y i-1 are added, the result is ACl
can be obtained.

At this time, △X is read from the DM, and if △X = 0, the contents of ACl are stored in the DM as Σ△Yi and the process moves on to the next arithmetic unit, and when △X\0, the contents of ACl are It is set to BRl and Y i -1 is read from DM to BH3.

This DM address is determined by the CM output, and the CM
is sequentially updated by C.

Now, when the contents of BH3 and BRl are determined from ACl by Σ1, they are set to BH3 via selector SL2.

At this time, BR1 is multiplied by 1/2 and the contents of ACl are stored in DM as Yi.

Next, BRl is subtracted from BH3 and set to ACl.

Furthermore, BH3 reads Ri-1 from DM and has an adder Z.
2, the ACI fish is added when △X>O, and subtracted when △X<O.

When an overflow occurs as a result of the operation using Σ2, set +△Zi, when no overflow occurs and Σ2 is 0, set 1△Zi, and when no overflow occurs and Σ2>0, set 0 to BH3. The result is stored as Ri in DM via SL,1.

Furthermore, since the value set in BH3 is S-0 and it is the write phase, the output of CM is made a negative value according to equation (5), the address of DM is determined, and ΔZ is written.

The calculations are performed sequentially using the above-mentioned flat head.

As described above, according to the present invention, there is no need to change the integration method depending on the connection of the arithmetic units, and it is possible to perform processing equivalent to parallel calculation by simple control, and the effect is excellent.

[Brief Description of the Drawings] Fig. 1 is a diagram for explaining the problems of the conventional DDA, Fig. 2 is a diagram for explaining the operation of the DDA of the present invention, Fig. 3,
FIG. 6 is a diagram showing a data storage method of the DDA of the present invention;
Fig. 7 is a block diagram of a serial-parallel operation type DDA, Fig. 4) is a diagram showing the binary code output of the storage device CM in which addresses are stored, and Fig. 5 explains the addressing method of the present invention. This is a time chart for A, B, C... Integrator.

Claims (1)

[Claims] A calculation means for performing a predetermined calculation consisting of 11 or more calculation steps, and a calculation means for storing the calculation results based on the predetermined calculation. a first storage means having a
a second storage means for storing address information of the storage means as a binary code; and a state register means whose state changes alternately between a 0 state and a 1 state each time each calculation step in the predetermined calculation is completed. , changing the state of the register means and generating a read strobe signal and a write strobe signal for the first storage means, and in response to the strobe signals, from the binary code read from the second memory means. control means for controlling the generation of addresses in the first storage means, from address 0 in the first storage means to addresses (lt) (l is a positive integer smaller than 2n) and (2n-); 1-
l) A phase in which the cubic increment among the calculation results is stored from the address to address (2n-1), and the cubic increment is read out from the first storage means in each calculation step; For each phase of writing an increment to said first storage means, said state register means is in the 1 state and said read strobe signal is generated and said state register means is in the O state and said write strobe signal is generated. When the binary code is read from the second storage means, the polarity of the lower n bits or (n-1) bits is inverted and used as an address in the first storage means, and the state register means is in the 1 state and the write strobe signal is generated, and when the status register means is in the 0 state and the read strobe signal is generated, the lower order of the binary code read from the second storage means. A digital differential analyzer characterized in that the control means performs control such that n bits or (n-1) bits from 1 to 1 are set as an address of the first storage means.