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JPS5815959B2 - Method for manufacturing transparent laminated wiring board - Google Patents
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JPS5815959B2 - Method for manufacturing transparent laminated wiring board - Google Patents

Method for manufacturing transparent laminated wiring board

Info

Publication number
JPS5815959B2
JPS5815959B2 JP16893979A JP16893979A JPS5815959B2 JP S5815959 B2 JPS5815959 B2 JP S5815959B2 JP 16893979 A JP16893979 A JP 16893979A JP 16893979 A JP16893979 A JP 16893979A JP S5815959 B2 JPS5815959 B2 JP S5815959B2
Authority
JP
Japan
Prior art keywords
wiring board
transparent
laminated wiring
melting point
transparent laminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16893979A
Other languages
Japanese (ja)
Other versions
JPS5691491A (en
Inventor
上條芳省
中野渡旬
藤岡和則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP16893979A priority Critical patent/JPS5815959B2/en
Publication of JPS5691491A publication Critical patent/JPS5691491A/en
Publication of JPS5815959B2 publication Critical patent/JPS5815959B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 本発明は透明積層配線基板の製造方法に係り、特に発光
ダイオード(LED)、液晶(LCD)、エレクトロル
ミネッセンス(EL)等の表示素子の実装に好適な透明
積層配線基板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a transparent laminated wiring board, and in particular, a transparent laminated wiring board suitable for mounting display elements such as light emitting diodes (LEDs), liquid crystals (LCDs), and electroluminescence (EL). Relating to a manufacturing method.

積層配線基板としては従来プラスチック系−銅張り配線
板又はセラミック系−メタライズ配線板等が一般的であ
る。
Conventionally, the laminated wiring board is generally a plastic-copper-clad wiring board or a ceramic-metallized wiring board.

これら配線板は相応の特徴を有するが不透明のため透明
が要求されるLED。
These wiring boards have appropriate characteristics, but since they are opaque, LEDs require transparency.

LCD、EI、ECD(エレクトロクロミックディスプ
レイ)等の表示素子を実装するには不向きであった。
It was not suitable for mounting display elements such as LCD, EI, and ECD (electrochromic display).

従って、本発明は表示素子を実装するに好適な透明の積
層配線基板を提供できると共に、製造性が良く信頼性の
高い比較的低コストの積層配線板の製造方法を提供する
ことを目的とする。
Therefore, an object of the present invention is to provide a transparent laminated wiring board suitable for mounting display elements, and also to provide a relatively low-cost manufacturing method for a laminated wiring board with good manufacturability and high reliability. .

以下本発明に係る製造方法の実施例を図面に従って詳細
に説明する。
Embodiments of the manufacturing method according to the present invention will be described in detail below with reference to the drawings.

第1図乃至第5図は本発明の積層板の製造方法を説明す
る説明図であり、図中1は透明ガラス基板又は透明セラ
ミック基板、2.2’は透明酸化インジウム系導電被膜
、3は酸化けい素板膜、4は酸化鉛、酸化亜鉛系の低融
点ガラス層である。
1 to 5 are explanatory diagrams for explaining the method of manufacturing a laminate of the present invention, in which 1 is a transparent glass substrate or a transparent ceramic substrate, 2.2' is a transparent indium oxide-based conductive coating, and 3 is a transparent indium oxide-based conductive coating. The silicon oxide plate film 4 is a low melting point glass layer based on lead oxide and zinc oxide.

実施例 1 ステップl;透明ガラス基板又は透明セラミック基板1
の全面又は部分に透明酸化インジウム系導電被膜2を真
空蒸着法又はスパッタリング法により形成する(第1図
)。
Example 1 Step 1; Transparent glass substrate or transparent ceramic substrate 1
A transparent indium oxide conductive film 2 is formed on the entire surface or a portion thereof by vacuum evaporation or sputtering (FIG. 1).

ステップ2:次に導電被膜2の上面の必要部分に有機シ
リコン化合物、たとえば正けい酸エチルを均一に被着し
これを500℃前後で加熱分解して酸化けい素度膜3を
1oooi以下程度形成する(第2図)。
Step 2: Next, an organic silicon compound, such as ethyl orthosilicate, is uniformly deposited on the required part of the upper surface of the conductive film 2, and this is thermally decomposed at around 500°C to form a silicon oxide film 3 of about 1000 or less. (Figure 2).

ステップ3;引き続いて酸化鉛、酸化亜鉛系の低融点ガ
ラス層4を酸化けい素板膜3上及び除去すべき導電被膜
の適所に形成する。
Step 3: Subsequently, a lead oxide/zinc oxide based low melting point glass layer 4 is formed on the silicon oxide plate film 3 and at appropriate locations on the conductive film to be removed.

この低融点ガラス層4の形成はガラスフリットとエチル
セルローズと有機溶剤とを均一に混合して得られるペー
スト状インクを用いてスクリーン印刷法で形成する(第
3図)。
The low melting point glass layer 4 is formed by a screen printing method using a paste ink obtained by uniformly mixing glass frit, ethyl cellulose, and an organic solvent (FIG. 3).

ステップ4;ついで、低融点ガラス被膜4を400乃至
500℃位で加熱する。
Step 4: Next, the low melting point glass coating 4 is heated to about 400 to 500°C.

これにより導電被膜2に直接接触している部分a(第3
図)に変化が起こり該導電被膜2が低融点ガラス被膜4
に溶けて消滅し、不導体化する。
As a result, the portion a (third
(Fig.) changes and the conductive coating 2 changes to the low melting point glass coating 4.
It dissolves and disappears, becoming a nonconductor.

一方、中間層の酸化ケイ素(Sin2)被膜3が形成さ
れである部4分す、c、d(第3図)の導電被膜には上
記変化が生じず、該導電被膜は不導体化しない(第4囚
これにより必要な回路のパタニング及び導電被膜2の保
護、絶縁が完了する。
On the other hand, the above-mentioned changes do not occur in the conductive film in the portions c and d (Fig. 3) where the silicon oxide (Sin2) film 3 of the intermediate layer is formed, and the conductive film does not become non-conductive ( The fourth step completes the necessary circuit patterning and the protection and insulation of the conductive film 2.

ステップ5;以後同様に透明酸化インジウム系導電被膜
2′を全面あるいは必要な個所に形成しく第5図)、上
記工程を繰返えし必要な層数り透明積層配線基板を作成
するっ 以上実施例1によればパターンの選択性が容易であり、
又各層を確実に積層できるうえ、導体被膜の絶縁、保護
が行なえ、更には比較的安価に透明積層配線基板を提供
できる。
Step 5: Thereafter, the transparent indium oxide-based conductive film 2' is similarly formed on the entire surface or at necessary locations (Fig. 5), and the above steps are repeated to create the required number of layers of the transparent laminated wiring board. According to Example 1, pattern selectivity is easy;
In addition, each layer can be laminated reliably, the conductor film can be insulated and protected, and a transparent laminated wiring board can be provided at a relatively low cost.

実施例 2 ステップ1:有機インジウム系ペーストをスクリーン印
刷法にて基板1上に秘着し500℃前後で加熱分解して
導電被膜2を形成する(第1図)。
Example 2 Step 1: An organic indium paste is deposited on a substrate 1 by screen printing and thermally decomposed at around 500° C. to form a conductive film 2 (FIG. 1).

この方法たよればパターン形成をスパッタリング、蒸着
法による場合に比らべ簡単に行なえることができる。
According to this method, pattern formation can be performed more easily than when using sputtering or vapor deposition methods.

尚、ステップ2以降の工程は実施例1に同じ。Note that the steps after step 2 are the same as in the first embodiment.

実施例 3 実施例1のステップ2における有機シリコン化合物に替
えて、有機チタン化合物を導電被膜2の上面の必要部分
に均一に被着し、加熱分解して酸化チタンTiO2を形
成した。
Example 3 Instead of the organosilicon compound in Step 2 of Example 1, an organotitanium compound was uniformly deposited on the necessary portions of the upper surface of the conductive film 2, and was thermally decomposed to form titanium oxide TiO2.

尚、ステップ1,3゜4.5については実施例1と同一
である。
Note that steps 1, 3 and 4.5 are the same as in the first embodiment.

この実施例3の場合忙は黄褐色に着色され、無色透明な
積層基板を得ることができなかった。
In this Example 3, the substrate was colored yellowish brown, and a colorless and transparent laminated substrate could not be obtained.

実施例 4 実施例1のステップ3においては酸化けい素被膜3及び
除去すべき導電被膜2,2/上に低融点ガラス層4が形
成されるがこの低融点ガラス層4の融点を第1層(54
0°C)、第2層(500℃第3層(480℃)、第4
層(450℃)と上層尾行くほど低く〜して透明積層配
線基板を作成した。
Example 4 In step 3 of Example 1, a low melting point glass layer 4 is formed on the silicon oxide film 3 and the conductive films 2, 2/ to be removed. (54
0°C), 2nd layer (500°C), 3rd layer (480°C), 4th layer
A transparent laminated wiring board was prepared by heating the upper layer (at 450° C.) and lowering the temperature toward the upper layer.

尚、基板1としてソーダガラス基板を用いた。透明配線
基板を多層化するには低融点ガラス4により各層間を絶
縁する必要があるが、該低融点ガラスの融点を各層すべ
て同一にすると、第(i+1)層のパターン作成の際(
ステップ4)該層の導電被膜2/が第1層(i−1,2
・・・・・・)即ち下層の低融点ガラス4の加熱溶融に
より溶けてしまい、良好な透明配線基板を作成すること
ができない場合が生じる。
Note that a soda glass substrate was used as the substrate 1. In order to make a transparent wiring board multi-layered, it is necessary to insulate each layer with low melting point glass 4, but if the melting point of the low melting point glass is made the same for all layers, when creating a pattern for the (i+1)th layer, (
Step 4) The conductive coating 2/ of the layer is applied to the first layer (i-1, 2
(...) That is, the lower layer low melting point glass 4 may be melted by heating and melting, making it impossible to create a good transparent wiring board.

しかし、実施例4によれば上層へ行くほど低融点ガラス
の融点が低いため、ステップ4の加熱温度を上層へ行く
程低く〜できるから第(i+1)層の導電被膜2′が第
1層の低融点ガラスに喰われることはない。
However, according to Example 4, since the melting point of the low-melting glass is lower as it goes to the upper layer, the heating temperature in step 4 can be lowered as it goes to the upper layer. It will not be eaten by low melting point glass.

同、融点差は最低20℃必要であった。Similarly, the melting point difference was required to be at least 20°C.

実施例 5 実施例1のステップ4以降にステップ4′ として次の
工程を加えて透明積層配線基板を作成した。
Example 5 A transparent laminated wiring board was prepared by adding the following process as step 4' to step 4 and subsequent steps of example 1.

ステップ4′;低融点ガラス層4上に有機シリコン化合
物な被着し、これを500’C前後で加熱分解して酸化
けい素被膜3′を100OA以下程度形成する(第6図
)。
Step 4': An organic silicon compound is deposited on the low melting point glass layer 4, and this is thermally decomposed at about 500'C to form a silicon oxide film 3' of about 100 OA or less (FIG. 6).

以後ステップ1〜4′を繰返えして透明積層配線基板を
作成した。
Thereafter, steps 1 to 4' were repeated to produce a transparent laminated wiring board.

。即ち実施例5では中間層の導電被膜2/ を酸化けい
素皮膜3警はさみ込んで透明積層配線基板を作成した。
. That is, in Example 5, a transparent laminated wiring board was prepared by sandwiching an intermediate conductive film 2 and a silicon oxide film 3.

実施例4の場合には低融点ガラスの融点差を順次20℃
以上づつ下げてゆかなくてはならないため積層数に限界
があるが、実施例5の場合には各低融点ガラス4の融点
を同一にできるため積層数の限界はない。
In the case of Example 4, the melting point difference of the low melting point glasses was sequentially increased by 20°C.
There is a limit to the number of laminated layers because the melting point has to be lowered step by step, but in the case of Example 5, there is no limit to the number of laminated layers because the melting points of each low melting point glass 4 can be made the same.

以上、本発明によれば表示素子の実装に好適なしかも信
頼性の高い即ち絶縁性、保護性等が良好で、製造性の良
い透明積層配線基板を提供することができる。
As described above, according to the present invention, it is possible to provide a transparent laminated wiring board that is suitable for mounting display elements, has high reliability, that is, has good insulation properties, protection properties, etc., and has good manufacturability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図、第3図、第4図、第5図及び第6図は
本発明に係る透明積層配線基板の製造方法の各工程を説
明する説明図である。 1・・・・・・透明ガラス基板又は透明セラミック基板
、2.2′ ・・・・・・透明酸化インジウム系導電被
膜、3゜31 ・・・・・・百般イにしtX、X去才古
■宜 A 、、、、、、酸イに左へ 酸イレ石鉛
系の低融点ガラス層。
FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5, and FIG. 6 are explanatory diagrams illustrating each step of the method for manufacturing a transparent laminated wiring board according to the present invention. 1...Transparent glass substrate or transparent ceramic substrate, 2.2'...Transparent indium oxide conductive coating, 3゜31...100% X, X old ■Yi A,,,,,,to the left Acidite lead-based low melting point glass layer.

Claims (1)

【特許請求の範囲】 1 耐熱性透明絶縁基板の上面に全面或いは部分的に酸
化インジウム系透明導電皮膜を形成し、その上面の必要
な部分に有機けい素化合物を熱分解して酸化けい素の皮
膜を被着し、更にその上面の必要部分に低融点ガラス質
を覆い、加熱溶融させて不必要な部分の該導電皮膜を除
去し、しかる後上記工程を繰返えして透明積層配線基板
を製造することを特徴とする透明積層配線基板の製造方
法。 2 透明積層配線基板忙積層する前記各層の低融点ガラ
スの融点を積層順に順次低く〜したことを特徴とする特
許請求の範囲第1項記載の透明積層配線基板の製造方法
。 32層目以降の前記酸化インジウム系透明導電皮膜を酸
化けい素度膜ではさんだことを特徴とする特許請求の範
囲第1項記載の透明積層配線基板の製造方法。
[Claims] 1. An indium oxide-based transparent conductive film is formed entirely or partially on the upper surface of a heat-resistant transparent insulating substrate, and an organosilicon compound is thermally decomposed on the necessary portions of the upper surface to form silicon oxide. A film is applied, a low melting point glass material is further covered on the necessary parts of the upper surface, the conductive film is removed from unnecessary parts by heating and melting, and then the above process is repeated to form a transparent laminated wiring board. A method for manufacturing a transparent laminated wiring board, the method comprising: manufacturing a transparent laminated wiring board. 2. The method of manufacturing a transparent laminated wiring board according to claim 1, wherein the melting point of the low melting point glass of each of the laminated layers is lowered in the order of lamination. 2. The method of manufacturing a transparent laminated wiring board according to claim 1, wherein the indium oxide-based transparent conductive film from the 32nd layer onward is sandwiched between silicon oxide films.
JP16893979A 1979-12-25 1979-12-25 Method for manufacturing transparent laminated wiring board Expired JPS5815959B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16893979A JPS5815959B2 (en) 1979-12-25 1979-12-25 Method for manufacturing transparent laminated wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16893979A JPS5815959B2 (en) 1979-12-25 1979-12-25 Method for manufacturing transparent laminated wiring board

Publications (2)

Publication Number Publication Date
JPS5691491A JPS5691491A (en) 1981-07-24
JPS5815959B2 true JPS5815959B2 (en) 1983-03-28

Family

ID=15877336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16893979A Expired JPS5815959B2 (en) 1979-12-25 1979-12-25 Method for manufacturing transparent laminated wiring board

Country Status (1)

Country Link
JP (1) JPS5815959B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482425A (en) * 1987-09-24 1989-03-28 Nitto Seiko Kk Manufacture of temperature fuse
KR20200127031A (en) * 2018-03-13 2020-11-09 신에츠 폴리머 가부시키가이샤 Substrate storage container
KR20210146803A (en) * 2020-05-26 2021-12-06 에이에스엠 아이피 홀딩 비.브이. Purge nozzle assembly and semiconductor processing assembly including the purge nozzle assembly

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010735A (en) * 1983-06-30 1985-01-19 Toshiba Corp Semiconductor device
JP2597809B2 (en) * 1993-10-12 1997-04-09 株式会社東芝 Method for manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482425A (en) * 1987-09-24 1989-03-28 Nitto Seiko Kk Manufacture of temperature fuse
KR20200127031A (en) * 2018-03-13 2020-11-09 신에츠 폴리머 가부시키가이샤 Substrate storage container
KR20210146803A (en) * 2020-05-26 2021-12-06 에이에스엠 아이피 홀딩 비.브이. Purge nozzle assembly and semiconductor processing assembly including the purge nozzle assembly

Also Published As

Publication number Publication date
JPS5691491A (en) 1981-07-24

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