JPS5816461B2 - weight measuring device - Google Patents

Description

Detailed Description of the Invention This invention provides a reference voltage generator that generates reference voltages of both positive and negative polarities, and uses an A/D converter that can operate with inputs of both positive and negative polarities. Concerning a measuring device.

The present inventor previously provided a weight measuring device of this type having a circuit configuration shown in FIG.

(Special 52-46608) This circuit will be explained below.

1 is a reference voltage power supply, 2 is a load cell, and 3 is a DC amplifier, which are integrated and built into the case in close proximity to each other so that they are always under the same temperature condition.

The reference voltage power supply 1 includes a DC power supply 101 and an operational amplifier 1.
The positive terminal of the power supply 101 is connected to the non-inverting input terminal (+) of the operational amplifier 102, and the negative terminal of the power supply 101 is connected to the operational amplifier 10.
It is connected to the non-inverting input terminal (+) of No. 3.

A resistor 104 is connected between the inverting input terminal (-) of the operational amplifier 102 and the output terminal of the amplifier 102, and a resistor 105 is connected between the inverting input terminal (-) of the operational amplifier 102 and ground. .

Further, a resistor 106 is connected between the output terminal of the operational amplifier 102 and the inverting input terminal (-) of the operational amplifier 103, and the inverting input terminal (-) of the operational amplifier 103 is
A resistor 107 is connected between the output terminal 7 of the amplifier 103 and the output terminal 7 of the amplifier 103.

Although the DC power supply 101 of the reference 1-voltage power supply 1 is not grounded, a reference voltage is obtained by the circuitry of the operational amplifiers 102 and 103.

the operational amplifier 103; There is a resistance of 1 between the power terminal and the ground.
A series circuit of 08 and 109 is connected.

Further, a resistor 901 forming a bias circuit 9 and a potentiometer 9 are connected between the output terminal of the operational amplifier 103 and the ground.
02 and a resistor 903 are connected in series.

The load cell 2 has a resistor 201 attached to the load receiving part,
It consists of a bridge circuit with 202203.204 as the four sides, resistor 201.203 and resistor 202゜204.
are provided facing each other.

Each of these resistors 201 to 204 has a resistance value that changes depending on the distortion of the load receiving portion.
The resistor 203 changes in a decreasing direction, and the resistor 202204 changes in an increasing direction.

Further, the P-cell 2 further has a resistor 205 connected in series with the resistor 201 on the side where the resistor 201 is located, for adjusting the output voltage E to a specified value when the load cell 2 is under no load. Further, a resistor 206 is interposed in series with the resistor 204 on the side where the resistor 204 is interposed to make the temperature coefficient of the strain resistor zero.

The connection point between the side where the resistor 201 is located and the side where the resistor 204 is located is connected to the positive terminal of the DC power supply 101 via the sensitivity temperature coefficient adjusting resistor 207. The connection point between the side and the side where the resistor 204 is interposed is connected to the negative terminal of the DC power supply 101.

The sensitivity temperature coefficient adjusting resistor 207 is for correcting the temperature coefficient of Young's modulus of the load receiving member.

The load cell output Bi is connected between the connection point a between the side where the resistor 204 and the resistor 203 are located, and the connection point A between the side where the resistor 201 and the resistor 202 are located. I am trying to output .

Note that the connection point is grounded.

The DC amplifier 3 is connected between the connection points a and b via a resistor 5, and a low-pass filter 6 is connected in parallel between the load cell 2 and the amplifier 3.

The low-frequency Z filter 6 is used to cut the AC component superimposed on the load cell output.

The DC amplifier 3 includes an operational amplifier 301 and first to fourth four
analog switches 302.303.304.305
A connection point a of the load cell 2 is connected to a non-inverting input terminal (+) of an operational amplifier 301 via a resistor 5 and a first analog switch 302 in series.

A series circuit of a second analog switch 303 and a resistor 310 is connected between the non-inverting input terminal (+) of the amplifier 301 and ground.

A resistor 30 is connected between the output terminal of the operational amplifier 301 and ground.
6.307 series circuits are connected and further capacitor 3
The third analog switch 304 is connected through a resistor 309 and a resistor 309 in series.

The connection point with the resistors 306 and 307 is connected to the inverting input terminal (-) of the operational amplifier 301.

The DC amplifier 3 outputs the output of its operational amplifier 301 through a capacitor 308, a resistor 309, and a fourth analog switch 305 in series.

Then, the movable terminal of the potentiometer 902 of the bias circuit 9 is connected to the second analog switch 303 and the resistor 3.
It is connected to the connection point with 10.

The output of the DC amplifier 3 is input to an A/D converter 7.

The A/D converter 7 includes four fifth to eighth analog switches 701, 702, 703, 704 and a capacitor 70.
5, an integrator 708 including an operational amplifier 707, a buffer amplifier 709, a comparator 710, a ninth analog switch 111, a flip-flop 712, and a counter 713.

The reference voltage generator 706 includes four analog switches 7
01 to 704 form a bridge circuit, and the switch 701
A capacitor 705 is connected between the connection point between the switches 703 and 702 and the connection point between the switches 703 and 704, and the output of the DC amplifier 3 is connected to the buffer amplifier 7 via the capacitor 705.
The signal is supplied to the non-inverting input terminal (+) of 09.

The connection point between the analog switches 701 and 704 is connected to the connection point between the resistors 108 and 109 of the reference voltage power source 1, and the connection point between the analog switches 702 and 703 is grounded.

The output terminal and the inverting input terminal (
-) is shorted.

The output terminal of the buffer amplifier 709 is connected to the inverting input terminal (-) of the operational amplifier 707 via a resistor 71-.

A capacitor 715 is connected between the non-inverting input terminal (+) of the operational amplifier 707 and ground, and the inverting input terminal (
-) and the output terminal, a capacitor 716 is connected.

The output terminal of the operational amplifier 707 is connected to the comparator 7.
It is connected to the inverting input terminal (-) of No. 10.

A DC power supply 717 is connected between the non-inverting input terminal (+) of the comparator 710 and the ground, with the ground side being the positive terminal.

The output terminal of the comparator 710 and the operational amplifier 7
The ninth analog switch 711 is connected between the non-inverting input terminal (+) of 07.

A control circuit 713 operates according to the output of the comparator 710.

Also, 8 is a switch controller, and this controller 8
is driven by the control circuit 713 and each of the analog switches 302, 303, 304°305.701.7
02, 703, 704, and 711 are opened and closed.

Specifically, at time t1, the control circuit 713 instructs the controller 8 to close only the second, fourth, sixth, seventh, and ninth analog switches 303, 305, 702, 703, and 711.

The control circuit 713 then controls its state so that its own clock pulse counter 712 continues for a period T1 in which it counts a predetermined number of clock pulses.

At time t2 when this period T1 ends, the control circuit 71
3 in turn instructs the controller 8 to close only the first and third analog switches 302f304.

Then, the control circuit 713 controls this state so that its own clock pulse counter 712 continues for a period T2 in which it counts a predetermined number of clock pulses.

Also, immediately before the end of period T2, this control circuit 713 determines whether the polarity of the input voltage to the buffer amplifier 709 is positive or negative based on the output of the near y ha v-t 710, and as a result, is transmitted to the controller 8.

The controller 8 switches the fifth analog switch 70 when the polarity of the input voltage is positive at the end of the period T2.
1 is closed, and when it is negative, the eighth analog switch 704 is closed.

Of course, all other analog switches are open at this time.

At time t3 when this period T2 ends, the control circuit 71
3 causes its own clock pulse counter 712 to count clock pulses again.

This counting operation is now stopped when the output of the comparator 710 becomes zero.

This stop time is designated as t4, and the count counted by the clock pulse counter 712 during the period T3 provides digital weight measurement information.

The operation of a device having such a circuit configuration is as follows.

That is, now the voltage of the DC power supply 101 is El, and the resistor 20 is
The resistance values of 1.202 and 203.204 are R11, respectively.
RZ is the resistance value of R125R3, R4, and resistors 205, 206, and 207, respectively.

The output Ei of the load cell 2, which is RZTIR8, is based on the relationship shown in FIG.

For example, if R, 1=R2=R, 3=R4=R and the resistance change when a load is applied to the load cell 2 is δ, the above equation (g) becomes as follows.

Since δ is the output proportional to the load, the rated load of the load cell 2 is F.

, if the applied load is F and the sensitivity of load cell 2 is K, then δ=
Upper K 1. Engineering.

(3) E1'・.

The output Ei of the load cell 2 is input to the DC amplifier 3 after the superimposed AC component is cut by the low-pass filter 6.

Now, at time t1, the analog switches 303, 305, 702° 703.71 are activated by the switch controller 8.
1 is closed, the operational amplifier 3017 in the DC amplifier 3
The difference voltage between the offset voltage V301 of 5000 and the voltage v9 set by the bias circuit 9 is amplified according to the gain A, = (1 + □, IIL) determined by the resistors 306 and 307, and the voltage AI (V2O3V9) is k output f le.

Ko (7)! Voltage A1 (V2O3Vg) is capacitor 3
08, a resistor 309, and a fourth analog switch 305, the capacitor 308 is charged.

On the other hand, the output of the operational amplifier 103 of the reference voltage power supply 1 is R
, RA2=--□, R106R104 (1+A2) (E, +V103 V2O3).

Therefore, the reference voltage = Vr supplied from the reference voltage power supply 1 to the reference voltage generator 706 of the A/D converter 1 is 109 -Vr = (1 + A2) (E1 + V1 o3 - V, o2)
□R108+也09 ・・・・・・・・・(6) It becomes.

Therefore, at time t1, the analog guide 702
, 703 is closed, the capacitor 705 is charged with −Vr with the illustrated polarity through the path of the analog switch 702, the capacitor 05, and the analog switch 703.

Furthermore, at time t1, analog switch 711 is closed.

Therefore, from the output terminal of comparator 710 to integrator 708
Since a negative feedback loop is formed to the non-inverting input terminal (+) of the operational amplifier 707 and acts to always make the differential input voltage to the operational amplifier 707 zero, the integrator 708 stops integrating. There is.

,' and this state continues for a period T1 from time t1 to time t2.

At time t2, analog switch 303°305.7
02, 703, and 711 are opened, and in turn, the first and third analog switches 302, 304 are closed.

Then, the output Ei of the load cell 2 is now amplified by the DC amplifier 3, and the output of the operational amplifier 301 is A1.
(Ei+■3o1).

By the way, during the period T1, the voltage A is applied to the capacitor 308.
1.vsot is charged and it is connected to analog switch 3.
05 is opened, the output of the DC amplifier 3, that is, the output of the third analog switch 304, is A1・(-Ei+V3o,) At (V2O3V9)
==-A, (Ei-V, ).

This indicates that the offset voltage 3o1 of the operational amplifier 301 has been removed.

Further, it is shown that the output of the third analog switch 304 can be arbitrarily set to both positive and negative polarities by setting the bias circuit 9.

The output of this analog switch 304 is the input of the A/D converter γ, and this value changes between positive and negative depending on the load applied to the load cell 2.

This signal voltage -A1 (Bi-Vg') is then input to the A/D converter 7.

Now, the capacitor 705 of the reference voltage generator 706 has one
Since the voltage of , is held, -A1 (Ei-V9) is combined into -Ei.

Considering this, a voltage of (f-Vr)+(-Bio) is input to the non-inverting input terminal (±) of the buffer amplifier 709.

This voltage is then integrated by an integrator 708 via a buffer amplifier 709.

By the way, the capacitor 715 of the A/D converter 7 has a period T.
Due to the formation of a negative feedback loop in 1, (−
vr +V707) has already been charged.

On the other hand, during period T2, the operational amplifier 7 of the integrator 708
The inverting input terminal (-) of 07 has (Vr) + (-E
io) The voltage of +V707 is input.

Therefore, the output of the operational intensifier 707 is ■. is V□=[((-Eio)+(Vr)+V7o7)-((
-Vr)+V707))XAo=-Eio-A.

・・・・・・・・・(7) (However, A.

is the closed loop gain of operational amplifier 707.

).

That is, a voltage corresponding to the output of the load cell 2 is output.

The integration by this integrator 708 is T from time t2 to t3.
It will be held over two periods.

Then, just before time t3, the comparator 710
The control circuit 71 determines whether the polarity of the input voltage to the buffer amplifier 709 is positive or negative depending on the output of the control circuit 71.
Detected by 3.

That is, it is detected whether the polarity of the level integrated by the integrator 708 is positive or negative.

For example, when the control circuit 713 detects that the output of the integrator 708 is negative based on the output of the comparator 710, the controller 8 outputs the first signal at time t3.
, commands the third analog switch 302, 304 to open and the eighth analog switch 704 to close.

This is the buffer amplifier 7 as shown in Figure 3.
This indicates that the output voltage to 09 will be O volts.

On the other hand, the control circuit 713 uses the clock pulse counter 712
When the time t3 arrives, the clock pulse count is started.

When the input voltage to the buffer amplifier 709 reaches O volts, the voltage integrated by the integrator 708 is gradually discharged.
Eventually, at time t4, the voltage level becomes zero, and the output level of the comparator 710 becomes zero.

When the output level of the comparator 710 becomes zero, the control circuit 713 stops the clock pulse counting operation by its own clock pulse counter 712.

Therefore, the clock pulse counter 712 counts from time j3 to
Clock pulses are counted during the T3 period up to t4.

By the way, the period T3 is proportional to the voltage level integrated by the integrator 708, and the voltage integrated by the integrator 708 is proportional to the output of the load cell 2, so the clock pulse counter 712 ultimately counts the voltage level over the period T3. The counted number of clock pulses digitally represents the amount of load measured by the load cell 2.

For example, when the control circuit 713 detects that the output of the integrator 708 is positive based on the output of the comparator 710, it causes the controller 8 to open the first and third analog switches 302 and 304 at time t3. and commands to close the fifth analog switch 701.

This is the buffer amplifier 7 as shown in Figure 4.
09 is (-Vr) + (-Vr) volts.

In this case as well, the control circuit 713 operates at time t.
3, start counting clock pulses.

Input voltage -2V to buffer amplifier 709 and integrator 1
Since the polarity of the integrated output of 08 is reversed, the voltage integrated in the integrator 708 is gradually discharged by the input voltage -2■, and eventually the voltage level becomes zero at time t4, and the output of the comparator 710 The level becomes zero.

In this case as well, the counter 712 counts clock pulses during the T3 period from time t3 to t4, and the load cell 2
The amount of load measured by is digitally represented.

The relationship between time and integrator output when the input voltage from the load cell 2 to the A/D converter 7 is negative and positive is as shown in a and b in FIG. 5.

Output ■ of integrator 708 during period T2.

1 if the charging voltage of the capacitor 716 at time t2 is zero.

Also, the output V of the integrator 708 during the period T3.

2 becomes.

′″jTEi・=”PiBi・Ei=−P−,,°ゝ°0
When 1o3-v1o2 can be ignored with respect to the voltage per one count of the counter 712, then .

By the way, as mentioned above, the A/D used in this device
Since the converter 7 operates with respect to both positive and negative input voltages, for example, when a load of exactly 1/2 of the maximum load Wn, that is, Wn/2, is applied to the load cell 2, A/
Potentiometer 902 of bias circuit 9 is adjusted so that the input voltage level to D converter γ is exactly zero.

This can be expressed graphically as shown in FIG.

In other words, when the load on load cell 2 is zero, A/-
When the input to the D converter 7 is R2 and the load on the load cell 2 is Wn /2, the input to the A/D converter 7 is zero, and when the load on the load cell 2 is the maximum Wn, the A/D converter Bias circuit 9 is adjusted so that the input to 7 becomes R3.

Note that the compensation range for the initial load of the load cell 2 is P1 to P2 when expressed by the input level to the A/D converter 7.
is set to .

By doing this, the A/D converter 7 has P1 to P3.
It can be operated for inputs in the range of , that is, in the positive to negative polar range.

For example, when the A/D converter 7 is operated in unipolar mode, W
The input voltage to the A/D converter 7 is 0 to P for a load of n.
Since the load cell 2 is limited to a range of 2,0 to P3, there is a problem in that a highly sensitive one with a large output relative to the load cannot be used as the load cell 2.

In this respect, this device uses an A/D converter 7 that can operate in the range from positive to negative, that is, in the range P1 to P3, and uses a bias circuit 9 to convert the A/D converter 7 into a load cell. 2, a highly sensitive one can be used as the load cell 2, and highly accurate weight measurement can be achieved.

In this device, a series circuit of resistors 108 and 109 is connected between the output terminal of the operational amplifier 103 and the ground, and a reference voltage generator 706 is connected in parallel to the resistor 109.

Therefore, the maximum value of the reference voltage level of reference voltage generator 706 is fixed.

That is, there is a problem that the sensitivity (output/input) of the A/D converter 7 is fixed and cannot be adjusted.

Therefore, for example, as shown in FIG.
A potentiometer 110 is inserted in series between the reference voltage generator 1 and the movable terminal of the potentiometer 110.
It is conceivable that the sensitivity of the A/D converter 7 can be adjusted by connecting it to the connection point of the analog switches 701 and 702 of 06.

However, simply doing so poses the following problems.

Point Q (shown in FIG. 6) is the operating point of the A/D converter 7.

) is represented by the count number Nr(Q).

Here, EL (Z) is the load cell output due to the initial load, EL
(B) is the load cell output due to zero balance, N5 is A
Counter 71 during signal integration period T3 of /D converter 7
2 count number, Rw is Rw, /Rw, + Rw2
+RT is R12/Rr 1 +Rr 2 +A2・E
l·Rw is a voltage applied to set the Q point of the A/D converter 7.

Since the sensitivity of the A/D converter 7 is adjusted by changing R4, that is, by changing the potentiometer 110, the relative change rate of Nr(Q) is as follows.

However, in the case of a circuit configuration in which the numerator of equation (13) is very large as in this circuit, when Rr is changed to adjust the sensitivity of the A/D converter 7, Nr(Q) changes greatly. There are drawbacks.

In other words, this means that even if Q is once set to a predetermined value in FIG.
) may deviate by a large width, making it extremely difficult to adjust the sensitivity of the A/D converter 7.

This invention was made in view of the points mentioned above.
To provide a weight measuring device capable of adjusting the sensitivity of an A/D converter while keeping the count number at an operating point of the A/D converter substantially constant, and also capable of accurately measuring weight. The purpose is to

Embodiments of the present invention will be described below with reference to the drawings.

Note that the same parts as those of the circuits explained in FIGS. 1 to 7 are given the same reference numerals and detailed explanations will be omitted.

As shown in FIG.
0, one end of the bias circuit 9 is separated from the output terminal of the operational amplifier 103, and a high impedance circuit 11 comprising an operational amplifier 111 is connected between the movable terminal of the potentiometer 110 and one end of the bias circuit 9.
are inserted into each.

That is, the high impedance circuit 11 connects the non-inverting input terminal (+) of the operational amplifier 111 to the movable terminal of the potentiometer 110, and connects the inverting input terminal (-) of the operational amplifier 111 to the output terminal of the amplifier 111. The output terminal of the operational amplifier 111 is connected to one end of the bias circuit 9.

With such a configuration, the voltage supplied to the bias circuit 9 is provided from the sensitivity adjustment circuit 10 to the A/D converter 7 via the operational amplifier 111, so the sensitivity adjustment circuit 1
Even if the sensitivity of the A/D converter 7 is adjusted at 0, that is, the slope of the graph shown in FIG. can be retained.

In other words, in the device of this embodiment, the count number Nr of point Q
(Q) becomes.

However, Aj is the gain of the operational amplifier 111.

In the above equation (15), the first term, that is, At (E
L (Z) ± EL (B)) This is the part related to the voltage that is given to set at the point, and is the first term (second term).

The second term does not include Rr.

Therefore, the potentiometer 10 of the sensitivity adjustment circuit 10
Even if Rr is varied by manipulating , the second term does not change and remains constant.

On the other hand, focusing on the first term, BL(B) is the output of the load cell 2 due to zero balance, which can be adjusted by the resistance 205 of the load cell 2.

Therefore, by adjusting the resistor 205 appropriately, BL(Z)±
EL(B)≠0 can be satisfied.

When EL(B) is set in this way, the numerator of the first term becomes approximately zero, and even if Rr is varied, the first term hardly changes as a result.

Note that setting E L (Z) ± EL (B) #O is to adjust the load cell output to zero in a state where the initial load of a plate or the like is applied to the load cell 2.

By adjusting the sensitivity adjustment circuit 10 in this way, A
Even if the sensitivity of the /D converter 7 is changed, the
The count number Nr(Q) of the operating point Q of the D converter 7 does not change significantly.

In other words, the count number Nr(Q) at point Q is calculated by the A/D converter 7.
Even if the sensitivity of the holder is changed, the retainer can be kept substantially constant.

It should be noted that high accuracy in weight measurement can be obtained, similar to the circuit shown in FIG.

In the above embodiments, an operational amplifier is used as the high impedance circuit, but this is not necessarily the case. good.

[Brief explanation of drawings]

Figures 1 to 6 show examples of prior applications. Figure 1 is a circuit configuration diagram, Figure 2 is an equivalent circuit diagram of a load cell, and Figure 3 is an integrator input section when the input voltage is negative. Equivalent circuit diagram. Figure 4 is an equivalent circuit diagram of the integrator input section when the input voltage is positive. Figure 5 is an equivalent circuit diagram of the integrator input section when the input voltage is positive.
The figures are graphs showing the operating characteristics of an integrator, a is a graph when the input voltage is negative, b is a graph when the input voltage is positive, Fig. 6 is a graph showing the operating characteristics of an AZD converter, and Fig. 7 is a graph showing the operating characteristics of an AZD converter. Part 8 is a partial circuit diagram for explaining the problems of the prior application.
The figure is a circuit configuration diagram showing an embodiment of the present invention. 1... Reference voltage power supply, 2... Curved load cell,
3゛°. ...DC amplifier, 7...-A/D converter, 70
6...Reference voltage generator, 9...Bias circuit, 10...Sensitivity adjustment circuit, 11...
・・High impedance circuit, 110.902・・・・
- Potentiometer.

Claims (1)

[Claims] 1. A load cell that outputs a voltage signal according to a load, a reference voltage power source, a reference voltage generator connected to this power source, and an intervening device between the reference voltage generator and the power source. The input section includes the inserted sensitivity adjustment circuit and the reference voltage generator,
Double integral type A/ that can operate with inputs of both positive and negative polarity.
a D converter, a high impedance circuit, a bias circuit connected to the power source via the sensitivity adjustment circuit and the high impedance circuit, an input section connected to the bias circuit and the load cell, and the A/D converter. The input section is connected to the output section, and the input section is equipped with an operational amplifier, the output section is equipped with a capacitor, and a DC amplifier is provided with a plurality of switch elements for input/output control at the output section. , the DC amplifier is first inputted with the bias circuit output by selectively operating each switch element, then manually energizes the operational amplifier to charge the capacitor, and then inputted with the load cell output. The operational amplifier is energized to charge the capacitor, thereby obtaining a superimposed output of the load cell output and the bias circuit output, and supplying the output to the A/D converter, and the bias circuit is connected to the load cell. A weight measuring device characterized in that an output level is set so that the output level of the DC amplifier input to the A/D converter becomes exactly zero when a load of approximately half of the maximum effective weighing load is applied. 2. The weight measuring device according to claim 1, wherein the high impedance circuit is constituted by an operational amplifier.