JPS5816474B2 - Trigger signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in trigger circuits used in various waveform observation devices such as oscilloscopes and spectrum analyzers.

In such waveform observation devices, when sweeping and brightness modulating the observed waveform, the generation of sweep signals, brightness modulation signals, etc. is controlled based on the trigger input signal, and the level of the trigger input signal and the brightness modulation signal are controlled. A trigger signal generation circuit is required that generates a trigger signal by detecting a crossing with a preset trigger level.

Figure 1 is a circuit diagram of a conventional trigger signal generation circuit.In recent years, waveform observation devices have been required to be particularly compact and lightweight, as well as low power consumption. This figure shows an example configured using an integrated circuit.

In the figure, a trigger input signal applied to an input IN is passed through a transistor Q1 and a resistor R2 to a transistor Q2. Q3 is applied to a comparator circuit using a differential amplifier A, where it is detected that the trigger level and the level of the trigger input signal intersect.

The output of the differential amplifier A is taken out as a change in the collector voltage of the transistor Q3 due to the collector resistor R6 of the transistor Q3, and is output to the NAND gate G1 . It is applied to the input of G2, becomes a trigger signal through a NAND gate, and is sent to the output OT.

However, the polarity of the trigger input signal waveform when detecting the crossing with the trigger level is selected by the switch S, and when the switch S is on the (+) side, one input of the NAND gate G2 is grounded and the low level ( Below, -L
//) Therefore, the output of the gate G2 is fixed at 1L" regardless of the input of the other gate.

On the other hand, when transistor Q3 is turned off, its collector voltage is equal to the voltage of +E3, which causes NA
One input of the ND gate G1 is at a high level (hereinafter referred to as 'H'').
), and since the other input is also set to 1H" through the switch S, the output is 'L', and the output changes in response to changes in the collector voltage of the transistor Q3.

Therefore, at this time, the NAND gate G2 is not involved in sending out the trigger signal.

Note that each gate 01 to G4 has a waveform shaping function that sends out a constant level output when the input level changes beyond a predetermined threshold level, and also has an amplification function at the point of change as described later. have.

Now, when the level of the trigger input signal crosses the trigger level, the transistor Q3 turns on and its collector voltage decreases, so the input of the NAND gate G1 becomes "L", and when its output changes to "1H", the NAND gate data The output changes from t%H" to "L", and this level change is sent out as a trigger signal.

In order to accelerate the output change during the transition period of the level change and to make the rise and fall of the level change steep, the NAND gate G1 is provided with a positive feedback circuit consisting of resistors R6t and R8, and the transistor Qs-NAN
The loop gain of D gate G1 and resistor R6 is set to 1 or more, and as shown in Fig. 2, it is assumed that the trigger signal voltage with respect to the change in trigger input signal voltage VIN jumps vertically depending on the change in oT. , trigger signal voltage ■o
Trigger input signal voltage VIN at the rise and fall of T
The values of are different and exhibit hysteresis characteristics, but
This is to set a dead zone in which the generation of the trigger signal does not respond to the noise component superimposed on the trigger input signal, and this result is obtained based on the input and output characteristics of the NAND gate data, as will be described later.

In addition, if the switch S is on the (-) side, the output of the NAND gate is fixed at 1H, and the NAND gate is fixed at 1H.
ND gate G2 is resistor R7? R8 performs positive feedback and operates in the same manner as described above, but at this time NAND
Since gate G3 is inserted, the output polarity is reversed and NA
A trigger signal is sent out using a trigger input signal waveform with a polarity opposite to that during operation of the ND gate G1.

The circuit shown in FIG. 1 operates as described above and is generally used as a trigger signal generation circuit for various waveform observation devices. Due to the characteristics of G2, the response characteristics deteriorate for high-frequency trigger input signals, and the difference between the trigger input signal voltages v1 and 2 at the rising start point U and the falling start point of the hysteresis characteristics shown in Figure 2. Since the width of the dead area changes due to the difference in sensitivity, this is extremely inconvenient for the purpose of setting (trigger sensitivity) - (noise margin).

Therefore, due to this restriction, the circuit shown in FIG. 1 is unsuitable for high-end equipment that handles up to high frequency bands, and has the disadvantage that it can only be applied to low-end equipment that handles up to relatively low frequencies.

This is because the input impedance of the NAND gate, G2, etc. decreases at high frequencies, and the loop gain of the positive feedback circuit decreases.
Examples include circuit configurations such as gate data tG2.

That is, in general, an AND integrated circuit such as a NAND gate device G2 is configured as shown in the circuit diagram shown in Figure 3, where the first stage multi-emitter transistor Qll has a common base, and the Hisai transistor Q1 has an emitter common. In Fig. 4, the emitter voltage of the transistor Q1□ is set as the input voltage ■1, and the output stage transistor Ql3
Connection point between both at t Ql 4; output voltage v
As shown in the input/output characteristics shown as o, the threshold voltage at which the output voltage changes is determined, and near this threshold voltage, the transistor Qll is in a state of saturation.
Transistor Q12 operates in a high gain amplification state.

: Therefore, if the gain of the transistor Q12 is G, the collector-base capacitance COB of the transistor QI2 becomes G-CoB due to the Miller effect and appears between the base and emitter, and this is directly inputted via the transistor Q1□. It becomes an internal capacitance in the emitter of , lowering the input impedance in the high frequency range.

This decrease in input impedance causes a decrease in the load impedance of transistor Q3 in differential amplifier A, which lowers the frequency response characteristic of voltage amplification in the high frequency range, making it impossible to maintain the loop gain of the positive feedback circuit at 1 or more. become.

As a countermeasure, it is possible to extend the frequency response characteristic to a high frequency range by setting the collector resistor R3 of the transistor Q3 to a low resistance value, but in this case, the collector current of the transistor Q3 must be increased, and it is necessary to reduce power consumption. Furthermore, even with this, it is extremely difficult to maintain the voltage amplification degree at a predetermined value.

Note that the broken line in FIG. 4 represents the loop gain of the positive feedback circuit, and the input voltage 1. ■2 is determined,
This pixel corresponds to both points U and D in Figure 2, and the width between them can be set by the value of the loop gain, but due to the decrease in the loop gain mentioned above, the slope of the dashed line in the figure approaches the horizontal direction. As the contacts U and D shift accordingly, the corresponding points U and D in Fig. 3 also shift in the horizontal direction, and the trigger input signal of the trigger signal changes according to the frequency of the trigger input signal. The dead area for voltage changes.

In this way, the one in FIG. 1 has a change in operating characteristics in the high frequency range, and in order to eliminate this, the NAND gate G1.
It is necessary to take measures such as using an integrated circuit with good high frequency characteristics for G2 etc. or adding an amplifier, but these all lead to a complicated circuit configuration, an increase in the cost of the parts used, and power consumption. This resulted in an increase in

The present invention has been made to solve the five drawbacks of the conventional technology at once.
As mentioned above, a simple impedance conversion circuit of about 16 transistors is inserted between the differential amplifier and the AND circuit, thereby ensuring good operation over a high frequency range and increasing power consumption and the number of parts. The present invention provides a trigger signal generation circuit that has only a small amount of noise and does not hinder miniaturization, weight reduction, and cost reduction.

Hereinafter, the present invention will be explained in detail with reference to FIG. 6 showing an actual case.

This figure shows an impedance conversion circuit inserted into the one shown in FIG. 1, and is the same as that shown in FIG. 1 except that a transistor Q4 and a resistor R0 are added.

That is, the transistor Q4 operates as an impedance conversion circuit using an emitter follower circuit using the resistor R0, and its base input is connected to the collector of the transistor Q3, which is the output of the differential amplifier iA, and the emitter output is connected to the collector of the transistor Q3, which is the output of the differential amplifier iA. NAND gates G1 and G
Connect to the second input.

Therefore, the transistor Q4 exhibits high input impedance and low output impedance due to the series negative feedback of the resistor R9, and the collector load of the transistor Q3 is determined by the resistor R5. can be easily obtained.

Also, NAND gate day. Since G2 is driven by a low impedance, the effect of lowering the input impedance due to the internal capacitance of this portion is prevented, and a good broadband amplification effect is performed in the NAND gate G2.

Therefore, the loop gain of the positive feedback circuit is 1 up to the high frequency range.
The above desired values are maintained, and overall good operation is performed for trigger input signals over a high frequency band.

Incidentally, the increase in current caused by the transistor Q4 is only slight, and is almost negligible compared to the increase in current when the resistor R6 described above has a low resistance value.

Also, the number of components increases by two, including transistor Q4 and resistor R0.
This does not pose any particular problem in reducing size, weight, and cost.

In addition, as an impedance conversion circuit, a source follower circuit in which a resistor is inserted into the source of a field effect transistor may be used. In this case, a higher input impedance is maintained, so the voltage amplification degree of transistor Q3 is increased and It is easy to widen the frequency characteristics, and the jump characteristics shown in FIG. 2 can be made more stable.

As is clear from the above explanation, according to the present invention, the frequency response characteristics of the conventional trigger signal generation circuit are improved by adding only a few components, the rise and fall characteristics of the trigger signal are improved, and the present invention can be applied to high-end devices. Despite the fact that the space required, power consumption, and price increase are almost negligible, it can be used in various waveform observation devices to improve the performance of medium and low-grade instruments and reduce the price of high-end instruments. was realized,
You can get a lot of benefits.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional trigger signal generation circuit, Figure 2 is a circuit diagram showing a conventional trigger signal generation circuit.
The figure is a diagram showing the relationship between the trigger input signal voltage and the trigger signal voltage, and FIG. 3 is a circuit diagram showing a configuration example of an AND integrated circuit.
FIG. 4 is an output voltage characteristic diagram of the circuit shown in FIG. 3, and FIG. 5 is a circuit diagram showing an embodiment of the present invention. IN...Input, RV...Potentiometer, Q1~Q,...Transistor, A...
...Differential amplifier, 01-G4...NAND gate (AND circuit), R1-R0...Resistor,
OT...Output.

Claims (1)

[Claims] 1. A trigger circuit of a waveform observation device includes a differential amplifier that sets a trigger level and detects an intersection between the trigger level and the level of a trigger input signal, and a differential amplifier that amplifies the output of the differential amplifier. and an AND circuit that positively feeds a part of the amplified output to the differential amplifier, and a high input by a transistor whose input is connected to the output of the differential amplifier and whose output is connected to the input of the AND circuit. A trigger signal generation circuit characterized by inserting an impedance and low output impedance conversion circuit. 2. The trigger signal generation circuit according to claim 1, wherein an emitter follower circuit using a transistor is used as the impedance conversion circuit. 3. The trigger signal generation circuit according to claim 1, wherein a source follower circuit using a field effect transistor is used as the impedance conversion circuit.