JPS5816481B2 - computer system power supply - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply device for supplying power to a computer system, and more particularly to a power supply device for a multi-computer system consisting of a plurality of computers each having a storage device such as a core memory.

In a multi-computer system, functions can be distributed among multiple computers, thereby improving the reliability of the entire system.

To supply power to such a system, it is common to provide a power supply for each computer or several computers in order to maintain the reliability benefits of functional distribution. Even if one power supply goes down, computers with other power supply units can continue operating.

In order to prevent the multi-computer system from stopping partially due to a power supply abnormality and to further improve reliability, it is necessary to multiplex the power supplies. Problems arise both economically and in terms of the space taken up by the power supply.

Therefore, a configuration as shown in FIG. 1 has been proposed in an attempt to obtain sufficient effects with as low redundancy as possible.

This includes n computers 20-1.・・・・・・・・・
....

20-n are common power supply devices 10-1.・・・・・・
...-210-n to output diodes 16-1, 16
-n, and is further provided with a standby power supply 15 having an output voltage slightly lower than the output voltage of these regular power supplies, and output diodes 16-1 . . . . , a diode 17-1 .・・・・・・・・・
.

17-n.

If any of the regular power supplies causes an internal fault and the output voltage drops, the standby power supply 15 will supply power in its place.

According to such a configuration, by providing only one backup power supply device, it is possible to continue supplying power to the computer without momentary interruption even in the event of an internal failure in any of the regular power supply devices.

However, if one regular power supply unit is undergoing maintenance and another regular power supply unit has an internal accident, or if multiple units have an internal accident at the same time, the standby power supply unit 15 will be overloaded, resulting in a voltage drop or There is a risk of failure of the backup power supply unit due to overheating.

Generally speaking, storage devices used in computers are of a destructive read type, such as core memory, which maintains the stored contents by writing them again after reading them. If the power supply drops below the operable voltage during operation, the stored contents will be destroyed.

Therefore, in the configuration as shown in FIG. 1, there is a risk that the memory of the storage device may be destroyed if an accident occurs in a plurality of regular power supply devices as described above.

In other words, in the configuration as shown in FIG.
5 needs to have a current capacity equivalent to a plurality of regular power supply devices.

In addition, in order to ensure that current is supplied from the regular power supply during normal operation, it is necessary to set the voltage by taking into account variations in the bias voltage of the diode, which, combined with the above-mentioned current capacity, poses an industrial disadvantage in standardizing power supplies. many.

The present invention was made in view of the shortcomings of the prior art, and an object of the present invention is to provide a power supply device that has low redundancy, sufficiently increases reliability against computer memory corruption, and facilitates standardization of the device. shall be.

The characteristic configuration of the present invention is to provide an extra power supply device of the same capacity, with no distinction between regular and standby power supplies, to the number n units capable of covering the entire load, and connect all of these outputs to the power bus to power each computer. In addition to receiving power from the power supply bus, each power supply device is equipped with a circuit that detects the establishment of power supply, and the operation of the storage device of each computer is permitted when the power supply of n power supply devices is established. It is.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows the overall configuration of an embodiment of the present invention.
n+1.) power supply devices 10-1.・・・・・・・・・
.

1O-(n+1), n computers 20-1.
.....Power is supplied to 20-n.

Each power supply device has the same capacity and the same configuration, and has a current capacity that allows n units to supply power to all n computers.

Each power supply device has a power switch 11-1゜...
・, 11-(n+1) converts the AC input obtained through An individual power supply is established on the condition that AC input is input to the AC/DC conversion circuit 12 that converts to a constant DC voltage, and that the output DC voltage VDC is equal to or higher than the operating voltage of the computer's core memory. It consists of a level detector 13 that turns on the signal PAVL, and an output diode 14 that connects the DC output to the power supply bus 18.

A specific example of the level detection circuit 13 is shown in FIG. 3, and its operation is shown in FIG.

First, when the AC power is turned on by the power switch at tl, the relay 134 operates and its normally open contact 136 closes.

The DC voltage JVDC gradually increases, and when its value reaches the operating voltage VCR of the core memory or higher, the relay 135 operates, and the individual power supply establishment signal PAVL is turned on only after its normally open contact 137 closes at τ2.

When the AC power supply is cut off at t3, the relay 133 is restored and the individual power supply establishment signal PAVL is turned off at t4.

On the other hand, since the DC voltage VDC decreases with a certain time constant due to the movement of capacitors provided in various parts, it remains above the operating voltage of the core memory until time τ2 has elapsed.

In FIG. 3, 131 is a bridge rectifier, and 133 is a capacitor.The capacitance of the capacitor 133 is adjusted so that the relay 134 will not be restored in the event of a momentary interruption of the AC power supply that does not affect the operation of the computer.

Returning to FIG. 2 and continuing the explanation, each computer's core memory 22 is connected to a DC power switch 23i from a power bus.
. . . Power is supplied via 23-n.

On the other hand, the individual power supply establishment signal of each power supply device is generated by the logic circuit 19.
connected to.

The logic circuit 19 determines that the individual power supply establishment signals of arbitrary n or more power supply devices among the (n+1) power supply devices are on, and turns on the system power supply establishment signal PRDY.

Such a logic circuit can be easily realized with a semiconductor logic circuit or a relay circuit, and FIG. 5 shows a power supply device 5.
An example in which the logic circuit 19 when using a stand is realized by a relay circuit is shown.

The relays 191a, . . . , 191e each have an individual power supply establishment signal PAVL1 . . . P
When AVL is turned on, it operates and closes each contact,
If four or more of these relays operate, relay 19
2 operates, its contact 193 closes, and the system power supply establishment signal PRDY is turned on.

The system power supply establishment signal PRDY is the power supply establishment switch 24
-1. . . . , 24-n are connected to the core memory control device of each computer.

The core memory control device 21 controls writing to the core memory and continuous output according to instructions from a program control device (not shown) of the computer, but if the applied system power supply establishment signal is not turned on, If the core memory does not start operating and the applied system power supply establishment signal is turned off, once one cycle of writing and reading is completed, subsequent operations are stopped and the contents of the core memory are saved. .

FIG. 6 shows the part of the core memory control circuit that performs this memory content storage function, where MST is a memory activation command issued from the program control device, RUN is a signal indicating that the computer is executing a calculation, The PC is an increment signal, 5TA, which increments the program counter of the program control device.
RT is the memory activation signal actually applied to the core memory,
5TOP indicates a memory stop signal.

When the memory start command MST is issued, the memory start signal 5TART is issued via the AND gate 217.
One cycle of core memory read and write operations is started, but if the system power supply establishment signal PRDY is turned off during this time, the AND gate is activated when the step signal PC indicating the end of the one cycle operation is issued. The clip-flop 215 is set by the output of 213, and the memory stop signal 5 is output via the OR gate 216 and the AND gate 220.
TOP is issued.

In this state, even if the memory start command MST is issued next, the inverter 218 closes the controller 1-217, and the memory start signal 5TART is not issued.

FIG. 7 shows a time chart during this period.

When the system power establishment signal PRDY is turned on again, the flip-flop 215 is reset, the memory stop signal is turned off, and the memory start signal 5TART is issued in response to the next memory start command MST.

Note that if the computer is running calculations, the core memory will not be in operation and the step signal PC will not be generated. Immediately upon the output of 214, a memory stop signal 5TOP is issued.

The operation of the entire embodiment described above will be explained using the time chart of FIG. 8.

To start up the computer system, first turn on the power switch 11-1°, 11-2......1l-(n
+1).

Next, the DC power switch 23-1...23
-n, and then the weight establishment switch 24-1...
...Inject 24-n.

In FIG. 8, the DC power switch 23-1 of the computer 20-1 is turned on at tl, and the power supply establishment switch 24 is turned on at t2.
This indicates that -1 was inserted.

The interval between turning on the DC power switch and turning on the power supply establishment switch must always be a time interval tR necessary for the voltage actually supplied to the core memory to rise, but the power supply device 10-1... ...1O-(n+1
) are abnormal, even if the power supply establishment switch 24-1 is turned on at t2 after this time interval tR, the power supply voltage supplied to the core memory at that time will not reach the operating voltage VCH. There is a possibility that it has not been reached.

However, according to the present embodiment, in such a case, the individual power supply establishment signal PAVL of the abnormal power supply device is in the off state, and the system power supply establishment signal PRDY is in the off state, so that t
Even if the power establishment switch 24-1 is turned on in step 2, the system power establishment signals PR and DY1 input to the memory division device of the computer 20-1 remain off, and the core memory is not activated.

Therefore, the core memory will not be activated with insufficient supply voltage and the stored contents will not be destroyed.

Furthermore, in FIG. 8, at time t3, the DC power switch 23
-1 is turned on, and the power supply establishment switch 24-1 is turned on at time t4. At this time, all the power supply devices have normally established the output voltage, and the system power supply establishment switch 24-1 is turned on.
DY is on, and when the power establishment switch 24-1 is turned on at time t4, the system power establishment signal PRDY1 is applied to the memory control m circuit of the computer 20-1.
is immediately turned on, allowing the core memory to be activated.

In such a case, the power supply voltage supplied to the core memory is established within the prescribed time interval tR, so that the stored contents will not be destroyed.

Also, during system operation, at time t, the power supply device 10-1,
If the power supply device 10-2 becomes abnormal at time t6, time t6
Immediately after, the system power establishment signal PRDY is turned off, and in response to this, the memory planning devices of all computers perform the processing explained in FIG. t7 in the figure indicates the point in time when the DC power switch 23-1 is shut off after learning that the computer has stopped operating.

In the operation explanation described above, the power switch 11-1.-
After turning on 11-'(n+1), the DC power switch 23-1...-23-n and the power supply establishment switch 24-1...・24-
An example has been shown in which the system is started by turning on the DC power switch 23-1, but according to the configuration shown in FIG.
......23-n and power supply establishment switch 2
4-1...24-n is turned on, turn on the power switch 11-1...11-(n+1)
(You may also start the system.)

Even if such a startup is performed, the output of the required number of power supplies is secured, and the core memory of each computer is allowed to operate because the system power supply establishment signal PRDY is turned on, so the contents of the core memory are not changed. Not destroyed (the entire system is activated).

For this reason, in a system where n computers are always operated simultaneously, the DC power switch 23-1...23-n and the power establishment switch 24-1... . . . 24-n does not necessarily need to be provided, and the power supply bus and system power establishment signal may be directly connected to each computer.

However, if the computers are connected via switches as shown in FIG. 2, maintenance can be performed by cutting off the power to any computer while the system is running.

Figure 9 shows the case where only the computer 20-1 is powered off while the system is running.
The DC power switch 23-1 may be turned off after the storage contents of the core memory are saved by turning off the DC power switch 23-1.

In the embodiment described above, power is supplied to n computers by (n7+-1) power supplies, and memory operation is performed by ensuring the output of the required number n of the power supplies. Although the configuration allows this, the number of power supply devices that are provided in excess of the required number is not limited to one, and it goes without saying that the reliability of the power supply increases as the number of power supply devices is further increased.

Also, the power capacity per power supply device may be arbitrarily selected.

However, if one power supply has a current capacity of 5,000 yen so that it can cover one computer as in this example, the system can be easily It is possible to create a power supply configuration suitable for

In other words, this embodiment has the most expandable system configuration.

As is clear from the above description, the present invention provides a power supply device that has low redundancy, has sufficiently high reliability against computer memory corruption caused by power supply abnormalities, and is easy to standardize power supply units and has high system expandability. can be obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a conventional power supply device, Figure 2 is a block diagram showing an example of a conventional power supply device.
Figure 1 is a block diagram showing one embodiment of the present invention, Figure 1 is a circuit diagram showing the internal configuration of block 13 in Figure 2, Figure 4 is a time chart showing the operation of Figure 3, and Figure 5 is a circuit diagram showing the internal configuration of block 13 in Figure 2. FIG. 6 is a circuit diagram showing an example of the internal configuration of block 19 in FIG. 2, FIG. 6 is a circuit diagram showing the function of block 210 in FIG.
8 and 9 are time charts showing the operation of FIG. 2. FIG. 8 and FIG. 9 are time charts showing the operation of FIG. 10-1...1O-(n+1)...
...Power supply device, 12...AC/DC conversion circuit, 13.
... Level detection circuit, 14 ... Diode, 18 ... Power supply bus, 19 ... Logic circuit, 20-1 ...・20-n...
...Computer, 23-1...23-
n...DC power switch, 24-1...
...24-n...Power supply establishment switch.

Claims (1)

[Claims] 1. In a system that supplies DC power to a system consisting of a plurality of computers, an extra number of power supply devices of the same capacity is provided for the number n required for the load, and their outputs are sequentially output. The plurality of computers are connected to a power supply bus via a directional diode, and each of the plurality of computers is connected to obtain power from the power supply bus, and each of the plurality of power supplies detects that its own output is established. A level detecting means is provided, and it is determined from the output of the level detecting means that the output of any n or more of the plurality of power supply devices is established, and the storage device is transmitted to the plurality of computers. A power supply device for a computer system, comprising a logic circuit that generates a signal for permitting operation. 2. The plurality of computers described in claim 1 are each connected to a power bus through a DC power switch, and the output of a logic circuit is connected through a power supply establishment switch. power supply for computer systems. 3. A power supply device for a computer system, wherein each of the plurality of power supply devices according to claim 1 has a current capacity sufficient to supply power to one of the plurality of computers.