JPS5816496B2 - Power supply abnormality control method for multiprocessor processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a power failure control method for a multiprocessor processing system, particularly in a multiprocessor processing system in which a plurality of central processing unit systems share a plurality of groups of peripheral device systems. In addition to providing switching devices that are controlled independently of each other at the intersections between the central processing unit system bus line and the peripheral device system bus line, the central processing unit system The power supply control unit that controls the main power supply to the main power supply and peripheral equipment system is placed under the control of the power supply control management device, and when the main power supply fails, the power supply control unit automatically forces the bus to the switching device. This invention relates to a power supply abnormality control method for a multiprocessor processing system that is capable of sending switching signals.

In order to improve the reliability and processing capacity of data processing systems, multiple central processing unit systems and multiple groups of peripheral equipment systems are combined, so that even if one central processing unit system goes down, other central processing units Efforts have been made to enable back amplification depending on the system, or to enable parallel processing by a plurality of central processing unit systems.

In the case of such a system configuration, a failure of one central processing unit system, one peripheral device system, or a failure of the switching device itself will not have an undesirable effect on the operating status of other healthy systems. Consideration must be given to such considerations.

For this purpose, a switching device is provided at each intersection of the central processing unit system bus line and the peripheral device system bus line, which can be turned on and off independently of each other, so that the bus can be disconnected independently as necessary. .

In addition, since the number of each component unit is extremely large in such a system, a stored program control power supply control management device is provided in the configuration processing device that includes the above-mentioned switching device, and the power supply control It is considered that the power supply of the entire system is centrally managed by a central control device.

Also, prepare at least two independent systems of AC power supplies for the central processing unit system power supply and the peripheral device system power supply, and set it so that power is supplied from either one.
Even if a failure occurs in any one of the systems, consideration is given so that the system can be operated in a degraded manner by the systems that are currently being supplied with power from the power sources of other healthy systems.

The present invention provides a power supply system as described above and a system for managing the same, in which when any of the plurality of power supply systems (main power supply) fails, processing by stored program control becomes congested and processing time is delayed. It is an object of the present invention to perform processing at high speed without waiting for processing under stored program control, and to enable at least forced bus switching to be performed on the switching device.

Therefore, in the power supply abnormality control method of the multiprocessor processing system of the present invention, a plurality of central processing unit systems and a plurality of groups of peripheral device systems use a switching device to switch each central processing unit system bus line and each peripheral device system bus line. In a multiprocessor processing system connected by turning on and off through a multiprocessor processing system, a switching device is provided corresponding to the intersection of each central processing unit system bus line and each peripheral device system bus line and controlled independently from each other. , a component processing unit having a power supply control section for controlling the power supply of the central processing unit system and the peripheral device system, and a power supply control management section for stored program control; The power control section is configured to turn on and off the power under the control of the power control management device in response to a power abnormality in the device system, and the power control section is configured to turn on and off the power under the control of the power control management device, and the power control section and each of the above-mentioned peripheral device systems is provided with a power supply setting circuit that maintains which of the plurality of mutually independent main power supplies is set to be supplied with power, and an output from the power supply setting circuit. Based on the output from the power supply abnormality detector of each of the above-mentioned multiple independent main power supply systems, each of the above-mentioned central processing unit system and/or peripheral device system that is supplied with power from the main power supply where the power supply abnormality has occurred is determined. A bus forced switching processing circuit that supplies a bus forced switching signal to the switching device associated with the busbar is provided, and when a power failure occurs in any of the main power sources, the power supply control section executes the above mentioned switchover signal. The present invention is characterized by being configured to directly send out the forced bus switching signal without waiting for the control of the power supply control supervising device.

This will be explained below with reference to the drawings. FIG. 1 shows the structure of an embodiment of the present invention, and FIG. 2 shows the structure of an embodiment of the main parts related to the present invention of the power supply control section shown in FIG.

In FIG. 1, 1-1 to 1-3 are central processing units, 2-1 to 2-3 are central processing unit system bus lines, and 3
-1 to 3-3 are configuration control devices, which monitor the status of each corresponding central processing unit system, communicate with each other, and perform cooperative processing of the entire system for each switching device SW. 4-1 to 4-n are peripheral device systems (or their channels), 5
-1 to 5-n are peripheral device bus lines, 6-1 to 6-3 are central processing unit power supply devices, 7-1 to 7-n are peripheral device power supply devices, and 8 is a configuration process. 9A and 9B are main power failure detection devices, 10 is a power control management device that performs stored program control, and 11 is a power control unit that is controlled by the power control management device 10. 5W11 to 5W3n each represent a switching device that controls power to each central processing unit system and each peripheral device system.

A again. B is a main power supply independent of each other, Xl to X6
y1 to y6 are power supply control signal lines, respectively, and zl to Z6 are bus forced switching signal lines, respectively.

Each central processing unit system and peripheral device system is set in advance to be powered from either the A or B main power source.

Even at the moment when one of the main power sources is out of power, degenerate system operation is possible in the system that is being supplied with power from the healthy main power source.

In the following, for example, it is assumed that the central processing units 1-1 and 1-3 and the peripheral device system channels 4-21 and 4-22 are powered by the main power supply of the A system, and the central processing unit 1-2 and the peripheral device The following description assumes that system channels 4-1 and 4-n are powered by the B system main power supply.

In the case of the system shown in FIG. 1, needless to say, for example, the central processing unit 1-1 is the switching device Sw1□, 5w12...
-3W, n can be turned on and off to connect or disconnect each peripheral device system.

The configuration control unit 3-3 performs priority processing for peripheral device systems between each central processing unit 1-1 to 1-3.
1 to 3-3 communication.

In the data processing system shown in FIG. 1, since the scale of the entire system is extremely large,
A power control supervising device 10 that performs stored program control is installed within the system, and is configured to control the power of the entire system and perform power-related processing in the event of system abnormality or power supply abnormality.

Regarding the power supply related to each central processing unit system and each peripheral device system, a power supply control unit 11 is provided below the power supply control management unit 10, and the power supply control unit 11 is connected to the power supply control management unit 10. The power supply devices 6-1 to 6-3 and 7-1 to 7-n are monitored or controlled under the control of the power supply devices 6-1 to 6-3 and 7-1 to 7-n.

In the case of the configuration shown in Figure 1, as mentioned above, there are two main power supply systems, A and B, and even if one of the main power supply systems fails, even at that moment, the system that is being supplied with power from the healthy main power supply system will continue to operate. It is made to become a degenerate system with dynamic power.

That is, as described above, for example, (I) the central processing units 1-1 and 1-3 and the peripheral device channels 4-21 and 4-22 are supplied with power by the A-system main power supply; (11) the central processing unit 1-2; And peripheral device channels 4-1 and 4-n are supplied with power by the B-system main power supply.

It will be done like this.

In the event of a power outage of the main power supply, the systems that are supplied with power from the main power supply will inevitably be disconnected from the system. If you try to
During emergency processing such as the above-mentioned power outage, the processing may be delayed and the bus switching processing based on the history of the switching device may be delayed.

In some cases, this may cause undesirable damage to a healthy system.

For this purpose, when the illustrated power supply control unit 11 is notified of a main power outage from the main power outage detection device 9A or 9B, it reports this to the power supply control management device 10 and also issues commands from the device 10. To force a so-called switching device associated with a main power supply in which a power failure has occurred to perform bus switching directly via signal lines Z1 to Z6 without waiting.

Of course, the forced bus switching is performed after a known termination processing sequence between the central processing unit and the peripheral device system has been executed.

FIG. 2 shows an embodiment of the configuration of the main parts of the power supply control section shown in FIG. 1 related to the present invention.

Symbols A, B, 9A, 9B, 11, Z, to Z in the figure
6 corresponds to FIG. 1, and 12 is a power supply setting circuit, which sets the power supply to each system as described in 1) and (11) on the upper floor, and outputs a logic "1" or "0". Those emitting , 13 to 24 are AND circuits, 25
30 to 30 represent OR circuits, respectively.

AND circuits 13 to 18 are main power failure detection devices 9, respectively.
The AND circuits 19 to 24 each receive a power outage occurrence signal from the main power outage detection device 9B.

Under the settings as described in (t) and (ii) above, for example, if the main power supply A is in a power outage state, the central processing unit system bus 2
-1°2-3 and the peripheral device system bus 5-2 become unusable.

At this time, the power supply control unit 11 responds to the power outage by switching the switching devices sw, 1. q, , , , , -, , , SW, .

sw , sw ,... History and 5w2231 32
A bus forced switching signal is sent to 3n1.

Furthermore, when the main power supply B goes into a power outage state, the central processing unit system bus 2-2 and the peripheral device system bus 5-1゜5-n become unusable, and the switching devices 5w21, 5w22゜...
..., 5W2n, Swn, 5w31. sw]n, 5w3
A bus forced switching signal is sent to the n.

That is, in FIG. 2, corresponding to the evaluation described in m and (11) above, AND circuits 13, 15, 17°20.22
, 24 are in a standby state where they can be turned on.

Then, when the main power failure detection device 9A issues a power failure occurrence signal, the AND circuits 13, 15, and 17 are turned on, and the signal Z
,,Z3. Z5 is sent out.

As a result, each switching device Sw receiving these signals
1□, 5W12. ......, 5w1n, sw
3□, 5w32..., 5w3n, 5w2
2 performs bus switching.

Further, when the main power failure detection device 9B issues a power failure occurrence signal, the AND circuits 20, 22, and 24 are turned on, and the signal Z2.
Z4. Z6 is sent out.

As a result, each switching device 5W20 . . . receives the respective signals.
S'w22. ......, 5w2n, 5w16
．． S'w30. S'w1n and 5w3n perform bus switching.

Needless to say, when the above bus switching is performed, the power supply control management device 10 performs other necessary processing.

As explained above, according to the present invention, it is possible to perform forced bus switching in the switching device 8v without being affected by processing delays in stored program control during emergency processing such as a main power outage. , it becomes possible to continue degenerate operation with a healthy system.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of one embodiment of the present invention, and FIG.
1 shows an embodiment of the configuration of the main parts related to the present invention of the illustrated power supply control section. In the figure, 1 is the central processing unit, 2 is the central processing unit system bus line, and 3
is a configuration control device, 4 is a peripheral device system (or its channel), 5 is a peripheral device system bus line, 6 is a central processing unit system power supply device, 7 is a peripheral device system power supply device, 8 is a configuration processing device, and 9 is a A main power failure detection device, 10 a power control management device, 11 a power control unit, 8v1 to SW3. are respectively switching devices, and A and B are respective main power sources.

Claims (1)

[Scope of Claims] 1. A plurality of central processing unit systems and a plurality of groups of peripheral device systems are linked by turning each central processing unit system bus line and each peripheral device system bus line on and off via a switching device. In a multi-processor processing system, mutual signals are provided corresponding to the intersections of the individual central processing unit bus lines and the peripheral device bus lines. a configuration processing device having a switching device that is independently controlled by the central processing unit, a power control unit that controls the power of the central processing unit system and the peripheral device system, and a power control management unit that controls a stored program; Power supply for the central processing unit system and peripheral device system. In response to an abnormality, the power supply control unit is configured to turn on and off the power under the control of the power supply control management unit, and the power supply control unit is configured to turn on and off the power under the control of the power supply control system, and It is equipped with a power supply setting circuit that maintains which of the plurality of mutually independent main power supply systems each of the peripheral device systems is set to be supplied with power, and outputs from the power supply setting circuit and the plurality of systems mentioned above. Based on the outputs from the power supply abnormality detection parts of the mutually independent main power supplies,
A bus forced switching processing circuit that supplies a bus forced switching signal to the switching device associated with each bus of the central processing unit system and/or peripheral device system that is supplied with power from the main power supply where the power supply abnormality has occurred. The present invention is characterized in that, when a power failure occurs in any of the main power sources, the power supply control unit is configured to directly send the bus forced switching signal without being controlled by the stored program controlled power supply control management device. Power supply abnormality control method for multiprocessor processing systems.