JPS5816773B2 - Intra-station phase synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is designed to eliminate phase differences caused by variations in the transmission path lengths of multiple lines that are phase-synchronized on the incoming side of the station and transmitted within the station, on the receiving side. This relates to an intra-station phase synchronization method for absorption.

Conventionally, an intra-office phase synchronization system is configured as shown in FIG.

That is, in Fig. 1, 1 indicates outside the station building, 2 indicates inside the station building, 3 indicates the end station repeater, and 4 indicates the frame phase synchronization for the signals transmitted between stations at the unified timing within the station. 5 is an internal clock supply device, 6 is an internal frame phase supply device, 7 is a phase synchronizer for obtaining phase synchronization, and 8 is a waveform shaping device for the internal unified clock supplied from the internal clock supply device 5. and an internal clock supply device for distributing this to a device 7 for obtaining phase synchronization, 9 a waveform shaping circuit, 10 an equalization amplifier, 11 a clock extraction circuit, 12 an identification circuit, and 13 a variable delay line. ,1
4 is a retiming circuit, and 15 is a frame synchronization signal extraction circuit.

16 is a shift register, 17 is a strap terminal, 18 is an intra-office line connecting the end-office repeater 3 and frame phase synchronizer 4, 19 is a line for guiding the inter-office transmitted signal to the intra-office clock supply device 5, and 20 is 21 is a line for supplying the clock from the local clock supply device 5 to each transmission device; 21 is a line for supplying the frame phase synchronization device 4 with the claim phase from the local frame phase supply device 6; 22 is a signal local transmission line. , 23 is an in-office unified clock supply line, 24
is the intra-office line on the output side of the intra-office phase synchronizer.

Next, to explain the operation of this conventional example, first, the input signal within the station is bit phase synchronized by the frame phase synchronizer 4 to the station unified clock using the station unified clock and the station reference frame phase, and the reference frame phase will be synchronized.

The phase of this phase-synchronized signal is changed by the intra-office transmission line 22.

The received frame phase is transmitted to the synchronization device 7, but since the intra-office transmission path length varies, the received frame phase differs for each line.

Also, a virtual base that is equal to or further behind the most delayed frame phase among the line bundles to be phase synchronized.

If Δθi is the phase deviation between the quasi-frame and the line with number i of interest (Δθi<<TF, where TF is the frame period), and [Δθi] is the symbol representing the largest integer that does not exceed Δθi, then Δθi is It is expressed as Δθi=(Δθi)A+(Δθi)D where Δθi)A3Δθi−CΔθi] (Δθi)D3[Δθi].

In this equation, (Δθi)A represents a phase deviation of 1 bit or less, (Δθi)D represents an integer bit of Δθi, and the phase synchronizer 7
This is a device that synchronizes so that θi is constant.

In this device 7, the received signal is equalized, amplified, waveform-shaped, and retimed by adjusting the frame phase so that it can be retimed using the in-office unified clock, and is retimed within 1 bit corresponding to (Δθi)A of the music composition. frame phase deviation is removed.

Next, the shift register 16 selects the shifted terminal with the bit number corresponding to (Δθi)D, and the line 24 is strapped by the strap terminal 17 to take out the output.

With this configuration, the variable delay line 13 is adjusted in advance to match the line, and then the strap terminal 17 is adjusted after checking all the frame phases of each line after the virtual reference phase timing. stage adjustments are required;
Although the phase deviation within the station is relatively small, it has the drawback of requiring a great deal of effort for adjustment.

In addition, since the frame signal has a specific fixed pattern and is transmitted in a state in which it is indistinguishable from data, the frame synchronization signal extraction circuit 15 has a function of checking pattern matching, a function of shifting the input signal, and a function of changing the pattern. After confirming the match, a circuit with a function to check whether it is not pseudo-synchronized is required, which results in a large circuit size, which is disadvantageous in terms of packaging density and economy when used for an in-office phase synchronization device required for line support. was there.

In order to eliminate the drawbacks of the conventional example, the present invention provides bit phase synchronization and frame phase synchronization at the input side of each circuit, and when transmitting within the station, the phase difference that occurs on the receiving side due to variations in the length of the transmission path within the station. The present invention provides an intra-station phase synchronization system characterized in that phase synchronization is achieved by absorbing deviations by using an elastic memory in which writing and reading can be controlled independently or a memory that operates equivalently.

Hereinafter, embodiments will be described in detail with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, in which the same reference numerals as in FIG. a distribution line, 27 a frame synchronization circuit, 28 a write address counter, 29 a read address counter,
30 and 31 are decoders corresponding to address counters 28 and 29, respectively, 32 and 33 are write and read selectors, 34 is a memory, and 35 is an OR gate.

Next, the operation of this embodiment will be explained.

As in the conventional example shown in FIG. 1, the frame phase synchronization device 4 performs frame phase synchronization at the uniform timing within the station.

This phase-synchronized signal is transmitted within the station via the intra-office line 22, and is identified and reproduced by the receiving circuit in the same manner as in the conventional example shown in FIG.

The frame synchronization signal on the write side is separated from the clock extracted from the received signal and the identified and regenerated pulse train.
Reset the address counter in memory 34.

The address specified by write address counter 28 is decoded by decoder 30 and one gate of read selectors 32 is selected to write data into memory 34 .

On the other hand, data from the memory 34 is read by controlling the read address counter 29, decoder 31, and read selector 33 in the same way as writing using the internal station unified clock and the reference frame phase.

The phase of the reference frame that determines the readout phase is the line bundle whose phase at the position of the readout address counter 29 should be phase-synchronized.

The intra-office frame phase supply device 6 controls and supplies the signal so that it is further delayed than the phase that is the most delayed among them, and the reference frame pulse waveform shaping circuit 25 obtains it in bit synchronization with the intra-office unified clock.

FIG. 3 shows the relationship in the phase synchronization described above. and
AI I A21..., An corresponds to the input line in FIG.

With such a configuration, the intra-office frame phase supply device 6
When supplying the frame phase to the frame phase synchronizer 4 and the internal clock supply device 7, it is necessary to control and supply this frame phase, but the memory 34 for phase synchronization corresponds to the variation in the internal transmission path length. the number of bits to
This can be achieved with a memory capacity equal to the phase margin plus the required number of bits.

Note that, as shown in the embodiment of FIG. 2, if a memory in which writing and reading can be controlled independently is used, as shown in the conventional example of FIG. It is not necessary to switch the taps of the shift register for adjustment and phase adjustment of 1 bit or more for each device (there is an advantage that these adjustments can be made simultaneously and automatically, so there is an extremely large labor-saving effect. Not only that, but it also has the advantage of being able to handle failure recovery very quickly.

FIG. 4 shows another embodiment of the present invention, in which the method of supplying the reference frame phase is different from that in FIG. 2, but the same reference numerals as in FIG. 2 indicate the same things. , also 36
is a delay circuit.

In this embodiment, the reference frame phase is not received from the intra-office frame phase supply device 6, but is obtained by using the frame synchronization signal of any one of the line bundles to be intra-office phase synchronized, as shown in FIGS. The delay circuit 36 shown in FIG. 8 delays the phase by a delay time greater than the maximum phase deviation corresponding to variations in the intra-office transmission path length of each line, and supplies it to the device 7 for achieving phase synchronization.

FIG. 5 shows an embodiment of the delay circuit 36 in FIG. 4, in which 37 is a reference frame phase generation control line, 38 is a variable delay circuit, 39 is an AND circuit, 40 is a load control terminal,
41 is a data terminal for loading, 42 is a frame counter, 43 is a NAND circuit, 23 is an in-office unified clock supply line connected to the clock terminal of the frame counter 42, 26 is a reference frame phase distribution line, 27 is a frame synchronization circuit.

Next, the operation of this circuit will be explained using the time chart shown in FIG.

The variable delay circuit 38 is inserted to maintain a good timing relationship between the phase of the local unified clock and the phase of the output pulse of the frame synchronization circuit 27, and the reference frame phase generation control line 37 is connected to the initial stage of the frame counter 42. This is provided to load the phase, and control pulses are sent according to a separately determined control procedure during manual operation or in the event of a failure.

On the other hand, the data terminal 41 for loading is connected to the frame counter 4.
It is used to provide load data for loading data equal to the number of stages of 2, and this load data is provided, for example, by applying a pulse to the load control terminal 40,
If the reference pulse is to be output to the reference frame phase distribution line 26 after N bits, it is necessary to set the state of the counter before N bits.

When a control pulse is applied to the load control terminal 40, the frame counter 42 loads the data of the data terminal 41 for loading, starts counting from the next cross-shift pulse, and generates a frame synchronization pulse that matches the initially set phase. Output.

With the configuration shown in FIG. 4, there is no need to control and supply the reference frame phase using the intra-office frame supply bag, so there is an advantage that the intra-office frame phase shift supply device 8 can be constructed easily.

Further, as long as no control pulse is applied to the reference frame phase generation control line 37, the reference frame phase is constantly added by the output of the frame counter 42, so even if the frame phase of the frame synchronization circuit 27 fluctuates for some reason. This has the advantage of providing a stable reference frame phase.

7 and 8 respectively show other embodiments of the delay circuit 36 in FIG. 4, and the same numerals 4 as in FIG. 45 is a timing circuit, and 46 is a shift register.

In FIG. 7, the delay line 45 is a circuit that retimes the reference frame phase using the local unified clock;
Fig. 8 Delay.

The amount of circuit delay required is the amount corresponding to the N bits in FIG.

By using the delay circuit as described above, there is an advantage that the reference frame phase can be supplied with an extremely simple circuit.

FIG. 9 shows another embodiment of the frame phase synchronization device of the present invention, which uses a bipolar violation transmission method that changes the waveform conversion rule so that the frame synchronization signal can be distinguished from data as an intra-office transmission method. I am using it.

Figure 9 Smell. 4, the same reference numerals as in FIG.
0 is a D flip-flop, 51 is an AND gate, and 52 is an OR gate.

Next, the operation of this embodiment will be explained with reference to the time chart of FIG.

The code string transmitted within the station via the intra-office transmission line 22 includes the shaded code in FIG. 10 at the position of the frame synchronization signal.

Since this disturbs the original bipolar rule, this irregularity is detected by the AND gate 51 and the OR gate 52 based on the outputs obtained from the RS flip-flop 49 and the D flip-flop 50.

In this way, the frame synchronization signal can be obtained with a simple circuit, so the local phase synchronization circuit can be integrated with the local transmission system that transmits the frame synchronization signal in a form that is easy to separate, thereby reducing the circuit scale. , an economical method can be realized.

In addition to the bipolar violation shown in Figure 10, intra-office transmission systems suitable for this purpose include a system in which the frame synchronization signal is transmitted in a waveform different from that of the data; It can be realized with a circuit.

As explained above, according to the present invention, in binary ζ rus transmission, frame phase synchronization is first performed on the input side within the station using the unified timing within the station.

This absorbs large variations in delay between stations, so variations in delay occurring within a station are as small as a few bits.

Moreover, the variation in this delay can be calculated.

Therefore, it is possible to set the read frame phase, that is, the reference frame phase, with a phase margin for this delay variation.

The present invention eliminates the conflict between the frame phases of the input and output of the elastic memory by setting such a reference frame phase. Therefore, the present invention eliminates the need for a detection circuit for the input and output frame phase difference, and allows the phase within the station to be determined without slipping. It is possible to synchronize.

In this way, the present invention can simultaneously and automatically absorb phase deviations of 1 bit or more and phase deviations of 1 bit or less to achieve phase synchronization, which has the advantage of facilitating adjustment and maintenance during construction.

Therefore, the present invention is suitable for an intra-office phase synchronization method in a digital integrated network.

In addition, by changing the regularity of the data to make it easier to separate the frame synchronization signal for intra-station transmission, and by using a combination of the method of changing the waveform and the above-mentioned intra-station phase synchronization method, the circuit size of the intra-station phase synchronization device can be reduced. It has the advantage of being small and realizing an economical intra-station phase synchronization system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional intra-station phase synchronization system, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a diagram explaining the intra-station phase synchronization relationship of FIG. 5 is a block diagram of another embodiment of the present invention, FIG. 5 is a block diagram of one embodiment of the delay circuit of FIG. 4, FIG. 6 is a time chart explaining the operation of FIG. 5, and FIG. 8 is a block diagram of another embodiment of the delay circuit shown in FIG. 4, and FIG. 9 is a block diagram of yet another embodiment of the present invention, in which intra-station transmission and intra-station phase synchronization system are integrated. , 10th
The figure is a time chart for explaining the operation of FIG. 9. 1...Outside the station building, 2...Inside the station building, 3...
...End station repeater, 4...Frame phase synchronizer, 5...Internal clock supply device, 6...
... Intra-station frame phase supply device, 7... Phase synchronization device, 8... In-office clock supply device, 9.
... Waveform shaping circuit, 10 ... Equalization amplifier, 11 ... Clock extraction circuit, 12 ...
- Identification circuit, 13... Variable delay line, 14...
... Retiming circuit, 15 ... Frame synchronization signal extraction circuit, 16 ... Shift register, 1
7...Strap terminal, 18-24...
・Internal line, 25...Waveform shaping circuit, 26...
...Reference frame phase distribution line, 27...
Frame synchronization signal extraction circuit, 28...Write address counter, 29...Read address counter, 30.31...Decoder, 32...
・Write selector, 33...Read selector, 3
4...Memory, 35...Or Gate,
36...Delay circuit, 37...Reference frame phase generation control line, 38...Variable delay circuit,
39...AND circuit, 40...Load control terminal, 41...Load data terminal, 42
... Frame counter, 43 ... NAND circuit, 44 ... Delay line, 45 ... Retiming circuit, 46 ... Shift register, 4
7, 48...Identification circuit, 49...RS
Flip-flop, 50...D flip-flop, 51...AND gate, 52...
Orgate.

Claims (1)

[Claims] 1. Writing and reading for absorbing frame phase differences on the receiving side caused by variations in transmission line length within the station in a system that synchronizes the frame phase of digital devices that operate synchronously within the station. . The writing/reading control of the memory is performed by writing data into the memory using a clock synchronized with the phase of the received signal and a frame synchronization signal extracted from the received signal. , of the line bundle to be phase synchronized. An intra-office phase synchronization method characterized in that a reference frame phase set to absorb a frame phase fluctuation width is received from a device for supplying an in-office timing signal, and reading is performed using the clock and the phase. 2. A memory that can independently control writing and reading to absorb frame phase differences on the receiving side caused by variations in transmission line length within the station in a system that synchronizes the frame phase of digital devices that operate synchronously within the station. The writing/reading control of the memory writes data to the memory using a clock synchronized with the phase of the received signal and a frame synchronization signal extracted from the received signal, while the device for supplying a timing signal within the station A reference frame phase created by passing the supplied station unified clock and frame phase synchronization of any one line of the line bundle to be phase synchronized through a delay circuit having a delay larger than the frame phase variation width. An intra-station phase synchronization method characterized in that readout is performed using. 3 Memory that can independently control writing and reading to absorb frame phase differences on the receiving side caused by variations in transmission line length within the station in a system that synchronizes the frame phase of digital devices that operate synchronously within the station. The writing/reading control of the memory writes data to the memory using a clock synchronized with the phase of the received signal and a frame synchronization signal extracted from the received signal, while writing data into the memory using a clock synchronized with the phase of the received signal and a frame synchronization signal extracted from the received signal. The in-station phase synchronization method performs reading using a reference frame phase that is set to absorb the frame phase fluctuation width of the frame, and the transmission waveform of data and frame synchronization signals that disturbs the regularity of data code transmission. An intra-office phase synchronization method characterized in that the circuit scale of an intra-office phase synchronization device is reduced by combining an intra-office transmission method in which frame synchronization signals can be easily separated by changing the .