JPS5816778B2 - Frame synchronization method - Google Patents

Description

[Detailed description of the invention] The present invention relates to a frame synchronization method.

For example, in a time-division PCM transmission device, the position of a marker bit in a bitstream is detected by examining the correlation between corresponding bits in each frame;
A frame synchronization method that performs frame synchronization is known.

That is, when a received bitstream as shown in FIG. 6 is arbitrarily divided by frame length N, bit contents that are the same as each other are placed at a specific bit position k of each frame (the third bit from the division in FIG. 6). That is, (a)=(b
) - (c) - (d) = ... (1) or the bit contents inverted for each frame, that is, (a) - (b) = (C) = (d) = ...・-(2)
If exists, it is determined that there is an inter-frame correlation for bit position k, and if the relationship (1) or (2) does not exist for k, it is determined that there is no inter-frame correlation. be done.

Two-stage stack and frame synchronization methods are used for this type of frame synchronization.
There is a 3-bit memory pattern detection - 1-bit immediate shift method, a 3-stage stack memory 4-bit pattern detection - 1-bit immediate shift method, etc., but the disadvantage of these methods is first that the resynchronization time is relatively long. Second, the circuit is complicated, which increases the price of the device. Third, increasing the memory capacity will shorten the resynchronization time (although it tends to become shorter if you increase the memory capacity to a certain extent). Even if the capacity is increased, the resynchronization time hardly decreases, and ends up converging to a considerably long resynchronization time.

Therefore, an object of the present invention is to provide a relatively simple circuit that eliminates the drawbacks of the prior art described above, and as the memory capacity increases by increasing the register length for the memory, the limit value of the resynchronization time becomes almost zero. The objective is to provide a frame synchronization method.

The feature of the method of the present invention for achieving the above object is that M(=1.2,...
. . . ) bits, and a means for calculating the inter-frame correlation of the frame display pattern detection results consisting of a small number of bits (all consisting of 1 bit) for these digit positions, and an M-bit length for storing the inter-correlation calculation results. and a shift register, and if the contents of the shift register indicate no correlation, select the digit position of the M bit after the M bit in the next frame or after the next calculation frame to calculate the interframe correlation. If there is a correlation, the number of frames determined to be correlated is counted, and when this counted value exceeds a certain value and the number of digits indicating the presence of correlation in the shift register is only one bit. To,
A frame in which the detection start digit position is always aligned with the digit position indicating the presence of correlation in the next frame or after the next calculation frame so that the digit indicating the presence of correlation is located at the rear end of the shift register. It is in a synchronous method.

The system of the present invention will be explained in detail below with reference to the illustrated embodiments.

FIG. 1 shows an embodiment of a frame synchronization circuit to which the method of the present invention is applied.

The purpose of the frame synchronization circuit shown in Figure 1 is to detect a specific correlated bit position k (see Figure 6) using as few frames as possible, given the frame length N of the received bitstream. There is a particular thing.

This frame synchronization circuit 1 receives 1 input from an input terminal 2.
Frame synchronization is achieved with a bit-serial PCM input signal S1 whose frame consists of 386 bits.

In the PCM input signal S1, the first digit in each frame is used as a frame display pattern, and the logic level of this digit is determined by a transmitting side (not shown) so that adjacent frames always have opposite logic levels.

Therefore, in the frame display pattern, "1" and "0" alternately appear in consecutive frames.

The input PCM signal S1 is input to the frame pattern detection section 3, and when a digit that is considered to be a frame pattern existing in the signal S1 is input into the detection section 3, its level changes to "l" in response to this input. A detection pulse S2 is output from the output terminal 3a of the detection section 3.

That is, the frame pattern detection unit 3 detects the same pattern as the marker bit included in the bitstream, regardless of whether there is a correlation or not.

(The bitstream may contain a pattern that has the same pattern as the frame pattern but has no frame correlation, that is, a pseudo frame pattern.

) Select and extract the detection pulse S2 corresponding to 5 bits at a predetermined digit position in each frame of the PCM input signal S1, and also take the correlation between frames of the detection pulse S2 which is the frame pattern detection result from the frame pattern detection section. Therefore, a correlation detection circuit 4 is provided.

The correlation detection circuit 4 is composed of a 5-bit shift register 5, an AND gate 6, and an OR gate 1. The AND gate 6 receives a detection pulse S2, an output signal S3 of the shift register 5, and a 5-bit/10-bit A first 5-bit gate signal S4 from the counter 8 is input.

5 bit/10 bit counter 8 is frame counter 9
The clock pulse S6 is reset by a reset pulse S5 from the clock input terminal 10 and is applied as a clock signal to the clock terminal 8a via the inverters 11 and 12.

In addition to the first 5-bit gate signal S4, the counter 8 receives the second 5-bit gate signal S4 at a predetermined timing by inputting the reset pulse S5.
A bit gate signal S7 and a 10-bit gate signal S8 are output as shown in FIGS. 2a to 2e.

The second 5-bit gate signal S7 is input to the Nant gate 13 together with the inverted clock pulse 6, and the Nant gate 1
The output of 3 is input to the Nant gate 15 together with the q output of the D-flip 70 tube 14, and the shift clock S is input to the shift register 5 only during the period when the first 5-bit gate signal S4 from the Nant gate 15 is at the rtJ level. Supplies only pulses.

Therefore, in the correlation detection circuit 4, first, the 5-bit frame pattern detection results at a predetermined digit position of the first frame are sequentially input into the shift register 5, and from the next frame onwards, the 5-bit frame pattern detection results at a predetermined digit position are sequentially inputted into the shift register 5. The AND gate 6 is opened by the first 5-bit gate signal S4, and at this time, the contents of the shift register 5 are changed by the shift clock S to the AND gate 6 in synchronization with the detection pulse S2 being output from the output terminal 3a. The detection result of the previous frame and the detection result of this frame are correlated for each bit in Antogeatro.
This correlation result is sequentially stored in the shift register 5 via the OR gate 7 opened.

This correlation result is applied to the other input of an AND gate 16, one input of which receives an inverted clock pulse S6, the output of which is an R8 flip-flop 17 which is reset by a reset pulse S5.
is input to the set input of

Therefore, if a determination result indicating no correlation is obtained for any of the predetermined 5 digit positions (that is, if the output from the AND gate 6 is rOJ for any digit position), the R8-flip - The output signal SsO of the flop 17 remains at "1", and the Q output of the D-flip-flop 18 reset by the reset pulse S also remains at "1".

This R8-flip flop 17 and D-flip 7
0ZG 18 detects whether the contents of the shift register 5 have become all zeros, in other words, it is detected whether or not there is a digit that exhibits a strong correlation between frames among all the 5 bits in question.

When the contents of the shift register 5 are all zeros, the D-flip frog 18 is used to repeat the same operation for the next 5 digit positions after all the 5 digit positions investigated.
The output is input to a shift circuit 20 for shifting the frame counter 9 by 5 bits.

That is, a 10-bit shift pulse appears on the clock signal S input to the shift register 5 to perform the correlation detection of the next 5 digits, and the results for the previous 5 digits are shifted out.

Since the signal 515 (all 1's) is shifted into the register 5, the detection pulse S2 is written into the register 5 as is in the detection of the next five digits.

The shift circuit 20 includes a Nant gate 21, a NOR gate 22 .
It consists of 23.

The input of the Nant gate 21 is a D-flip-flop 1.
The Q output of 8 and the 10 bit gate signal S8 are input, and when the Q output is "1", the output of the NAND gate 21 is "0".

As will be described in detail later, one input of the NOR gate 22 becomes the "0" level when the synchronization signal S1□ of the control circuit 24 is at the "11" level when an out-of-synchronization state is detected. Therefore, the NOR gate 23 is closed, and input of the inverted clock pulse S6 to the frame counter 9 is prohibited.

This inhibited state continues until the 10-bit gate signal S8 changes from the "1" level to the "0" level, so that in the end only 5 bits of the inverted clock pulse g6 are not input.

Therefore, the reset pulse from the frame counter 9 is output with a delay of 5 bits compared to the normal case, so the position of the 5 digits for correlation in the next frame is 5 digits relative to the 5 digit position of the previous frame. It will be shifted backward by one bit.

In this way, if it is determined that there is no correlation as a result of taking the inter-frame correlation for the 5 digit positions of interest in the AND gate 6, the 5 digit positions are successively shifted by 5 bits as described above and the same process is performed. Repeat the action.

Next, the result of correlation between frames is at least 1
The operation when it is determined that the digits are correlated will be explained.

If it is determined that there is a correlation in at least one of the predetermined five digits, the Q output of the D-flip frog 18 becomes "0", so as will be readily understood from the previous explanation, the shift circuit 20 noah gate 23
is not closed, and the frame counter 9 outputs the reset pulse S again in response to the 386th clock pulse from the generation point of the previous reset pulse S5.

Therefore, in the next frame, the correlation detection circuit 4 again sequentially compares the detection pulse S2 at the same digit position as in the previous frame with the contents of the shift register 5 to determine the correlation.

At this time, the contents of shift register 5 must be "1" again.
5 in each frame for correlation detection.
Repeat the same operation once again without changing the digit position.

This repeated operation is for backward protection, and the number of times this operation is repeated is counted in the control circuit 24 using the q outputs of the D-flip-flops 1 and 8 and the reset pulse S5. It is determined whether or not there is a frame synchronization bit (or pattern) in the five digits based on whether the number exceeds the number.

Also, at this time, the number of "1"s in the contents of the shift register 5 is checked, and if the number of repetitions of 1 exceeds a predetermined number and only one "1" is included in the contents of the shift register 5. The synchronizing signal S1□ becomes "0" level.

The synchronous output signal Sll is applied to one input of the R8-7 lip-flop 25, and the output signal S3 from the shift register 5 is input to the other input, so the signal S1□ is "0". Then, an inverted output signal S3 is outputted from the output, which is inverted again by the inverter 26 and applied to the input of the NOR gate 22.

Assuming that the contents of the shift register at this time are (00010), the signal S12 of the Q output of the D-flip-flop 18 changes from "0" to "1" when "1-1" is output from the output of the shift register 5. ”, the output signal 313 of the Nant gate 21 becomes the inverted clock pulse S6.
3, the waveform becomes as shown in FIG.

Therefore, the signal S14 from the inverter 26 has a waveform as shown in FIG. 3e, but since it is input to the NOR circuit 22 together with the output signal S13, the output signal St5 of the NOR circuit 22 is as shown in FIG. 3d. The waveform becomes =.

Therefore, since the inverted clock pulse 6 applied to the frame counter 9 via the NOR gate 23 is inhibited by 3 bits, the output timing of the next reset pulse is shifted by 3 bits, and the digits indicating the correlation in the shift register 5 are inhibited by 3 bits. .

Because of this 3-pit reset pulse, it comes to the rear end of the shift register 5, and the detection start digit position can always be aligned with this digit position indicating that there is a correlation.

In this way, body synchronization is completed.

This synchronization state is constantly monitored by the inverter 27 and the Nant gate 28, and when the error pulse signal from the Nant gate 28 exceeds a predetermined pulse density, the control circuit 24 determines that frame synchronization has been lost, and performs the above-mentioned operation. Repeat again to perform synchronous pull-in.

This operation is shown in a flowchart as shown in FIG.

In the above embodiment, a 5-bit shift register is used, and 5 bits in a frame are taken out to obtain a correlation between frames. However, the number of bits is not limited to 5 bits, but any number of bits may be used.

Further, it goes without saying that the number of bits for the frame synchronization pattern is limited to 1 bit and any number of bits may be used.

Now, assuming that this number of bits is M bits, the average value <T> of the resynchronization time according to the method of the present invention is calculated as follows.

First, express correlation as 1'' and no correlation as 0'', and in order to check the contents of the shift register after repeating looping n times, the pattern detection result Dn is expressed as Dn = (X, n, X2 n, ...+-+4Mn
) ---・(1).

Here, n is the looping number and indicates the number of times, and
in is the digit (x
inεGF2).

"i-th bit of shift register after n-layer ping" (X
ir, r=1 to n) are all 1, which is the probability that the complement of the event occurs, and is.

Here, Pe is the probability that X1j-1. Therefore, n
The probability PnS that the contents of the shift register become all zeros in the second looping is PnS=(1-(Pe)n)M...Song (4).

When it becomes all zero, it is shifted by M bits, so this becomes the shift probability.

Using equation (4) to find the probability PnL of looping for n+1 times, Pn -1-pns ...... ~------...
・−・・・−・・−・・・・(5) PnL= 1
(1(Pe)n)''--(6).

From these, the probability PnFST that a shift occurs for the first time after the nth looping is determined.

Therefore, the average number of looping <n> until the M-bit shift occurs, and the resynchronization time <T> becomes, where τ is the looping time and L is the frame length.

Therefore, if we increase the register length M, <T> will decrease by nM, and if we simply increase M, <T> will decrease by nM.
T> can be made small, and its limit value becomes approximately zero.

However, in other conventional methods, even if the register length is increased, <T> becomes smaller to some extent, but its ultimate value approaches (only) a predetermined constant value that is not zero.

This situation is shown in FIG.

According to the present invention, the resynchronization time can be brought close to approximately zero by simply increasing the register length as described above, and the operation of correlating the predetermined M bits with the previous frame and storing the result in the register is also possible. High speed is only required for this process, and the subsequent processing can be performed during one loop, so there are many low-speed processing parts, and the circuit can be constructed at low cost.

Furthermore, since the algorithm is relatively simple compared to conventional systems, it has excellent effects such as a simpler circuit.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment according to the method of the present invention, Fig. 2a
2e to 3e and 3a to 3d are time charts for explaining the operation, FIG. 4 is a flowchart showing the operation of the circuit in FIG. 1, and FIG. 5 is a diagram showing the operation when the register length is increased. Diagram 6 to show how the average value of resynchronization time changes
The figure is a diagram for explaining the presence or absence of interframe correlation in a pit stream. DESCRIPTION OF SYMBOLS 1... Frame synchronization circuit, 3... Frame pattern detection section, 4... Correlation detection circuit, 5
...Shift register, 8...5-bit/10-bit counter, 9°-゛° frame counter, 20°...-shift circuit, 24...-control Circuit, Sl...-PCM input signal, S2...
...detection pulse, S4 ...first 5-bit gate signal, S5 ...reset pulse, S6 ...
...Clock pulse, S7...Second 5-bit gate signal, S8...10-bit gate signal,
S...Shift clock, Sll...
Synchronous output signal.

Claims (1)

[Claims] 1 M (=1.2
, . . . - . . If the contents of the shift register indicate no correlation, the digit position of the M bits after the M bits is selected in the next frame or after the next calculation frame to perform interframe correlation. If there is a correlation, the number of frames determined to be correlated is counted, and if this counted value exceeds a certain value and the number of digits in the shift register that are displayed as correlated is only 1 bit. Then, in the next frame or after the next calculation frame,
A frame synchronization method characterized in that the digit indicating the presence of correlation is placed at the rear end of the shift register so that the detection start digit position is always aligned with the digit position indicating the presence of correlation.