JPS5816835B2 - Audio multiplex signal receiving circuit for TV receivers, etc. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an audio multiplex signal receiving circuit for a television (hereinafter abbreviated as TV) receiver, etc., and in particular to an audio multiplex signal receiving circuit for an FM-FMM multiplex system that reduces parts by making it into an IC. The purpose of this is to reduce the amount of work required and reduce the number of man-hours involved.

In this type of circuit, an LPF (low pass filter) and a BPF (band pass filter) are used to separate the main and sub channels, respectively, but these filters both have inductance components and also perform stereo separation. In order to make it easier to obtain the delay time, a predetermined delay time (20
μ5ec), and therefore the adjustment precision of the bandpass filter portion must be extremely strict, which has been a bottleneck in implementing an efficient and effective IC.

As illustrated in FIG. 1, such a trap-equipped BPF includes a bridge T-type trap T1 for removing the stereo switching control signal 3.5fH, and fH (horizontal scanning frequency) and 3fH provided for the purpose of reducing buzz noise. Parallel traps T2, T3 and B P of 31.5±15.5KHz
F (B).

In view of the above points, the present invention attempts to achieve the intended purpose by configuring the BPF as shown in FIG. 3, and configuring the main circuit parts as shown in the circuit block diagram of FIG. 2. .

First, the circuit configuration of the main part will be explained with reference to FIG.

The FM-FMM voice multiplex signal which is the SIF detection output is 7'
L for main channel signal via IJ amplifier PA
For PF and sub-channel signals, a trap equipped HPF (bypass filter) T-HPF (
The details will be described later).

The extracted sub-channel signal is passed through a limiter amplifier A1 to a shift register SR, which is another feature of the present invention.
After FM demodulation according to the pulse counter format, the signal is input to the stereo matrix circuit M via the amplifier A2, the stereo changeover switch ST1, the low-pass filter LPF, and the multiplex changeover switch S1.

This circuit, together with the main channel signal that is input via a separate buffer circuit BF (generally refers to circuits such as emitter follower, de-emphasis, delay, etc. ), (L-R) system] are separated into L-R signals, which are individually connected to corresponding audio amplifiers AR and AL via selection switches SL1 and SL2.

The stereo switching control signal and the multiplex switching control signal are similarly separated from the HPF and are individually passed through filters TF1. TF2 and correspondingly subsequent amplifier A4,
Diode detection via A5 (diodes DI, D2)
After that, the stereo selector switch SS and the multiplex selector switch SM are actuated individually, and the corresponding display means L1 . Audio multiplexing detected by turning on L2 and energizing the movable contacts of switches 81 and 82;
The necessary circuits are selected or displayed according to each stereo mode.

Next, the HPF with trap shown in FIG. 3 will be explained.

In this circuit, each of the bridge T-type 3.5fH traps T1, fH and 3fH) wraps T2 and T3 are the same as in the conventional example shown in FIG.

HPF has an inductance L1 and two capacitors CI
, C2 is enabled, and the sub-channel signal and stereo/multiplex switching control signal are
The configuration is such that the main channel signal is extracted from between the E terminals and from between the FG terminals.

Next, an example of an FM demodulation circuit including the shift register SR will be explained with reference to FIGS. 4 and 5.

The shift register SR includes a JK flip-flop F1
．． F2. F3. F4 are sequentially connected in cascade, and each flip-flop has 3
, 58 MHz color subcarrier signal by a frequency dividing circuit FD (0.5 to IMHz) can be applied as a clock signal to form a serial input type.

J of the first stage flip-flop F1 of this shift register
The output of the limiter amplifier AL is applied to the terminal, and the output of the amplification/limiter circuit described above is applied to the K terminal after being inverted by the inverter (2). When the output of AL is added to an exclusive OR circuit FOR and the output of this exclusive OR circuit is integrated by an integration circuit IL, the audio demodulation output of the sub-channel can be obtained.

In such an embodiment, as can be seen from the waveform diagram in FIG.
The first stage flip-flop F1 is an amplification/limiter circuit AL
Since it is inverted according to the output of the clock signal at the falling edge of the clock signal, the output of the flip-flop F1 is at the maximum rising edge and falling edge, compared to the output of the amplifying/limiter circuit AL. The signal C is delayed by the pulse width of .

Then, by applying this signal C and the original signal A to the exclusive OR circuit FOR, the signal shown in FIG. 52 is obtained as its output.

Therefore, if this signal 2 is integrated by the integrating circuit EIL, an audio detection output E corresponding to the density of the original FM signal can be obtained.

In addition, in this case, the limiter amplifier (amplification and limiter circuit AL
Since each rising and falling edge of the output signal is not in a fixed phase relationship with the clock signal port, the exclusive OR circuit FO
The pulse width of the output of R is the pulse width Tw of the above clock signal.
However, since this clock signal (approximately IMHz) is selected to be sufficiently higher than the FM input signal (31,5 KHz ± fH, fH: frequency of audio signal), such changes in pulse width can be detected. The effect on the output E is not that big of a problem.

However, in order to improve such effects and increase the detection output, one input of the exclusive OR circuit FOR is replaced with the output cover of the first-stage flip-flop F1, and the second-stage and subsequent flip-flops F2-- All you have to do is take one from F3.

At that time, a maximum time delay of Tw occurs per flip-flop stage, so the above exclusive OR circuit FOR
The maximum pulse width of the output is 2TW, 3Tw, and 4T, respectively.
w, and the detection efficiency improves as the output of the flip-flop in the subsequent stage is used, but the FM that can be detected increases accordingly.
It should be noted that the frequency of the signal becomes lower and therefore the frequency characteristics of the detection circuit deteriorate in that case.

In addition, as mentioned above, in the case of stereo broadcasting, the sub channel signal is set at the broadcasting station in advance by 20 μm with respect to the main channel signal.
This sub-channel signal is delayed by the band-pass filter circuit BPF so that it coincides with the main channel signal in time, but the band-pass filter circuit shown in FIG. Like HP
If the delay time (20 μs) is insufficient due to the use of F, the exclusive OR circuit F
If the two-man power of OR is taken from the subsequent flip-flops (for example, the outputs of F3 and F4), then the above delay time can be expressed as (n-1)Tw, where n is the number of flip-flops constituting the shift register SR. It can be compensated within the range of

That is, by setting n and Tw, a desired delay can be achieved.

More specifically, as shown in the figure, terminals AO to D are provided, and any two of these terminals (however, there must be at least one step between them) are installed. It is convenient if it is used as an input to the exclusive OR circuit FOR.

In the embodiment shown in FIG. 4, a serial input type shift register is constructed using JK flip-flops, but this shift register has a slight gap between its input and output (maximum n T w in the case of the above embodiment). Any other format may be used as long as it is configured to cause a time delay.

As mentioned above, the circuit of the present invention replaces the BPF for subchannel signal extraction and separation with an HPF and a shift register, and
Combined with the configuration in which the HPF is also used as an LPF for separating main channel signals, it is possible not only to reduce the number of components but also to greatly reduce the manufacturing and adjustment processes, and to improve the performance of the audio multiplex signal receiving circuit. It is possible to enjoy effects such as efficient IC implementation.

[Brief explanation of drawings]

FIG. 1 is an example of a conventional BPF with a trap. 2 to 5 all relate to the present invention; FIG. 2 is a main circuit block diagram, FIG. 3 is an embodiment of an HPF with a trap, FIG. 4 is an embodiment of an FM demodulation circuit, and FIG. FIG. 5 is an explanatory diagram of the operation. T-HPE...HPF with trap, HPF--HPF
FAl...limiter amplifier, SR...shift register, A5...exclusive OR circuit.

Claims (1)

[Claims] 1. FM modulates the sub channel signal and transmits FM to the main channel.
In an audio multiplex signal receiving circuit of M multiplexing method, the sub-channel signal is separated through an HPF (bypass filter), and a subsequent FM sub-splint channel signal input with a predetermined delay time C setting is input. An audio multiplex signal receiving circuit such as a TV receiver configured to use a shift register. 2. An audio multiplex signal receiving circuit for a TV receiver or the like according to claim 1, wherein the HPF is also used as an LPF (low pass filter) for main channel separation. 3. Among the flip-flop circuits that drive the shift register with a clock pulse having a sufficiently higher frequency than the FM carrier of the subcarrier and constitute the shift register,
An audio multiplex signal receiving circuit for a TV receiver or the like according to claim 1, configured to obtain an FM demodulated output by integrating exclusive OR outputs of at least one or more interstage outputs.