JPS581781B2 - mojishingohatseisouchi - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an improvement in an apparatus for generating character signals in the form of digital signals for displaying character patterns such as Chinese characters on a picture tube screen or the like. When characters, especially character patterns with many strokes such as kanji, are constructed using digital signals, in order to improve the quality of the characters, the dots (
It is necessary to increase the number of points) as much as possible. Conventionally, when increasing the number of dots that make up a character pattern in order to improve its definition, a digital computer is used to store a group of digital signals that make up the font of these character patterns so that they can be used repeatedly. The capacity of memory is increasing rapidly, and the equipment becomes extremely expensive due to the large memory capacity required.In addition, when these digital character signals are to be generated as television image signals, it is necessary to process these digital signals. However, the frequency of the clock pulse becomes extremely high, making it difficult to construct a signal processing circuit with the necessary performance. As mentioned above, in order to increase the definition of digitally displayed television images, when composing images by raster scanning such as interlaced scanning, scanning lines that are vertically adjacent to each other in the middle of each scanning line that displays image signals are used. It has been conventionally done to perform so-called scanning line interpolation by arranging scanning lines that display image signals formed by adding weights to the image signals displayed by the lines, but this is difficult for characters such as kanji that have many strokes. Although it depends on the size of the display screen, mere scanning line interpolation alone has not been able to sufficiently improve the definition. The purpose of the present invention is to solve the above-mentioned problems and improve the definition of character patterns such as kanji without increasing the frequency of the clock pulse used for configuring daily character signals. An object of the present invention is to provide an improved character signal generating device. Another object of the present invention is to provide an economical and improved character signal that increases the number of characters that can be stored without increasing the capacity of a digital memory for storing character pattern signals for forming character signals. The objective is to provide a generator. Still another object of the present invention is to provide an improved character signal generating device that increases the degree of freedom in configuring the character pattern signals stored in the memory and facilitates the configuration. That is, the character signal generating device of the present invention stores in a digital memory a required number of character pattern signals obtained by digitizing different character patterns, and generates the desired character pattern signals according to the display position on the display screen. In a character signal generating device, the character pattern signals are sequentially taken out from a memory and temporarily stored in a shift register, and the temporarily stored character pattern signals are repeatedly and sequentially reproduced from the shift register to display corresponding character patterns. , regarding the digital signal sequence constituting the digitized letter pattern signal, at least a predetermined plurality of consecutive "1" signals in at least the horizontal direction of the letter pattern, depending on the arrangement of the continuous "1" signals, The apparatus is characterized in that the number of consecutive "1" signals is reduced by at least one, and the signal is shifted for a period of time less than the unit digit time length so as to be reproduced from the shift register. . The present invention will be described in detail below with reference to the drawings. FIG. 1 shows an example in which a character pattern of a digital character signal generated by a conventional character signal generating device is composed of 8×8 bits, and FIG. 2 shows a schematic configuration of the conventional device. In the conventional device shown in FIG. 2, the required amount of character pattern signals configured in the same manner as in FIG.
The necessary character pattern signals are extracted according to the address 3 of the character to be generated to be displayed on the screen and the scanning line address 4 on the screen where the character is to be displayed, and each character pattern is constructed. The 8-bit digits are read in parallel into a shift register 2 and temporarily stored, and under the control of a clock pulse 5, each character pattern signal is taken out as an output line-sequentially as shown in the first figure while leaving an appropriate space. However, since the pattern of the character signal reproduced after being output from the shift register 2 has the same 8x8 dot configuration as the character pattern shown in Figure 1, the quality of the character pattern from the character signal generated by the conventional device is sufficient. I can't say that. On the other hand, in the device of the present invention, first of all, even if the character pattern stored in the digital memory is the same 8×8 bits, taking the same character as shown in FIG. 1 as an example, , constructed as shown in FIG. 5a. 5a and 5b show one of the principles of dot pattern generation in the character generator of the present invention in comparison with the conventional example shown in FIG. 1, and FIG. 5b shows the pattern of the character signal to be reproduced as an output from the shift register 2 in which it is temporarily stored. One of the principles of dot pattern generation in the device of the present invention is that, as shown in sequence in FIG. , 5th
Regarding the illustrated example, the definition is as follows. (1) The dot “1-1” connected to “0-1-1” and “0” is shifted by 0.5 dots and is one “1” dot located in the middle of “1-1” Express as. (2) “0-1-0” and “1” sandwiched between “0” on both sides
The dot is expressed as a "1" dot at the same position. (3) "...-1-1-1-..." and more than two consecutive "1"s are expressed as the same number of "1" dots in the same position, forming a continuous horizontal line. Putting the above together, a "1" dot that is flanked by "0" on both sides and is connected in more than one number will be a "1" dot that is connected in a position delayed by 0.5 dots in a number that is one less than the above number. , and the other "1" dots are expressed as they are in the same position. Above, one of the principles of dot pattern generation in the device of the present invention has been described in accordance with the example shown in Figure 3, but to generalize this further, it is possible to It is expressed as "1" (n-1) "1" dots that are connected more than a (n), and the other "1" dots are expressed as they are in the same position. According to one of the above principles of the present invention, for example, the conventional character pattern of 8×8 dots shown in FIG. 1 has substantially twice the number of dots in the horizontal direction, as shown in FIG. It becomes possible to express the character pattern as a 16×8 dot structure. FIG. 4 lists and shows examples of dot patterns that can be generated according to one of the dot pattern generation principles of the present invention shown in FIG. Examples of displaying dots are shown, and for b and e, 1 dot space is provided for each "0" dot, and for C, 1 and 5 dots are provided for each "0" dot. space, d is 2 for one “0” dot
Examples are shown in which a space for each dot is provided. Based on one of the principles of dot pattern generation in the device of the present invention as described above, a character pattern signal configured as described above is generated by processing a daisicle signal read out from a shift register in which a digital character pattern signal is temporarily stored. An example of the configuration of the logic circuit is shown in FIG. In FIG. 6, a three-stage flip-flop circuit corresponding to the three bits to perform the above-mentioned logical operation of the target bit and the upper and lower bits connected before and after the target bit in the readout portion of the shift register 2 is shown in FIG. Three AND gate circuits 7 are connected as shown below, and the respective outputs CC, A and C are obtained. The three input terminals of each A N D gate circuit 7 are respectively connected to either the Q output terminal or the Q output terminal of the three-stage flip-flop circuit. When the input signal is "1", "1" appears at these Q output terminals, and "1" appears at the Q output terminals when the input signal is "0", so if they are connected as shown in Figure 6, ,
Output CC becomes positive logic "1" when the above three bits are "1-1-1", and output A becomes "1" when the above three bits are "0-1-0".
”, the output C becomes “1” when it is “0-1-1”, and therefore corresponds to outputs (7), (2), and (3) of a 3-bit 8 code decoder (3-8 decoder), respectively. When any one of these outputs becomes a "1" signal, the true value of the target bit is "1", and otherwise it becomes "0". Therefore, in the device of the present invention, As mentioned above, in order to obtain a double-precision output by performing discrimination processing based on the combination of two consecutive bits in a digital alphabet pattern signal, the AND outputs of these are led to the OR circuit output and the C output, and then ORed. It is sufficient just to output the output.Next, in addition to the above-mentioned double precision in the horizontal direction of the character pattern according to the present invention, there is a case where running line interpolation is performed to further improve character quality using raster interlaced scanning. Fig. 7 shows the principle of the above-mentioned scanning line interpolation using interlaced scanning with an example of correction of diagonal lines in a character pattern.In other words, in Fig. 7, for odd fields, no logical operation is performed. The reproduced character pattern signal is output as is, but for even fields, the signal of scanning line l to be sent is compared with the signal of the next scanning line l+1, and the difference between the two is, for example, 0.5 dots. , the scanning line d-1-1 is shifted by ±0.25 dots as shown in the figure, and in case a kanji with many strokes has thin horizontal lines lined up at intervals.
When the signal is continuous dots, processing such as not performing the above-mentioned shift is performed. FIG. 8a shows the configuration of a logic circuit that performs the above-described scanning line interpolation shift. When performing scanning line interpolation on a character pattern, as can be seen from FIG. 7, the frequency of the clock pulse is doubled compared to the double precision operation shown in FIG. The processing shift register must also have two flip-flops for each dot of the character pattern to increase the degree of freedom and accuracy of signal processing. In the logic circuit for scanning line interpolation shown in FIG.
Shift register l1,l that temporarily stores the signal of l+1
Regarding the flip-flop circuit of two stages per dot and four stages per two dots as described above in each readout section of 2, a 3-bit 8 code decoder (3-8 decoder) 8 constructed in the same manner as shown in Fig. 4 is used. are connected to every three stages of the flip-flop circuit, and the AND output CC as shown in the fourth figure is obtained.
, A and C are determined by logical operations. As shown in FIG. 8b, these calculation outputs yield a positive logic "1" for any one of the clock pulses (A, B, C, D), so these shifted clock pulses An OR gate circuit 9 and an AND gate circuit 10 are connected in combination so as to gate (A, B, C, D), and the clock pulse of the gate output is used as a trigger to configure, for example, a one-shot 1 multi-byte break. The 1-dot width reproducing circuit 11 thus obtained is driven once to form a desired interpolation signal as shown in FIG. 4, and output signal 6. In the configuration example of the logic circuit shown in FIG. 8a, when stopping the logic operation of the odd field, the shift register l2 is loaded with a signal having the same content as l1.
The configuration of the signal processing circuit is simplified. Therefore, even if the structure lacks the above-mentioned portion for controlling the odd field, the purpose can be achieved. FIG. 9 shows the above-described double dot correction based on the principle of the present invention and its combination in order to increase the degree of freedom in creating a character pattern suitable for fully obtaining the effects of the character signal generating device of the present invention. An example will be shown in which, in addition to scanning line interpolation for matching, one dot at the left end of the letter pattern is used to add a control signal for erasing even fields. FIG. 9a shows a character pattern suitable for the device of the present invention configured similarly to FIG. 5a, at a desired position of the left margin.
This is an example in which an even field scanning erasing signal is added to the dots, and the interpolation signal is not displayed on the corresponding line of the even field in interlaced scanning. According to the character pattern signal having such a configuration, the character pattern signal shown in FIG. 5b reproduced from the character pattern signal of FIG.
No. 9, which has a pattern markedly different from that of
The character pattern shown in FIG. 2B can be reproduced from a substantially identical letter pattern to which an even field erasure signal is simply added, and the degree of freedom of the letter pattern increases accordingly. Incidentally, FIG. 9C shows an example of a reproduced character pattern when complete interpolation is performed by using the logic circuit of FIG. 8A by simultaneously using double precision and scanning line interpolation. As is clear from this example, in the device of the present invention, a character pattern signal having an 8×8 bit configuration similar to the conventional character pattern shown in FIG. , it is possible to reproduce a high-quality character pattern signal with far higher definition than in the past and use it as an output character signal, and when these patterns are compared, the effects obtained by the present invention are clear. . Regarding the scanning line interpolation of character patterns as described above, the calculation outputs (A), (B) and (C) in Fig. 8a are
, (D) are pulses with a width of 1 dot, and there is no need to change the pulse width.There is no need to use a high-speed clock pulse, which is expected to be about 40 MHz with double frequency etc. , as shown in FIG. 8b, signal processing is performed by sequentially delaying the clock pulse of the dot period, or alternatively, fixed delay circuits 12 such as delay lines and shift registers are connected in cascade, and each of them is processed. can reproduce the desired dot pattern even if the outputs (A, B, C, D) are supplied sequentially, and each calculation output (A, B, C, D) can be supplied with a delay amount 0.0.25
, 0.5 and 0.75 dot periods, respectively, to obtain a desired reproduction output signal. In order to realize one of the principles of dot pattern generation in the device of the present invention described above, it is preferable to use logic circuits having the configurations shown in FIGS. 6 and 8, but this is not limited to this example. Instead, for example, it is possible to combine delay circuits with various delay amounts, appropriately supply the required portion of the jimo pattern signal read from the shift register to these delay circuits, and self-control the delayed output signal at the appropriate timing. Many modifications can be made to the implementation of the principles of the invention, such as gating and synthesizing delayed and non-delayed portions of the letter pattern signal to form a character signal that constitutes a desired character pattern. Furthermore, the principle of character pattern generation in the present invention is not limited to what has been described in detail above; all character patterns are composed of a set of line segments, and each line segment is composed of a set of dots. When composing such a character pattern, each constituent dot should not be treated as representing a white or black point in its position, but should be treated as a set of multiple constituent dots, and each set should be represented within its respective constituent range. As long as information on the position and length of a line segment is indicated, various configurations can be adopted as the principle of character pattern generation in the present invention. Therefore, in order to improve the quality of characters expressed by dot patterns, it is important to have precision in the length and width of the line segments that make up such patterns. The inventor of the present invention has newly discovered that it is more important to precisely display the positions of the starting and ending points of the line segments constituting the pattern. As mentioned above, in the apparatus of the present invention, a plurality of dots constituting a character pattern are encoded as one set, and each set is given information on the position and length or width of the line segment to be represented within its constituent range. In embodying the principle of the present invention of specifying information, as described in detail above, for any three consecutive dots in a digital signal sequence representing a character pattern, the "1"
``Instead of instructing information on both the display position and the number of signals to be displayed, from the above-mentioned new perspective, only the display position information of the line segment to be expressed can be enhanced using multiple sets of character signal constituent dots. It is also possible to specify the accuracy.Another principle of character pattern generation in the present invention as described above will be explained with reference to FIGS. 12a and 12b.As shown in FIG. Two dots in the digital signal series represented by the digital signal sequence are sequentially set into one set.The information shown in FIG. ．．
0) →

[0], (0.1) → [1), (1,0) → (2
), (1.1) → [3], and these pieces of information are used as position information of the line segment. That is, based on the information of one set of two dots,

[0] is 2
Assuming that the white background for dots, [3] is the black line for 2 dots that is displayed in the same position, and [2] is to be displayed as it is, then
Compared to conventional character patterns in which each dot represents a white dot or a black dot at the same position, the shortest line segment that can be displayed is two dots, but the starting end of that line segment can occupy three different positions. You can use the position information displayed on the lines as follows:
This corresponds to expression using 3 dots, and the precision of position information will be increased by 1.5 times. Based on another one of the principles of the present invention described above, the configuration of a logic circuit for reproducing a digital signal of a letter pattern to form a character pattern signal can be as shown in FIG. 12, for example. That is, in FIG. 12, among the above-mentioned sets of two dot signals, the high-order bit signal and low-order bit signal of each set are divided into separate shift registers 2 and temporarily stored in sequence. (3) and (2) of the aforementioned composite output signals obtained from the decoder 13 are read out sequentially as a set.
), (1), and the signal [3] is delayed for a period of time and both are supplied to the OR gate circuit 14, and one of these gate input signals becomes a "1" signal at each timing. When this happens, an OR output 1 is formed and reproduced as a "1" signal for two dots and one dot starting at each timing. According to another principle of the present invention described above, by using such a simple logic circuit, line segments constituting a character pattern can be reproduced with higher accuracy in display position than in length or width. , it is possible to generate high-quality character signals. FIG. 13 shows an actual example of a character pattern constructed according to the principles of the invention described above. Figure 13a is an original drawing for creating a character pattern, and a required graph paper is placed on this to form a dot-structured character pattern, which is processed based on the principles of the present invention.
Figure 13b is a 36x32 dot character nocturne constructed using the conventional method so that each dot represents white or black, and Figure 13c is an 18x16 The same 3 6 X”'3 2 dot character pattern was recreated from the dot character pattern,
FIG. 13d illustrates a character pattern of 36×32 dots reproduced from a character pattern of 24×16 dots based on another principle of the present invention described later. As is clear from a comparison of these character patterns, in order to form these character patterns having approximately the same quality, it is sufficient to store them in the conventional digital memory shown in FIG. 13b. The principle of increasing the precision of character patterns in the present invention is not limited to the logical processing of double dots as in the example described above, but can also be applied to the logical processing of a large number of consecutive dots, and such logic The combination of dot signals reproduced by processing and the amount of shift are not limited to the above-mentioned example, and various combinations and shift amounts can be set. If the principles of the present invention are applied in an expanded manner, various improvements can be made regarding the generation of character signals, as described below. (1) By utilizing the increased space between lines and margins of a character pattern according to the principles of the present invention, a character formant is constructed in which control signals such as line segment position information and erasure information are inserted at appropriate locations. (2) The degree of freedom in creating a character pattern is increased by providing a plurality of pieces of deviation information for line segments that constitute a character pattern. (3) The fineness of the character pattern is increased only by the deviation information such as line segments as described above. (4) As described above, the reproduction pattern correction based on the combination of double dots is extended to the combination of three or more dots to improve the definition of multi-character strokes, diagonal lines, etc. (5) By allocating two or more dots to the line segment erasure control signal as shown in FIG. 9 and individually specifying odd and even lines, the degree of freedom in creating letter patterns is increased. (6) Improve the definition of diagonally shaded portions of character patterns by logical processing for correlations of three or more scanning lines. As is clear from the above description, according to the present invention, when character signals such as kanji characters are electronically digitized and configured, the capacity of the digital memory for storing the character pattern signals is not increased. Character signals capable of displaying high-quality character patterns can be generated without the need for high-speed processing of digital signals using particularly high-speed clock pulses, and in addition, the redundancy of character pattern information such as Kanji characters can be generated. Since we are using the jimo pattern (
There are almost no practical restrictions on the creation of fonts, and character patterns of any configuration can be easily obtained. Moreover, since the logic for character signal reproduction according to the present invention utilizes the correlation of character signals, the effect of improving the definition of character patterns is extremely large, and the circuit configuration for logic processing is simple and special. It does not include high-speed processing parts and is easy to implement. According to the present invention, as described above, it is possible not only to generate high-quality character pattern signals without increasing the capacity of the memory for storing character patterns or requiring high-speed processing of signals, but also to generate character pattern signals with the same level of quality as conventional ones. The number of character patterns that can be stored in the same memory capacity as before can be increased by simplifying the structure of the character pattern required to generate the character pattern signal, or
By increasing the degree of freedom in dot pattern deviation, arrangement, etc. and providing appropriate space, the number of characters that can be arranged on the display screen can be increased, or a high-resolution multi-character character pattern signal can be generated. You can also do that.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional character pattern, FIG. 2 is a block diagram showing a conventional character pattern signal generating device, and FIG. 3 is a diagram showing one of the principles of character pattern generation in the device of the present invention. Diagrams for explanation, Figures 4a to 4e are diagrams showing examples of character patterns generated by the device of the present invention, respectively, Figures 5a and b are examples of character patterns generated by the device of the present invention, and the character patterns thereof. Line sections showing examples of character patterns formed by reproducing patterns, No. 6
The figure is a block diagram showing an example of the configuration of a logic circuit for character pattern reproduction in the device of the present invention, FIG. 7 is a diagram for explaining the principle of scanning complementation in the device of the present invention, and FIGS. A block diagram and a waveform diagram respectively showing a configuration example of a logic circuit for reproducing a character pattern with scanning complementation and a waveform of a clock pulse. FIGS. 10 is a block diagram showing an example of the configuration of a circuit for forming sequentially delayed clock pulses in the device of the present invention, and FIG. 11 is a diagram showing another example of the principle of character pattern generation in the device of the present invention. FIG. 12 is a block diagram showing another configuration example of the logic circuit for reproducing a letter pattern in the device of the present invention; FIG. 13 is an explanatory diagram showing one example;
Figures a, b, c and d are diagrams respectively illustrating the original character pattern generated by the apparatus of the present invention and the reproduced diagram based on various principles. 1...Memory for storing character patterns, 2...
...Shift register, 3...Character address signal, 4...Scanning line address signal, 5...
...Clock pulse, 6...Output signal, 7.
...AND gate circuit, 8...3-bit 8 code decoder, 9...OR gate circuit, 10.
...AND gate circuit, 11...1 dot width reproduction circuit, 12...delay circuit, 13...
...Decoder, 14...OR gate circuit, DL
1, DL2...Delay line.

Claims (1)

[Claims] 1 A required number of digitized character pattern signals of different character patterns are stored in a digital memory, and the desired character pattern signals are sequentially retrieved from the memory according to the display position on the display screen and temporarily stored in a shift register. In the character signal generating device which stores the temporarily stored character pattern signals sequentially and repeatedly reproduces them sequentially from the shift register to display the respective corresponding character patterns on the display screen, the digitalized character pattern Regarding the daisicle signal series constituting the signal, at least a predetermined plurality of consecutive "1" signals in at least the horizontal direction of the letter pattern,
Depending on the manner in which these consecutive "1" signals are arranged, the number of consecutive "1" signals is reduced by at least one, and the number of consecutive "1" signals is shifted by a period of time less than the unit digit time length, and the shift register is A character signal generating device characterized in that the character signal generator is configured to reproduce data from.