JPS5818032B2 - Communication control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication control device that controls the transmission and reception of information between a large number of communication lines and a memory of a central processing unit or a buffer memory of the device itself using a storage program method.

Conventionally, this type of communication control device includes a line control section, a processing request interrupt generation section, a common control section, and the like.

The operation of such a communication control device is as follows.

For example, in the case of a call, the line control section sends out transmission information to the communication line one bit at a time, and when it is confirmed that one character has been sent out, the processing request interrupt generation section is activated to interrupt the common control section.

The common control unit prepares sending information using a program and sends the sending information to the line control unit.

In a communication control device using such a control method, in the processing of the common control unit at the time of an interrupt, the information sent to the line control includes information read from the central processing unit CPU and information created within the communication control device. There are two types of information (checksum, padding, etc.).

Therefore, in the program processing of the common control section, selection of transmission information, reading from the central processing unit CPU, and creation processing are necessary.

Therefore, the present invention is intended to improve the above-mentioned problems of the conventional technology, and its purpose is to reduce the load on the program of the communication control device and expand the processing capacity of the communication control device.

A feature of the present invention is that it has a sequence in which the sending character is read from the buffer memory of the central processing unit and processed, and a sequence in which the sending character is created and processed within the communication control device, and the two sequences are switched by the sequence control unit. The communication control device controls interrupts to the common control section.

Embodiments will be described below with reference to the drawings.

The accompanying drawing is a block diagram of the main parts of an embodiment of a communication control device according to the present invention.

In the diagram, there are multiple communication lines L1L2...
It is coupled to the central processing unit CPU via the communication control unit CCE.

1 is a line control unit that controls data transmission and reception with the line; 2
3 is a sequence control unit that determines the sequence for processing requests generated in the line control unit; 3 is a direct memory access DMA control unit that controls reading data from the central processing unit CPU; 4 is a sequence control unit that responds to requests controlled by the sequence control unit. An interrupt generating section 5 generates an interrupt, a common control section 5 performs predetermined processing on the interrupt, and a buffer 6 denotes a memory.

. Next, the detailed configuration of each part will be explained.

The line control section 1 includes an assemble buffer AB, a character buffer CB, and line request determination sections LR and Q.

The sequence control unit 2 includes a line number determination unit L OK, a sequence control execution unit SQO, and a processing execution line register ELN.
, an external storage control unit EMO, and an external storage EM.

The direct memory access control unit 3 includes a direct memory access execution unit DMAC1 memory address register M
Consists of AR and data register DTR.

The interrupt generating section 4 is composed of an interrupt request accepting section INTR, a sequence state storing section SQR, a line number storing section INR, and an interrupt address determining section IAD.

The common control section 5 is composed of a processing calculation PR and a main memory section MM.

These configurations are shown in FIG.

The line control section sends the data in the assemble buffer AB to the line one bit at a time in synchronization with the line speed.

When the last bit in AB is sent, the data to be sent next, which is set in advance in the character buffer OB, is transferred to A.
Move to B.

After the OB finishes transferring the transmission data to the AB, it issues a data request to the line request determination unit LRQ in order to retrieve the next data to be transmitted.

LRQ accepts requests from each line in order of priority,
Request processing to the sequence control unit along with the line number that accepted the request.

The line number determination unit LOK of the sequence control unit compares the received line number with the contents of the processing execution line register ELN that holds the line number currently being processed by the common control unit.
If it is determined that they are the same, the request to the sequence control execution unit SQO is temporarily suspended in order to prevent processing inconsistency due to conflict.

After that, when the processing of the common control unit is completed, or when it is determined that the received line number and the line number currently being processed by the common control unit are different, the sequence control execution unit SQC
Add a line number to the line and request processing.

The sequence control execution unit SQO passes the line number to the external storage control unit EMO and requests reading of information in the corresponding area of the external storage EM.

The external memory EM has a sequence state SQ for each line.

Buffer memory address M where transmission data is stored
A. Number of bytes of transmission data BC1 Area D for temporarily storing transmission data read from buffer memory
It has ATA.

The external storage control unit EMC is a sequence control execution unit sQc.
The sequence status SQ of the corresponding line area is read out in response to a request.

Sequence control execution unit SQO, when the read sequence state is a sequence for extracting transmission data from the buffer memory, successively reads buffer memory address MA and sets it in memory address register MAR of the direct memory access control unit, Direct memory access execution unit D reads out transmission data from the buffer memory.
Request MA0.

At the same time, the sequence control execution unit 8QO stores the sequence status in the sequence status storage unit SQR in the interrupt generation unit.
Set the line number in the line number storage LNR.

When the direct memory access execution unit DMA0 is requested to read the transmission data, the direct memory access execution unit DMA0 registers the memory address register MAR.
The contents of the buffer memory set in the buffer memory are read out and set in the data register DTR.

Then, the sequence control unit SQO is notified of the completion of reading the transmission data.

The sequence control unit SQO transfers the transmission data set in the data register DTR to the corresponding area DAT of the external storage BM.
A, and update the memory buffer addresses M and A and the number of transmitted bytes BO.

Further, the direct memory access executing unit DMA0 issues an interrupt request to the interrupt request accepting unit lNTR of the interrupt generating unit.

In the interrupt generation section, the interrupt request reception section lNTR receives a request from the direct memory access execution section DMA0, and the request is input to the interrupt address determination section IAD together with the contents of the sequence state storage section SQR.

The interrupt address determination unit IAD determines the address of the program to execute the entire process of setting the data read from the backup memory to the character buffer OB of the line control unit based on the request from the direct memory access execution unit DMA0 and the sequence status input. Then, it is set in the address register IA of the processing arithmetic unit PR in the common control unit, and interrupts the program.

The processing operation unit PR sequentially retrieves the instructions set in the address register IA from the main memory MM, executes the program, and transfers the contents of the transmission data DATA set in the external memory EM to the character buffer OB of the line control unit. At the same time, the sequence status for the next data request is set in the corresponding line area of the external storage EM of the sequence control unit.

Next, when the sequence execution unit SQO determines that the sequence status read from the external storage EM is in a status to transmit information created within the communication control device such as checksum and padding, the sequence execution unit SQO determines that the sequence status of the interrupt generation unit is Storage part S
The sequence state is set in QR, the line number is set in line number storage LNR, and an interrupt request is issued to interrupt request reception unit lNTR.

In the interrupt generation section, the interrupt request reception section lNTR receives a request from the sequence control execution section SQO, and the request is input to the interrupt address determination section IAD together with the contents of the sequence state storage section SQR.

The interrupt address determination unit IAD is connected to the sequence control execution unit SQO.
Create transmission data from the request and sequence state,
The address of the program that executes the process to set the character buffer OB of the line control unit in the common control unit.

It is set in the address register IA of the processing arithmetic unit PR and interrupts the program.

The processing arithmetic unit P'R sequentially retrieves instructions from the main memory device MM set in the address register IA, executes the program, creates data to be transmitted once, and sets the character buffer OBK of the line control unit. The sequence status for the next data request is stored in the external memory E of the sequence control unit.
Set in the corresponding line area of M.

Next, the operation of the communication control device according to the embodiment will be explained, taking as an example the case where data is sent to a communication line.

When the line control unit 1 sends data to the communication line, it requests the next data to be sent and starts the sequence control unit 2.

Here, when the processing line is in a state where the data in the buffer memory 6 is read out and sent out, the common control unit 2 specifies a sequence requesting the direct memory access control unit 3 in advance. 5 is specified by the program.

Therefore, when activated by the line control unit 1, the sequence control unit 2 activates the direct memory access control unit 3, reads predetermined information from the backup memory, and
Memory addresses, remaining character count counters, etc. are updated.

Next, the direct memory address control section 3 activates the interrupt generation section 4 to interrupt the program of the common control section 5.

At this time, the common control unit 5 performs predetermined processing such as changing the state and changing the sequence on the information read out from the buffer memory 6 by the direct memory access control unit 3, and also transfers the information to the line control unit 1. Transfer to.

On the other hand, the state of the processing line is changed to checksum, padding (
When you are in the state of transmitting information created in the communication control device, such as an extra character for timing,
It is assumed that the program of the common control section 5 specifies in advance a sequence in which the sequence control section 2 directly activates the interrupt generation section 4 without requesting the direct memory access control section.

In this case, when the sequence control section 2 is activated by the line control section 1, the sequence control section 2 directly activates the interrupt generation section 4 and interrupts the common control section 5.

The common control unit 5 performs predetermined processing such as creating information (checksum, padding, etc.) to be sent to the line by a program, and transfers the created information to the line control unit 1.

The structure of the sequence control section 2 and the direct memory access control section 3 is not limited to hardware based on wired logic, and it is also possible to control all or part of the circuits by a microprogram.

As explained above, when interrupting the common control unit, the selection and reading process of the information sent to the line is executed by hardware, which reduces the processing load of the interrupted program and reduces the processing load on the communication control unit. Processing capacity can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a communication control device according to the present invention, and FIG. 2 is a block diagram showing the detailed configuration of the device shown in FIG. LIL2~Ln...Communication circuit, CCE...
...Communication control device, CPU...Central processing unit,
1...Line control unit, 2...Sequence control unit, 3...Direct memory access DM
A control section, 4... Interrupt generation section, 5...
Common control unit, 6...Buffer memory, AB...
...Assemble buffer, CB...Character buffer, LRQ...Line request determination unit, L
OK...Line number determination section, SQC...
Sequence control execution unit, ELN...Process execution line register, EMC...External storage control unit, EM
...External memory, DMA0... Direct memory access execution unit, data register, lNTR.
...Interrupt request reception section, SQR...Sequence status storage section, LNR...Line number storage section,
IAD... Interrupt address determination section, PR,...
・Processed wave X MM... Main memory section.

Claims (1)

[Claims] 1 inserted between the central processing unit and multiple communication lines,
In a communication control device in which the total reception of data to and from the communication line is controlled character by character by a common control unit under program control, a sequence is established between the line control unit that controls the total reception of data to and from the line and the common control unit. A control unit is provided, and when notifying the common control unit of a character transmission request from the line control unit, a series of transmission data is stored when transmitting information instructed to be transmitted from the central processing unit. A sequence in which the transmission character is read from the backup memory in the central processing unit and notified to the common control unit, and when transmitting information created in the communication control unit, it is directly notified to the common control unit without going through the central processing unit. A communication control device comprising a sequence, and the two sequences are switched by the sequence control unit.