JPS5818646B2 - Data Densou System Hogohoushiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protection method for a data transmission system, and more particularly to a driver protection method for a bidirectional data transmission system in which a digital signal transmission driver is constructed of an LSI.

In a digital data control device such as a computer, a CPU (central processing unit) and an I10 device (peripheral device) are connected by a large number of signal transmission lines (data transmission lines).

For example, with a 16-bit CPU, there is 1
In addition to the 6-bit digital data signal, it is necessary to transmit and receive more than 20 types of control signals.

Increasing the number of transmission lines not only complicates the cables and connectors, but also makes the equipment more expensive and less reliable.

Therefore, it is known to make data bus signals and control bus signals bidirectional in order to reduce the number of transmission lines.

Where high speed is required for these bidirectional transmission signals, it is necessary to perform impedance matching between the signal driver and the transmission line.

Twisted pair wires and coaxial cables commonly used as transmission lines have an impedance of 30 to 150Ω, and the output impedance of the driver is also matched to this.

FIG. 1 is a schematic block diagram showing a portion of a digital data transmission system that is the background of the present invention.

In construction, this data transmission system performs, for example, 8-bit data transmission.

I10 device (sometimes this is a CPU) IODl.

■OD2. . . . l0Dn are connected to eight data transmission lines B1 . . . so that 8-bit digital data signals can be transmitted in both directions. B2. B3...s B
They are commonly connected by a bidirectional transmission bus including g.

These data buses and each I10 device l0D1゜■OD2.
. . . , l0Dn, there is a bus control unit BCD1. BCD2゜・・・・・・
・, BCDn is inserted.

The bus control unit BCD1 controls each transmission line B1.・・・・・・
・.

Receiver BR, □, ......, BR compatible with B8
18 and driver BD1□, . . . includes songs, BDs, and 8.

Similarly, the lotus control unit BCD2 is the receiver BR21,...
....

BR28 and driver BD21. ......, BD28
and the bus control unit B CD n is a receiver BRn1.
．． .......

B Rn s and driver BDn□,...+B
Including D n B.

Although not shown, control signal lines for transmitting various control signals are connected to the I10 devices OD1 to 10Dn.

In operation, consider a case where the transmission bus is transmitting 8-bit data in parallel in both directions.

At this time, the bus signal from the transmission bus is transmitted to each receiver BR.
1□~BR18, BR2, ~BR28t...

Received and amplified by B Rn 1 to B Rn g,
I10 equipment equipment ODI, I OD2, "" I O
Input signal to D n '5'11~i181 '21~'
28 s”°°”t int~ins.

Furthermore, ■10 devices l0D1゜■OD2.・・・・・・
, output signal from l0Dn 0□1~0 , O~0
......, On1 to On8 are Dora 18
21 28 Fiba BD, □~BD18. BD2□～BD28t...
....

BDn, .about.BDnB are added to the transmission bus.

I10 equipment l0Dt, I OD2-..."..., I
OD n is a bus control signal for selecting whether to send the output signal of a specific I10 device to the data bus based on a control signal from the control signal line (not shown).

c2. ..., one of cn is a high level signal (hereinafter referred to as "high level signal").

lower rHJ signal).

This high-level bus control signal c1. c2 or cn is the driver BD of the bus control unit BCD1, respectively.
1□～BD□8゜Driver BD2 of bus control unit BCD2
□~BD28 or bus control unit BCDn driver B
Dn1~.

Select and activate B D n B.

Therefore, I10 equipment ■OD1. ■OD2 or l0D
The output signals 011-018, 021-028 or Onl-On3 from the series of drivers BD1.n are activated as described above. ~BD18. BD2□~BD28 or BDnl.

~B D n B to the transmission bus.

The driver BD used in the above-mentioned bidirectional transmission system generally has a low output impedance for the reasons mentioned above.

If the input impedance of the receiver is high, the driver will receive a data bus signal from rHJ to rLJ or rL.
A large current flows only during the transient state when changing from J to rHJ.

However, if the transmission line is shorted due to a mistake during equipment assembly or adjustment or a defective mounted component, or if two or more drivers connected to a common transmission line operate simultaneously, the system will simply malfunction. Not only that, but the power consumption of a particular driver increases significantly, and in extreme cases, the driver may be damaged.

For example, one driver (LSI) operating at the same time is r
When the HJ signal is sent out and the other driver (LSI) sends out a low level (hereinafter referred to as rLJ signal), if both output impedances are 20Ω, a current of 125mA will flow between the 5■ power supply and ground, for example. become.

Therefore, each driver consumes 0.312W of power.

Therefore, if the data bus has 16 (bit) transmission lines, both of the two LSIs have 5W.
The power consumption is as follows.

Therefore, if these LSIs normally operate at 90°C, the LSI chips reach temperatures as high as 200°C.

If such high temperatures continue for a long time, the migration of the At wiring layer in the LSI will cause deterioration.
This causes a change in the threshold voltage of, for example, an IGFET that constitutes the driver.

Furthermore, since transmission lines are usually coaxial cables or twisted pair wires, there is a possibility of a short circuit with the ground.

In this way, in a bidirectional data transmission system, when an abnormality (defective) occurs in a certain part, it is desirable to prevent the previously normal part from being damaged due to this abnormality.

Therefore, a primary object of the present invention is to provide a data transmission system protection system that satisfies the above-mentioned special needs with a relatively simple configuration.

In summary, the present invention generally provides that data bus signals and bus control signals change synchronously using a transfer clock, and that bus control signals are commonly given to each driver of one bus control section. Focusing on the fact that A protection system for a data transmission system in which a common protection signal is derived as an abnormality and this protection signal is commonly given to each driver to prevent abnormal current from flowing to each driver. Figure 2 shows the principle of this invention. FIG. 2 is a schematic block diagram of a portion shown in FIG.

In configuration, this embodiment uses the first
It is almost the same as the figure.

That is, sensors 811 to S8 and 821 to 828 for detecting an abnormality in the respective drivers are individually associated with each bus control unit BCD and each driver BD1□ to BD18 and BD2□ to BD28 of BOD5. It will be established as follows.

The respective abnormality detection signals of the sensors 811 to 818 are commonly (logically) given as inputs to the protection signal generation circuit PS1.

This protection signal generation circuit PS1 includes sensors S1□ to 818
The circuit includes a signal generator P1 and a delay circuit DL1 that generate a protection signal in response to an abnormality detection signal being obtained from one of the following.

That is, the output signal from the signal generator P1 is used to determine whether this abnormal state continues for a certain period of time (for example, to confirm that there is no short-term abnormality due to a transient state of potential change of the data bus, external noise, reflection, etc.) ) is applied to the delay circuit DL.

The delay circuit DL1 output is output from each of the drivers BD1□ to BD.
Limiter Lll which is wedge-connected to 18 and installed in a similar manner
Commonly given to L18.

These limiters L1□~''18 are for preventing excessive current from flowing in the driver.

The abnormality detection signals of the sensors S21 to S828 are commonly given as human power to the protection signal generation circuit PS2.

This protection signal generation circuit PS2 includes a signal generator P2 and a delay circuit DL2.

The output of the delay circuit PL2 is output from each driver BD2□ to BD.
Limiter L2□~L provided individually in relation to 28
Commonly given to 28.

In operation, the bus control signal CI (D[Hj
It is assumed that the signal selects a series of drivers BD1, -BD18, and that the remaining drivers BD2□ -BD28, etc. are turned off.

At this time, output signals 011~ from I10 device IOD,
018'In fact, for example, even though driver BD1□ is configured to send out an "H" signal, this driver BD1. When an "H" signal is not obtained from the sensor S1, an abnormality detection signal is derived from the associated sensor S1□.

Therefore, the signal from the signal generator P1 is applied to the delay circuit DL and is delayed in time to generate a protection signal 'generating circuit PS1.
is derived as a protection signal from

Therefore, the limiters Lll to L18 are activated, the currents of the drivers BD1 to BD18 are limited, and the abnormal current of the driver BD11 that has caused the abnormality is accordingly reduced.

In this way all drivers can be protected.

A noteworthy feature of this invention is that the driver protection signal is commonly generated by taking advantage of the fact that a bus control signal is commonly given to a series of drivers (for example, BD1□ to BD1g) of each bus control unit. This is what I decided to do.

In this way, the circuit configuration is simpler than generating a protection signal for each driver.

This is even more effective in terms of the area occupied by the protection circuit when each circuit is constructed using an LSI.

FIG. 3 is an electrical circuit diagram showing essential parts of a preferred embodiment of the present invention.

In configuration, this circuit diagram shows only one bus controller BCD
Only shown.

Therefore, although not shown, the transmission line B1. B2. B3.・・・
....

Several other similar bus control units are connected to the data bus including G8, numbered as shown in FIG.

Moreover, although only BD and BD2 and their related circuits are shown among the drivers BD1 to BD8 of the bus control unit BCD, the other drivers BD3 to BD8 are similarly configured.

Furthermore, the FET used in the circuit of FIG. 3 is an N-channel enhancement type IG (In5ulated
Gate: Insulated gate type) FET, power supply voltage VDD = 5■, gate voltage VGG = 12 V,
Let Vth = 15V.

The configuration and operation of FIG. 3 will be explained below along with the waveform example diagram of FIG. 4.

I10 equipment or CP related to this bus control unit BCD
When the bus control signal C given via U is rHJ,
Either one of the NOR gate G1□ or G12 output ■1□ or ■1□ becomes rHJ.

Therefore, FETTIQ that constitutes a push-pull output circuit
Either TlO2 or TlO2 is turned on, and this driver BD1 is activated.

That is, the driver BD1 receives the corresponding bus control signal C.
is selected when rHJ, and acts as an output driver.

Here, as the other input of the NOR gate G12, the related I
When the output signal o1 from the No. 10 device (not shown) is rHJ, the NOR gate GH output V12 becomes "L" and N
OR gate G1, output ■□1 becomes rHJ.

Therefore, FBTTlol is turned on and TlO2 is turned off.

Therefore, the output of this driver BD1, that is, the corresponding transmission line B1 becomes rHJ.

Conversely, if the output signal is "L", the output Vll is "L".
", ■12 becomes rHJ, FET Tl0I turns off Tl
O2 is turned on and transmission line B1 becomes rLJ.

Further, if the bus control signal C is rLJ, the NOR gate G11. Both G12 outputs become “L” and the FE
Both TTl 01 and Tl 02 are in the off state.

Therefore, this driver BD1 becomes off-state,
This driver BD1 is in a disconnected state due to the equality constraint.

In this manner, the driver BD1 of the bus control unit BCD operates.

Note that the driver BD2 of this bus control unit BCD also operates in the same manner.

That is, FET T2O1. T2O2 is the push-pull output circuit, T2O6゜T2O7, T2O8 is the NOR gate G2□ (corresponding to the above G1□), T209,
T21(), T211 is the NOR gate G22 (the G,
(equivalent to 2).

As described above, if the bus control signal C is rHJ and the output signal o1 is rHJ, the transmission line B is 16fHJ.

Therefore, the FET T103, which works as the sensor S1, is off.

At this time, since the FET T1 (for pull-up) constituting the protection signal generator P is turned on by the gate voltage VGG, the signal a1 on its output line is rHJ.

Therefore, FET T2 forming the delay circuit DL is turned on, and the signal a2 is rLJ.

Therefore, the delay capacitor CD is not charged, FETTS remains off, and the turned on FE
The signal a3 on the output line of TT4 is rHJ.

That is, when the sensor S1 does not detect any abnormality, the two inputs of the NOR gate G, which together with the delay circuit DL constitute the protection signal generation circuit PS, are both at "H".
becomes.

Therefore, the output signal a4 of this NOR gate G becomes "L", the FET T105 constituting the limiter L1 remains off, and this limiter L1 does not work.

Here, when transmission line B1 should originally be rHJ, r
Let's assume that it is LJ.

This may occur, for example, when the transmission line B1 is short-circuited to the ground terminal, or when another driver (included in another bus control unit) connected to the transmission line B1 accidentally changes from the off state to rL.
This occurs when the situation becomes J.

At this point, the output ■1□ of the NOR gate G1□ is rHJ
Since the potential of the transmission line B1 becomes <"L" as shown in FIG. 4a, the FET T103 is turned on.

Therefore, as shown in Figure 4, the signal a1 (line) is
F'ETT2 is turned off in response.

Therefore, the delay capacitor CD starts to be charged, and after the elapse of time t1 (based on the capacitance of the capacitor CD), the signal a3 changes to "H" as shown in FIG. 4C.

Accordingly, at this timing, FETTS is turned on, so that the signal a3 becomes "L" as shown in FIG. 4d.

That is, when the sensor S1 detects an abnormality, the human power a1 on one side of the NOR gate G becomes "L", and after the elapse of time t1, the human power a2 on the other side becomes "H".

Here, the above-mentioned time t1 is set to prevent the device from operating in the event of a short-term abnormality as described above.

That is, even in a transient state where the potential of the transmission line B1 changes from "L" to rHJ, when the output V1 is rHJ and the transmission line B1 is "L", the signal a1 may become rLl.

Therefore, the signal a1 is delayed at least as long as this transient state continues.

The length of time this transient state lasts depends on the length of the data bus and the delay of the driver's control signal, and is typically up to 100 nm.
s~1 μS.

The output signal a4 of the NOR gate G is as shown in FIG.
After time t1 has passed since the occurrence of the abnormality, rHJ is determined.

Therefore, the FET T105 of the limiter L1 is turned on at this timing of input.

When the FET T105 is turned on, the potential of the output Vll of the NOR gate 401 approaches the potential of the transmission line B1 and decreases.

Therefore, the current flowing through FBTTlol is reduced.

Therefore, there is no abnormally excessive current, and power consumption does not increase.

Here, if there is no abnormality in the transmission line B1, the signal a
1 turns into "H".

Therefore, the output signal a3 of the delay circuit DL changes to rHl after a very short time t2 has elapsed from the timing of the return.

Therefore, NOR gate G output a4 is set to rLJ, and F
ETT 1035 is turned off.

At this time, an FBT is connected between the output ■1□ and FET T105.
FETT 104 is inserted and turned on to prevent Tlol from being completely cut off.

Therefore, when the abnormality in the transmission line B1 is removed, the potential of the transmission line B1 rises to rHJ (5■).

Therefore, the potential v1□ returns to the original rHJ (10V).

In order to do the above, the delay circuit DL increases the delay time t1 at the fall of the signal a1 when the abnormality is detected, and increases the delay time t1 at the rise of the signal a1 when the abnormality is removed. It is desirable to almost eliminate the time t2.

For this purpose, in FIG. 3, the charging time constant of the capacitor CD is increased and the discharging time constant is decreased.

If you try to form such a delay circuit DL in an LSI, it will include a capacitor and FET, and the protection signal a
4 occupies an area of approximately 0.06-.

Therefore, if each driver included in the bus control unit BCD is individually provided, a very large area will be required.

As a result, the degree of integration of the LSI decreases, and the yield rate also deteriorates, which is wasteful from a cost perspective.

Therefore, in the present invention, a protection signal generation circuit is commonly provided for a series of drivers ζ of one bus control section, thereby providing an effective data transmission system protection system when integrated into an LSI.

FIG. 5 is an electrical circuit diagram showing the main parts of another embodiment of the invention.

This embodiment is a circuit for the driver BD1 in the case where an abnormal current flows from the power supply to the output terminal of the push-pull output circuit of the driver BD1.

That is, NOR gates G1□, G12 and FET T10
6 and Tl 07 constitute a driver BD, and the FET
T108 and Tl 09 constitute the sensor S, and the FET
A protection signal generation circuit ps is configured by Tl, a delay circuit DL as shown in FIG. 3, and a NOR gate G, and the FET T
110.

T111 constitutes limiter L1.

Its operation method is similar to that of the embodiment shown in FIG. 3, and detailed explanation thereof will be omitted.

FIG. 6 is an electrical circuit diagram showing the main parts of another embodiment of the invention.

In configuration, this example uses a complementary MO8FET (C
MO8), FET T114, Tl
15, Tl 16°T117, T118. T11
9. T122 is an N-channel IGFET, FET T11
3, Tl 12.

Tl 13 , Tl 20 and Tl 21 are P-channel IGFETs.

Further, the driver BD is Tl 12 among the FETs.
, T113 , Tl 14 and FETT T119 configuring NOR gate G12 T120 , Tl 21
, T122.

Furthermore, FET T115 and T116 connect sensor S□,
FETT117. T118 constitutes limiter L1.

In addition, FET T1' is the signal generator P (for pull-up)
, delay circuit DL (similar to the one in Fig. 3) and NOR
Gate 1-G constitutes a protection signal generation circuit PS.

In operation, when the bus control signal C is "L", the FET
T119 is turned on, Tl2O is turned off, and its output voltage V12 becomes II, J.

Therefore, FET Tl constituting the push-pull output circuit
14 is turned off.

On the other hand, FET Tl 12 , T116 and T117
Since both are off, this driver BD is put into an off state.

Conversely, when the bus control signal C is rHJ, the FET Tl2O
is turned on, T112 is turned on, and T119 is turned off, and the driver BD is activated.

Therefore, if the output signal o1 is rHJ, the output voltage V12
becomes "L", FET Tl 13 is turned on, T114 is turned off, and the transmission line B1ζ becomes rH, which is the same as the output signal o1.
J is sent.

Also, if the output signal 01 is r L J, FET T12
1 is on and T122 is off, so the output voltage V1
2 becomes rHJ.

Therefore, if FET Tl 18 (of limiter L1) is off, FET T113 is off and T114 is on, and rLJ, which is the same as output signal o1, is sent to transmission line B1.

Here, the bus control signal C is rLJ, and the output signal o1
When is rLJ, FET T11 forming limiter L1
Even when B is turned on, compared to the on-resistance of FET T117,
If the sum of the on-resistances of FET Tl 20 and TI 21 is selected a little larger, the output V12 will logically be rHJ.
I can think of it as.

Therefore, the FET T113 is turned off, the FET T114 is turned on, and the transmission line B1 becomes "L".

Normally, FET Tl 15 that constitutes sensor S1 is off,
T116 is on.

Therefore, signal a1 becomes rHJ, signal a4 becomes rLJ,
FET T118, which constitutes limiter L1, is off.

If an abnormality occurs and the transmission line B1 becomes rHJ, the FETT 115 of the sensor S1 is turned on.

Therefore, the signal a1 becomes II, J.

Therefore, the output signal a4 of the NOR gate 1-G of the protection signal generation circuit PS becomes rHJ, and the FET of the limiter L1
118 is turned on.

Accordingly, the potential of the output V12 decreases. At this time, FET
Although Tl 14 remains on, its on-resistance increases and the current through this FET T114 decreases.

Therefore, the power consumption in this driver BD is reduced, so that damage due to heat generation etc. can be avoided.

Also, if the abnormality in transmission line B1 is resolved, this driver B
As described above, D returns as an output driver.

In addition, in the above-mentioned embodiment, enhancement type I
Although we have explained about GFET, this also applies to other semiconductor devices (
Of course, transistors (including bipolar transistors) may also be used.

As described above, according to the present invention, an abnormality in a data transmission bus can be detected and power consumption of an output driver can be reduced.

Furthermore, a common protection signal is generated based on a common bus control signal and an abnormality detection signal from each driver, and the current of each driver is commonly limited by a signal that is delayed for a certain period of time. It is possible to protect each driver from malfunctioning due to short-term abnormalities caused by transient conditions or noise, and it is effective in making each driver an LSI.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram showing a portion of a digital data transmission system that is the background of the present invention. FIG. 2 is a partial schematic block diagram showing the principle of this invention. FIG. 3 is an electrical circuit diagram showing essential parts of a preferred embodiment of the present invention. FIG. 4 is an example diagram of signal waveforms of various parts in this embodiment. FIG. 5 is an electrical circuit diagram showing the main parts of another embodiment of the invention. FIG. 6 is an electrical circuit diagram showing the main parts of another embodiment of the invention. In the figures, the same reference numerals indicate the same or corresponding parts, B1. B2.・・・・・・B8 is transmission line, IOD
is I10 device, BCD is bus control unit, BR is receiver 1
3D is driver, S is sensor, P is protection signal generator, D
L indicates a delay circuit, L indicates a limiter, 1 indicates an input signal, 0 indicates an output signal, and C indicates a bus control signal.

Claims (1)

[Scope of Claims] 1. A digital data transmission bus including a plurality of transmission lines, a data control device, and a digital data transmission bus interposed between the data transmission bus and the data control device and corresponding to the plurality of transmission lines. A protection method for a data transmission system including a bus control section having a plurality of output drivers arranged therein, wherein the bus control section is based on a bus control signal given from the data control device and the state of each transmission line. protection signal generation means for commonly generating a protection signal for each of the output drivers; delay means for delaying the common protection signal for a certain period of time; A protection method for a data transmission system comprising current limiting means for controlling the current to decrease.