JPS5818781B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5818781B2 JPS5818781B2 JP55171783A JP17178380A JPS5818781B2 JP S5818781 B2 JPS5818781 B2 JP S5818781B2 JP 55171783 A JP55171783 A JP 55171783A JP 17178380 A JP17178380 A JP 17178380A JP S5818781 B2 JPS5818781 B2 JP S5818781B2
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- monitor element
- terminal
- chip
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置特にモニタ素子を内蔵した集積回
路チップに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly an integrated circuit chip incorporating a monitor element.
集積回路を構成する素子の特性を破壊的又は非破壊的に
測定してその測定データを製造工程へ帰還しまた保守点
検の用に供するために、チップ内にモニタ素子を作り付
けしておくことが行なわれている。In order to destructively or non-destructively measure the characteristics of the elements that make up an integrated circuit and return the measured data to the manufacturing process and for maintenance and inspection purposes, it is possible to incorporate a monitor element into the chip. It is being done.
例えば実稼動トランジスタと同じ工程でモニタ用トラン
ジスタを製造しておけば、該モニタ用トランジスタの特
性を測定することにより実稼動トランジスタの特性を推
定することができ、この方法なら破壊試験も可能である
。For example, if a monitor transistor is manufactured in the same process as the actual transistor, the characteristics of the actual transistor can be estimated by measuring the characteristics of the monitor transistor, and destructive testing is also possible using this method. .
ところで既知のように集積回路ではピン数つまり外部端
子数が制限され、モニタ素子にピンを専有させることは
避けたい所である。By the way, as is known, in an integrated circuit, the number of pins, that is, the number of external terminals is limited, and it is desirable to avoid having the monitor element exclusively use the pins.
一方、集積回路には大電流用アース端子とは別に小電流
用アース端子を設けるなど同電位の外部端子を複数個設
けたものが有る。On the other hand, some integrated circuits are provided with a plurality of external terminals of the same potential, such as a small current ground terminal separate from a large current ground terminal.
このような集積回路では、実装後は該複数の外部端子は
配線により短絡されるが、それ迄は該端子は相互に独立
している。In such an integrated circuit, after mounting, the plurality of external terminals are short-circuited by wiring, but until then, the terminals are independent from each other.
従ってこれらの端子間にモニタ素子を接続しておけば、
専用端子またはピンを使用しないで該モニタ素子の特性
をチェックすることができる。Therefore, if a monitor element is connected between these terminals,
The characteristics of the monitor element can be checked without using dedicated terminals or pins.
本発明はか\る点に着目してなされたもので、特徴とす
る所は集積回路が構成された半導体チップの配線前は実
質的に絶縁され、配線後は同一電位にされる端子間に、
該チップに形成されそして該集積回路の特性を知る因子
を提供するモニタ素子を接続してなることにある。The present invention has been made with attention to this point, and is characterized by the fact that before wiring of a semiconductor chip in which an integrated circuit is constructed, there is substantially insulation, and after wiring, between terminals that are brought to the same potential. ,
A monitor element is formed on the chip and connected thereto to provide a factor to know the characteristics of the integrated circuit.
以下図面を参照しながらこれを詳細に説明する。This will be explained in detail below with reference to the drawings.
第1図で10は半導体チップで、周知のプロセスにより
電子回路が構成される。In FIG. 1, 10 is a semiconductor chip, and an electronic circuit is constructed by a well-known process.
本例ではこの電子回路12は演算増幅器とし、そのシン
ボルで示されている。In this example, this electronic circuit 12 is an operational amplifier and is indicated by its symbol.
14,16は演算増幅器の人、出力端、18は電源端子
である。14 and 16 are operational amplifier output terminals, and 18 is a power supply terminal.
22,24,26は該増幅器の入出力とグランドとを接
続する抵抗であり、28.32はグランド用の端子また
はボンデングパッドである。22, 24, and 26 are resistors that connect the input/output of the amplifier to the ground, and 28 and 32 are ground terminals or bonding pads.
グランド端子28.32は共にアースされるのであるか
ら共用することにより一方のみとしても原理的には支障
ないが、入力信号回路と出力段電源回路のように、流れ
る電流に大きな差がある場合は大電流側の影響を小電流
側が受ける、例えば端子32をやめて出力回路のグラン
ド配線も端子28を利用するようにすると、集積回路内
の配線は一般にアルミニウム蒸着膜であって抵抗がある
ので帰還がかXつたりして好ましくない。Since the ground terminals 28 and 32 are both grounded, there is no problem in principle if only one of them is used, but if there is a large difference in the current flowing, such as in the input signal circuit and the output stage power supply circuit, If the small current side is affected by the large current side, for example, if you remove the terminal 32 and use the terminal 28 for the ground wiring of the output circuit, the wiring in the integrated circuit is generally made of an aluminum evaporated film and has resistance, so feedback will not occur. I don't like it because it's bad.
そこで図示の如く大電流用グランド端子32と小電流用
グランド端子28は別にし、外部配線で、例えば大電流
用グランド端子32を導体ステージ20へ配線34によ
り接続し、集積回路パッケージのアース用ピンに至る配
線36をステージ20と小電流用端子28に接続すると
いう方法をとる。Therefore, as shown in the figure, the ground terminal 32 for large current and the ground terminal 28 for small current are separated, and the ground terminal 32 for large current is connected to the conductor stage 20 by an external wiring 34, and the ground terminal 32 for large current is connected to the conductor stage 20 by a wiring 34. A method is adopted in which the wiring 36 leading to the stage 20 and the small current terminal 28 are connected.
このようにすればステージ20の電気抵抗は小さいので
帰還がか5るようなことはない0
このような集積回路ではウェーハエ程の段階つまりチッ
プ10をスクライブする前の段階では勿論チップ10が
ステージに取付けられることはなく、端子28と32は
はマ絶縁状態にある。If this is done, the electric resistance of the stage 20 is small, so feedback will not be affected. In such an integrated circuit, the chip 10 is of course placed on the stage at the wafer stage, that is, before the chip 10 is scribed. It is not attached and terminals 28 and 32 are insulated.
本発明はか\る、実装後は同一電位になって1端子と実
質的に同一になるが実装前の段階では分離されている2
端子を利用し該端子に、チップ内に作り込んだモニタ素
子30を接続する。According to the present invention, two terminals have the same potential after mounting and are substantially the same as one terminal, but are separated before mounting.
A monitor element 30 built into the chip is connected to the terminal using the terminal.
第2図はモニタ素子の例を示すもので、aはピンチ抵抗
、bはMOS)ランジスタである。FIG. 2 shows an example of a monitor element, in which a is a pinch resistor and b is a MOS transistor.
ピンチ抵抗30aはバイポーラトランジスタの不純物拡
散工程で一緒に作られ、この抵抗値は該トランジスタの
hFEの指針となる。The pinch resistor 30a is created together with the bipolar transistor in the impurity diffusion process, and its resistance value serves as a guideline for the hFE of the transistor.
従ってウェーハエ程で端子28゜32に探針を轟て電圧
を加えて抵抗値を測定することによりチップ内電子回路
のトランジスタのhFEを推定し、異常があれば直ちに
それを製造工程へフィードバックすることができる。Therefore, during the wafer processing, the hFE of the transistor in the electronic circuit within the chip is estimated by applying a voltage to the terminal 28° 32 and measuring the resistance value, and if there is an abnormality, it is immediately fed back to the manufacturing process. Can be done.
bのMOSトランジスタ30bはゲートソースを短絡し
てダイオード接続し、端子28.32間に電流が流れる
ようになる電圧を知ってMO8I−ランジスタの重要な
パラメータである閾値(vth)を求めるモニタ素子で
ある。MOS transistor 30b is a monitor element whose gate and source are short-circuited and diode-connected, and which determines the threshold value (vth), which is an important parameter of the MO8I transistor, by knowing the voltage at which current flows between terminals 28 and 32. be.
このモニタ素子も勿論チップ内実稼動素子と同じ製造工
程で製造しておく。Of course, this monitor element is also manufactured in the same manufacturing process as the actual operating elements in the chip.
モニタ素子によるhFE、Vthの測定後は、チップス
クライブ、ICパッケージへの実装が行なわれ、第1図
で述べたように端子28.32は短絡されるのでモニタ
素子30は無いのと同様になる。After hFE and Vth are measured by the monitor element, the chip is scribed and mounted on the IC package, and as described in FIG. .
実装後もモニタ素子を測定してIC素子の特性推定を行
なうには端子28.32をICパッケージの異なるピン
に配線しておけばよい。In order to measure the monitor element and estimate the characteristics of the IC element even after mounting, the terminals 28 and 32 may be wired to different pins of the IC package.
このようにしておけば、該ICをソケットなどから外し
て上記ピン間の測定を行ない、IC素子特性の経年変化
などを推定することができる。In this way, it is possible to remove the IC from the socket or the like and measure the distance between the pins, thereby estimating changes in IC element characteristics over time.
この場合はピンが1つ余分に必要になるが、グランドピ
ン2個という市販ICもあり、このようなものに適用す
ればよい。In this case, one extra pin is required, but there are commercially available ICs that have two ground pins, and this can be applied to such ICs.
利用する端子又はピンとしては、グランド用の他に電源
用など、使用状態では短絡される複数端子を用いること
ができる。As the terminals or pins used, in addition to ground terminals, a plurality of terminals such as power supply terminals, which are short-circuited when in use, can be used.
以上説明したように本発明によれば端子ピンを増加せず
にモニタ素子をチップに内蔵でき甚だ有効である。As explained above, according to the present invention, a monitor element can be built into a chip without increasing the number of terminal pins, which is extremely effective.
第1図および第2図は本発明の実施例を示す回路図であ
る。
図面で10は半導体チップ、28.32は同一電位とな
る端子、30はモニタ素子である。1 and 2 are circuit diagrams showing an embodiment of the present invention. In the drawing, 10 is a semiconductor chip, 28 and 32 are terminals having the same potential, and 30 is a monitor element.
Claims (1)
的に絶縁され、配線後は同一電位にされる端子間に、該
チップに形成されそして該集積回路の特性を知る因子を
提供するモニタ素子を接続してなることを特徴とする半
導体装置。1. A monitor element that is formed on a semiconductor chip on which an integrated circuit is formed between terminals that are substantially insulated before wiring and that are held at the same potential after wiring, and that provides a factor for knowing the characteristics of the integrated circuit. A semiconductor device characterized by being formed by connecting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55171783A JPS5818781B2 (en) | 1980-12-05 | 1980-12-05 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55171783A JPS5818781B2 (en) | 1980-12-05 | 1980-12-05 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5795646A JPS5795646A (en) | 1982-06-14 |
| JPS5818781B2 true JPS5818781B2 (en) | 1983-04-14 |
Family
ID=15929595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55171783A Expired - Lifetime JPS5818781B2 (en) | 1980-12-05 | 1980-12-05 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5818781B2 (en) |
-
1980
- 1980-12-05 JP JP55171783A patent/JPS5818781B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5795646A (en) | 1982-06-14 |
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