JPS5818825B2 - vertical deflection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical deflection circuit that can be used in a television receiver.

A conventionally used vertical deflection circuit is shown in Fig. 1.
The waveforms at each point in the figure are shown in FIG.

In FIG. 1, 1 is a switching transistor, the vertical oscillation output pulse shown in FIG. Due to the charging/discharging circuit, a sawtooth voltage waveform shown in FIG. 2 appears at point b.

By changing the resistance value of the variable resistor 2, the amplitude of the sawtooth plate is changed to set the vertical amplitude of the screen.

Block 4 is a linearity adjustment circuit that adjusts the vertical linearity of the screen by a signal appearing at negative feedback resistor 5.

6 is a drive stage input coupling capacitor, which smoothes the negative feedback pulse signal supplied from the output stage midpoint voltage stabilizing transistor 7, generates a DC potential across the capacitor 60, and controls the base voltage of the drive transistor 8. This stabilizes the voltage at the midpoint (point d) of the output stage.

A voltage waveform as shown in FIG. 2C is applied to the base of the drive transistor 8.

9 is its emitter resistance, 10 is its collector resistance, 11.1
2 is a diode that compensates the base-emitter threshold voltage of the output transistors 13 and 14.

At point d, which is the midpoint of the output stage, an output waveform as shown by the solid line in FIG. 2d appears.

15 improves the efficiency of the vertical deflection circuit by switching the power supply voltage of the drive stage and output stage to the circuit power supply voltage ■8 during the scanning period, and to 2■B, which is twice the circuit power supply voltage during the retrace period. This is a switch circuit to prevent this from happening.

As a result, the output has a voltage waveform as shown in FIG. 2d.

16 is an output coupling capacitor, and 17 is a vertical deflection coil.

As described above, the transistor 7 is an output stage midpoint voltage stabilizing transistor, the base voltage of which is determined by the resistors 18 and 19, and operates only during the retrace period.

The resistor 20 and the 2L capacitor 22 constitute a filter circuit, and the average voltage of the voltage waveform at point d is at point f, as shown by the chain line in FIG. 2d.

appears. At the emitter 0 point of the transistor 7, a second
As shown in Figure e, a voltage waveform appears in which the voltage waveform at point f and the voltage waveform at point d are divided by resistors 20 and 21.

The operation of transistor 7 will be briefly explained.

When the DC level of the output stage midpoint voltage changes, the DC potential at point f, which is the average value, changes accordingly.

changes. Since the peak value of the retrace pulse of the waveform at point d is 2VB and constant, as shown in Figure 2 d, the peak value Vep of the waveform shown in Figure 2 e changes according to changes in vo. .

Transistor 7 operates in response to this change in Vep, and a control signal is applied to the base circuit of transistor 8.

This control signal is a pulse signal only during the blanking period, and as mentioned above, it is converted into a DC signal by the circuit of the coupling capacitor 6 and resistor 23 connected to the input circuit of the drive stage, and the average voltage value at point d is The base bias of transistor 8 is controlled to be constant.

The capacitor 6 is charged by the pulse output signal of the transistor 7 during the retrace period, and is discharged during the scanning period, but if the discharge time constant is made sufficiently larger than the scanning period, the capacitor 6 is converted to a DC signal.

Now, the problem here is first the amplitude change of the voltage waveform appearing at the output point d during the scanning period due to a change in the ambient temperature.

The series equivalent resistance changes as the copper loss of the vertical deflection coil 17 changes with temperature.

In this case, the deflection current flowing through the vertical deflection coil 17 is controlled to be constant by the negative feedback signal appearing at both ends of the vertical deflection coil 17 and the series resistor 5, so that when the equal series resistance of the vertical deflection coil 17 changes, , the amplitude of the voltage waveform appearing at point d changes.

d due to variations in the deflection efficiency of the vertical deflection coil 17.
Temperature change variations in the output stage midpoint voltage occur due to variations in the amplitude of the voltage waveform appearing at the points, and the following problems occur.

FIG. 3 shows how the output stage midpoint voltage changes and the operating time of the output transistor changes when the amplitude of the output waveform changes.

Figure 3A shows the output waveform at point d, with level V.

This output voltage waveform is connected to resistors 20, 21 and capacitor 22.
is the average value of the output voltage waveform obtained through the filter circuit.

Level v1 is the potential at the midpoint of the output stage when the operation of the output transistor 13 is switched, and the operation period T1 of the output transistor 13 and the operation period T of the other output transistor 14 are
2 are equal, and the collector loss and operating area of both output transistors are set to be equal.

Level■. The difference between and (1) is due to the retrace pulse, which is higher than (1) by the average voltage obtained by integrating the pulse waveform of the retrace period Tr.

With the circuit system shown in Figure 1, ■ is always the case.

Level V1 is controlled so that V1 remains constant.

Expressed in equation 1, it is as follows: ◯, and the DC level of the output voltage is controlled so that vo is always constant.

Next, consider the case where the amplitude becomes large.

Now, assuming that the level v1 does not change even when the amplitude increases, the output voltage waveform will be as shown in FIG. 3B.

■ in Figure 3B.

' is the average value of the output stage voltage waveform when the amplitude becomes large, and vo'>vo.

This is because when the amplitude increases, the retrace period T Bi becomes longer than the retrace period Tr when the amplitude is small, and the average voltage obtained by integrating the pulse waveform of the retrace period becomes higher than in the case of Figure 3A. It's for a reason.

FIG. 3B is an output voltage waveform diagram when the level ■1 is controlled to be constant, but in the case of the circuit of FIG. 1, the average voltage level ■ of the output voltage waveform.

Since it is controlled so that it is constant, the actual result is as shown in FIG. 3C.

That is, V in FIG. 3A.

and V in Figure 3C. level v1 so that they are at the same level
is controlled and becomes 11.

■1' Luher is v. Unless it is controlled so that '-v,=vo-v,', ■1' becomes lower than the level of ■1 in FIG. 3B.

As a result, the operating period T1 of one output transistor 13
' and the operating period T2' of the other output transistor 14 are no longer equal, T1'<T2', and the transistor 1
The core loss of transistor 4 becomes unbalanced and transistor 1
The collector loss is larger than the collector loss of No. 3, and a dimension problem arises especially in IC design, requiring a large area.

Furthermore, the operating region becomes unbalanced, and the operation of the transistor 14 becomes saturated at the end of the scan, as shown in FIG. 3C.
This causes an inconvenience in that the linearity at the bottom of the screen deteriorates.

The present invention eliminates the above-mentioned drawbacks, and one embodiment of the present invention will be described below with reference to the drawings.

An example of the circuit of the present invention is shown in FIG. 4, and the same parts as in FIG. 1 are given the same numbers and will be explained.

Block 24 is a waveform shaping circuit that extracts only the retrace pulse from the output voltage waveform and creates a pulse waveform. Block 25 removes the retrace pulse from the output voltage waveform, and as shown in FIG. Retrace pulse removal circuit, resistor 26, capacitor 2 to make the value close to the level
7 is a circuit that rectifies the voltage waveform at point f, and its output signal is at the voltage level 2 shown in Figure 5g.

, and the value almost matches the level of vl, as can be seen from FIG. 5d and f.

Bu. Lock 2B is a waveform synthesis circuit that uses a pulse signal with a constant peak value and a signal at point h as input signals to generate the voltage waveform shown in Figure 5g. It is meant to fluctuate.

When the output signal of block 28 is applied to the circuit of transistor 7 functioning as a voltage comparator, an operation substantially similar to that shown in FIG. 1 is performed, and the midpoint voltage of the output stage is stabilized.

Unlike the case shown in Fig. 1, this circuit configuration has a unique feature.

The point is the average value of the output voltage waveform■.

This almost coincides with the voltage level ■1 at the midpoint of the output stage when the operation of the output transistor changes, and as mentioned above, V generated by the retrace pulse of the output voltage waveform.

The negative effects caused by the level difference between and ■1 are eliminated,
Even if the amplitude changes, the operation period of the output transistor T1. T
2 can always be kept in the same period, the imbalance of collector loss is eliminated, and especially IIC argument paralysis can be economically traded, and if the linearity deteriorates, it will never occur.

A specific example of this circuit configuration is shown in FIG.

Corresponding to FIG. 4, block 24 in FIG. 4 is the circuit of the transistor 29, and block 25 is the circuit of the transistor 30.
circuit, block 28 is transistor 31, 32, 33
This is the circuit.

Next, the operation will be explained.

The transistor 29 is turned on by the retrace pulse of the output voltage waveform at point d, and turned off during the scanning period.

Only a retrace pulse appears at the output of transistor 29, and this pulse turns on transistors 30, 32, and 33, resulting in saturation.

At this time, the signal at point d is divided by resistors 34 and 35, and by selecting appropriate resistance values for resistors 34 and 35, the voltage waveform at point f becomes the waveform shown in FIG. 5f.

This waveform at point f is smoothed with a resistor 36 and a capacitor 37,
DC level ■ at point h.

A DC signal appears. Transistor 3
Add to the emitter follower circuit of 1.

Next, due to the operation of the retransistors 32 and 330, a pulse signal appears at the collector of the transistor 33, the peak value of which is approximately VB, and which has the time width of the retrace period.

This pulse signal is divided by resistors 20 and 21 based on the DC signal appearing at the emitter of transistor 31, and g
As shown in Figure 5g, the DC level is at the point ■.

A voltage waveform appears in which a pulse signal having a peak value Vep is superimposed on a DC signal.

Since VB is constant, this peak value VepO value is vo
changes according to changes in

When this signal is applied to the transistor 7, the output stage midpoint voltage can be stabilized so that even if the amplitude changes as described above, the period during which the output transistor operates is always the same.

FIG. 7 shows another embodiment of the present invention.

In FIG. 7, the difference from FIG. 6 is that the transistor 33
Everything else is exactly the same except for the pulse added to .

The vertical oscillation output pulse applied to transistor 1 is applied to transistor 38, and transistors 32 and 33 in FIG.
Similarly, transistors 33 and 38 are operated by vertical oscillation output pulses, and the output pulses are superimposed on the DC signal of the emitter output of transistor 31 and applied to the circuit of transistor 7.

The following operations are exactly the same as in FIG.

With the circuit configuration as described above, the output transistor can operate satisfactorily as described above.

- As described above, according to the present invention, the average value of the output voltage waveform of the vertical deflection circuit almost matches the voltage level at the midpoint of the output stage when the operation of the output transistor is switched;
This eliminates the negative effects caused by the voltage difference between the average value and the midpoint of the output stage caused by the retrace pulse of the output voltage waveform, and the operating period of the output transistor can be kept constant even if the amplitude changes. , the unbalance of the collector loss of the output transistor is eliminated, and the linearity is also good, making it particularly suitable for IC implementation.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional vertical deflection circuit, Figure 2 a, b,
c, d, e are waveform diagrams of each part of the circuit in Fig. 1, Fig. 3 A, B
, C is a waveform diagram of each part of the circuit in FIG. 1, FIG. 4 is a circuit diagram of a vertical deflection circuit in an embodiment of the present invention, and FIG. 5 d, f2
g is a waveform diagram of each part of the circuit of FIG. 4, FIG. 6 is a specific circuit diagram of the circuit of FIG. 4, and FIG. 7 is a specific circuit diagram of the circuit in the same embodiment. 1...Transistor, 1490100. Transistor, 17... Vertical deflection coil, 29...
...Transistor, 31...Transistor, 3
2...Transistor, 34...Resistor,
35...Resistance.

Claims (1)

[Scope of Claims] 1. A means for generating a sawtooth wave voltage based on the output of the switching element, comprising a switching element, an integrating circuit composed of a resistor and a capacitor, and the sawtooth wave voltage is supplied through a coupling capacitor. an output stage consisting of a first and second transistor directly connected to this drive stage, a vertical deflection coil connected to the midpoint of this output stage, and a retrace line from the vertical deflection output signal. A waveform shaping circuit for removing pulses, a circuit for rectifying and smoothing the output signal of this waveform shaping circuit, and a synthesizing circuit for superimposing a pulse signal with a constant peak value on the output DC voltage of this rectifying and smoothing circuit are provided. The output of the combining circuit is applied to one input terminal of a voltage comparator having two input terminals, a reference voltage is applied to the other input terminal of the voltage comparator, and the output of the voltage comparator is connected to the coupling capacitor. Vertical deflection circuit applied to the coupling point of the drive stage. 2. The vertical deflection circuit according to claim 1, wherein a pulse signal obtained from a vertical oscillation output pulse is used as the pulse signal having a constant peak value. 3. The vertical deflection circuit according to claim 1, wherein a pulse signal obtained from a retrace pulse appearing in the vertical deflection output signal is used as the pulse signal having a constant peak value.